[AMDGPU] Remove deprecated V_MUL_LO_I32 from GFX10

[Joe_Nash]

Summary

It was removed in GFX10 GPUs, but LLVM could
generate it.

[rampitec]

Generally speaking it is deprecated but it is supported. Well, not in gfx1030.

[arsenm]

Should the disassembler still understand it?

[rampitec]

In D94020#2477666, @arsenm wrote:

Should the disassembler still understand it?

I think we need to remove it from gfx1030+ only (e.g. !FeatureGFX10_3Insts).

[Joe_Nash]

remove inst from gfx1030 only, instead of all gfx10

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.td

1137

Please use GFX10_3Insts, not encoding.

[Joe_Nash]

changed B_encoding predicate to be 10_3Insts

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AMDGPU.td

def isGFX8GFX9 :
   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
   AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
 
 def isGFX10Plus :
   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
   AssemblerPredicate<(all_of FeatureGFX10Insts)>;
 
+def isGFX10Before1030 :
+  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
+            "!Subtarget->hasGFX10_3Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
+
 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
   AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
 
 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
   AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
   AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
 def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,

llvm/lib/Target/AMDGPU/VOP3Instructions.td

 } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
 
 defm V_READLANE_B32  : VOP3_Real_gfx10<0x360>;
 
 let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
 } // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
+let SubtargetPredicate = isGFX10Before1030 in {
+  defm V_MUL_LO_I32      : VOP3_Real_gfx10<0x16b>;
+}
+
 defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
 defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;
 defm V_LSHRREV_B64        : VOP3_Real_gfx10<0x300>;
 defm V_ASHRREV_I64        : VOP3_Real_gfx10<0x301>;
 defm V_PERM_B32           : VOP3_Real_gfx10<0x344>;
 defm V_XAD_U32            : VOP3_Real_gfx10<0x345>;
 defm V_LSHL_ADD_U32       : VOP3_Real_gfx10<0x346>;
 defm V_ADD_LSHL_U32       : VOP3_Real_gfx10<0x347>;
multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> :
   VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>;
 
 multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> :
   VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>;
 
 defm V_LSHL_B64        : VOP3_Real_gfx6_gfx7<0x161>;
 defm V_LSHR_B64        : VOP3_Real_gfx6_gfx7<0x162>;
 defm V_ASHR_I64        : VOP3_Real_gfx6_gfx7<0x163>;
+defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7<0x16b>;
 
 defm V_MAD_LEGACY_F32  : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
 defm V_MAD_F32         : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
 defm V_MAD_I32_I24     : VOP3_Real_gfx6_gfx7_gfx10<0x142>;
 defm V_MAD_U32_U24     : VOP3_Real_gfx6_gfx7_gfx10<0x143>;
 defm V_CUBEID_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x144>;
 defm V_CUBESC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x145>;
 defm V_CUBETC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x146>;

 defm V_DIV_FIXUP_F64   : VOP3_Real_gfx6_gfx7_gfx10<0x160>;
 defm V_ADD_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x164>;
 defm V_MUL_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x165>;
 defm V_MIN_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x166>;
 defm V_MAX_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
 defm V_LDEXP_F64       : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
 defm V_MUL_LO_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
 defm V_MUL_HI_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
-defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
 defm V_MUL_HI_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
 defm V_DIV_FMAS_F32    : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
 defm V_DIV_FMAS_F64    : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
 defm V_MSAD_U8         : VOP3_Real_gfx6_gfx7_gfx10<0x171>;
 defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>;
 defm V_TRIG_PREOP_F64  : VOP3_Real_gfx6_gfx7_gfx10<0x174>;
 defm V_DIV_SCALE_F32   : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>;
 defm V_DIV_SCALE_F64   : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;

llvm/test/MC/AMDGPU/gfx1030_unsupported.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
 
+v_mul_lo_i32 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 //===----------------------------------------------------------------------===//
 // Unsupported dpp variants.
 //===----------------------------------------------------------------------===//
 
 v_fmac_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
 
 //===----------------------------------------------------------------------===//
 // Unsupported sdwa variants.
 //===----------------------------------------------------------------------===//
 
 v_fmac_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported

llvm/test/MC/AMDGPU/gfx10_asm_vop3.s

 // GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x83,0x01,0x00]
 
 v_mul_hi_u32 v5, v1, 0.5
 // GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xe1,0x01,0x00]
 
 v_mul_hi_u32 v5, v1, -4.0
 // GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
 
+v_mul_lo_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x77,0x04,0x02,0x00]
+
 v_mul_hi_i32 v5, v1, v2
 // GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
 
 v_mul_hi_i32 v255, v1, v2
 // GFX10: encoding: [0xff,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
 
 v_mul_hi_i32 v5, v255, v2
 // GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xff,0x05,0x02,0x00]