[PowerPC] Exploitation of xxeval instruction for AND and NAND

[stefanp]

Summary

The xxeval instruction was intorduced in Power PC in Power 10.
The instruction accepts three vector registers and an immediate.
Depending on the value of the immediate the instruction can be used
to perform certain bitwise boolean operations (and, or, xor, ...) on
the given vector registers.

This patch implements the AND and NAND patterns that can be used by
the instruction.

[bsaleil]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2603

Should we add the equivalent functions from the ISA in comments next to the patterns that were simplified ? Like // nand(A,nor(B,C)) here.

[nemanjai]

LGTM as long as the test case is updated.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2584

I assume that we legalize bitwise operations on vectors by promoting everything to v4i32. If so, these patterns are perfectly fine. However, some of the test cases should use different types.

[nemanjai]

I think Baptiste's suggestion to add the expression prior to each pattern is a good idea.

[stefanp]

Updated the test case to use a multiclass and added a comment to each pattern.
Also added different types to one of the patterns.

[stefanp]

A few of the lines in the TD file were too long so I fixed that.

[bsaleil]

LGTM, just a minor comment regarding the multiclass.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2565

I think we don't need a multiclass here:

class xxevalPattern <dag pattern, bits<8> imm> :                                
  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}

2585

Then there is no need to use defm here

[NeHuang]

LGTM other than one minor can be addressed when committing.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2565

Agree with Baptiste's point above that we can use class here

[stefanp]

Changed the multiclass into class.

I will try to commit this patch on Monday if there are no further comments.

[jsji]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2569

Why xxeval needs PrefixInstrs Predicates?

2585

Can we use switch table + foreach to define all patterns?

something like:

class xxevalpat<bits<8> imm>{                                                                                                                                                 
dag pattern = !cond(!eq(imm,  1): (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),                                                                                                                  
                        !eq(imm,  6): (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))   
...                                                                                                            );                                                                                                                                                        }             


  foreach i = [1,6...] in {               
         def : xxevalPattern< xxevalpat<i>.pattern, i>;                                                                                                                            }       
  }

[stefanp]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2569

It is required because xxeval is a 64 bit prefixed instruction.

2585

Hmm... I actually feel like this would make things more confusing to read.
It is another level of indirection but in the end I am still just listing pairs of immediate values and patterns that go with them. On top of that I would have to maintain a list of values in the foreach.
I think I prefer to leave this as it stands.

[jsji]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2569

Ah.. OK. Missed that in ISA..

2585

I would have to maintain a list of values in the foreach

I think we don't, we may simple foreach 1-255, then handle the values in class.

but in the end I am still just listing pairs of immediate values and patterns that go with them.

This is just the implementation example, I was hoping that we can come up with better code that can return the pattern according to bit of imm.

But yeah, this is nice to have.

[jsji]

Thanks , LGTM as it is per discussion.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let AddedComplexity = 400, Predicates = [IsISA3_1] in {
   def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$rS, 0)), xoaddr:$src),
             (STXVRHX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
   def : Pat<(store (i32 (vector_extract v4i32:$rS, 0)), xoaddr:$src),
             (STXVRWX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
   def : Pat<(store (i64 (vector_extract v2i64:$rS, 0)), xoaddr:$src),
             (STXVRDX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
 }
 
+multiclass xxevalPattern <dag pattern, bits<8> imm> {
+  def : Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)>;
+}
+
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A)),
            (v4i32 (XXSPLTIW imm:$A))>;
  def : Pat<(f32 nzFPImmAsi32:$A),
            (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
                              VSFRC)>;
  def : Pat<(f64 nzFPImmAsi32:$A),
            (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
                              VSFRC)>;
+
+  // Anonymous patterns for XXEVAL
+  // AND
+  // and(A, B, C)
+  defm : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
+  // and(A, xor(B, C))
+  defm : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
+  // and(A, or(B, C))
+  defm : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
+  // and(A, nor(B, C))
+  defm : xxevalPattern<(and v4i32:$vA, (vnot_ppc (or v4i32:$vB, v4i32:$vC))),
+                       8>;
+  // and(A, eqv(B, C))
+  defm : xxevalPattern<(and v4i32:$vA, (vnot_ppc (xor v4i32:$vB, v4i32:$vC))),
+                       9>;
+  // and(A, nand(B, C))
+  defm : xxevalPattern<(and v4i32:$vA, (vnot_ppc (and v4i32:$vB, v4i32:$vC))),
+                       14>;
+
+  // NAND
+  // nand(A, B, C)
+  defm : xxevalPattern<(vnot_ppc (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
+                       !sub(255, 1)>;
+  // nand(A, xor(B, C))
+  defm : xxevalPattern<(vnot_ppc (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
+                       !sub(255, 6)>;
+  // nand(A, or(B, C))
+  defm : xxevalPattern<(vnot_ppc (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
+                       !sub(255, 7)>;
+  // nand(A, nor(B, C))
+  defm : xxevalPattern<(or (vnot_ppc v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
+                       !sub(255, 8)>;
+  // nand(A, eqv(B, C))
+  defm : xxevalPattern<(or (vnot_ppc v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
+                       !sub(255, 9)>;
+  // nand(A, nand(B, C))
+  defm : xxevalPattern<(or (vnot_ppc v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
+                       !sub(255, 14)>;
 }
 
 let Predicates = [PrefixInstrs] in {
   def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
             (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
                                        (COPY_TO_REGCLASS $B, VSRC),
                                        (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
   def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),

llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_not
+; CHECK:         xxlandc v2, v2, v3
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_and8
+; CHECK:         xxeval v2, v3, v2, v4, 1
+; CHECK-NEXT:    blr
+define dso_local <16 x i8> @and_and8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <16 x i8> %B, %A
+  %and1 = and <16 x i8> %and, %C
+  ret <16 x i8> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_and16
+; CHECK:         xxeval v2, v3, v2, v4, 1
+; CHECK-NEXT:    blr
+define dso_local <8 x i16> @and_and16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <8 x i16> %B, %A
+  %and1 = and <8 x i16> %and, %C
+  ret <8 x i16> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_and32
+; CHECK:         xxeval v2, v3, v2, v4, 1
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_and32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %B, %A
+  %and1 = and <4 x i32> %and, %C
+  ret <4 x i32> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_and64
+; CHECK:         xxeval v2, v3, v2, v4, 1
+; CHECK-NEXT:    blr
+define dso_local <2 x i64> @and_and64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <2 x i64> %B, %A
+  %and1 = and <2 x i64> %and, %C
+  ret <2 x i64> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_nand
+; CHECK:         xxeval v2, v2, v4, v3, 14
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %C, %B
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and1 = and <4 x i32> %neg, %A
+  ret <4 x i32> %and1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_or
+; CHECK:         xxeval v2, v2, v4, v3, 7
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %and = and <4 x i32> %or, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_nor
+; CHECK:         xxeval v2, v2, v4, v3, 8
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_xor
+; CHECK:         xxeval v2, v2, v4, v3, 6
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %and = and <4 x i32> %xor, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: and_eqv
+; CHECK:         xxeval v2, v2, v3, v4, 9
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg = xor <4 x i32> %xor, %C
+  %and = and <4 x i32> %neg, %A
+  ret <4 x i32> %and
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_nand
+; CHECK:         xxeval v2, v2, v4, v3, 241
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %C, %B
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg2 = or <4 x i32> %and, %A.not
+  ret <4 x i32> %neg2
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_and
+; CHECK:         xxeval v2, v3, v2, v4, 254
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %and = and <4 x i32> %B, %A
+  %and1 = and <4 x i32> %and, %C
+  %neg = xor <4 x i32> %and1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_xor
+; CHECK:         xxeval v2, v2, v4, v3, 249
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %and = and <4 x i32> %xor, %A
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_eqv
+; CHECK:         xxeval v2, v2, v4, v3, 246
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %xor = xor <4 x i32> %C, %B
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %neg1 = or <4 x i32> %xor, %A.not
+  ret <4 x i32> %neg1
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_or
+; CHECK:         xxeval v2, v2, v4, v3, 248
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %or = or <4 x i32> %C, %B
+  %and = and <4 x i32> %or, %A
+  %neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %neg
+}
+
+; Function Attrs: nounwind
+; CHECK-LABEL: nand_nor
+; CHECK:         xxeval v2, v2, v3, v4, 247
+; CHECK-NEXT:    blr
+define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+  %A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %or = or <4 x i32> %A.not, %B
+  %neg1 = or <4 x i32> %or, %C
+  ret <4 x i32> %neg1
+}
+
+attributes #0 = { nounwind }