[PowerPC] Support f128 under VSX

[qiucf]

Summary

This patch is the last one in backend to support fp128 type in pre-Power9 subtargets, removing temporary option and updating remaining tests.

[qiucf]

Since we change the requirement from Altivec to VSX, is this patch still relevant?

[qiucf]

Change requirement from Altivec to VSX to align with GCC behavior.

[steven.zhang]

LGTM. But please do a complete test before enabling it by default.

[qiucf]

Rebase

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
 
 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
 cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
 
 static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
 cl::desc("use absolute jump tables on ppc"), cl::Hidden);
 
-// TODO - Remove this option if soft fp128 has been fully supported .
-static cl::opt<bool>
-    EnableSoftFP128("enable-soft-fp128",
-                    cl::desc("temp option to enable soft fp128"), cl::Hidden);
-
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
 STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
 STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
 
 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
 
 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);

       setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FCEIL,  MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
+      addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
+
+      for (MVT FPT : MVT::fp_valuetypes())
+        setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
+
+      // Expand the SELECT to SELECT_CC
+      setOperationAction(ISD::SELECT, MVT::f128, Expand);
+
+      setTruncStoreAction(MVT::f128, MVT::f64, Expand);
+      setTruncStoreAction(MVT::f128, MVT::f32, Expand);
+
+      // No implementation for these ops for PowerPC.
+      setOperationAction(ISD::FSIN, MVT::f128, Expand);
+      setOperationAction(ISD::FCOS, MVT::f128, Expand);
+      setOperationAction(ISD::FPOW, MVT::f128, Expand);
+      setOperationAction(ISD::FPOWI, MVT::f128, Expand);
+      setOperationAction(ISD::FREM, MVT::f128, Expand);
     }
 
     if (Subtarget.hasP8Altivec()) {
       addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
       addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
     }
 
     if (Subtarget.hasP9Vector()) {
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
 
       // 128 bit shifts can be accomplished via 3 instructions for SHL and
       // SRL, but not for SRA because of the instructions available:
       // VS{RL} and VS{RL}O.
       setOperationAction(ISD::SHL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
-      addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
       setOperationAction(ISD::FADD, MVT::f128, Legal);
       setOperationAction(ISD::FSUB, MVT::f128, Legal);
       setOperationAction(ISD::FDIV, MVT::f128, Legal);
       setOperationAction(ISD::FMUL, MVT::f128, Legal);
       setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
-      // No extending loads to f128 on PPC.
-      for (MVT FPT : MVT::fp_valuetypes())
-        setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
+
       setOperationAction(ISD::FMA, MVT::f128, Legal);
       setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
       setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
       setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
       setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
       setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
       setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
 
       setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
       setOperationAction(ISD::FRINT, MVT::f128, Legal);
       setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
       setOperationAction(ISD::FCEIL, MVT::f128, Legal);
       setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
       setOperationAction(ISD::FROUND, MVT::f128, Legal);
 
-      setOperationAction(ISD::SELECT, MVT::f128, Expand);
       setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
       setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
-      setTruncStoreAction(MVT::f128, MVT::f64, Expand);
-      setTruncStoreAction(MVT::f128, MVT::f32, Expand);
       setOperationAction(ISD::BITCAST, MVT::i128, Custom);
-      // No implementation for these ops for PowerPC.
-      setOperationAction(ISD::FSIN, MVT::f128, Expand);
-      setOperationAction(ISD::FCOS, MVT::f128, Expand);
-      setOperationAction(ISD::FPOW, MVT::f128, Expand);
-      setOperationAction(ISD::FPOWI, MVT::f128, Expand);
-      setOperationAction(ISD::FREM, MVT::f128, Expand);
 
       // Handle constrained floating-point operations of fp128
       setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
       setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
       setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
       setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
       setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
       setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
       setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
       setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
-    } else if (Subtarget.hasAltivec() && EnableSoftFP128) {
-      addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
-
-      for (MVT FPT : MVT::fp_valuetypes())
-        setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
-
+    } else if (Subtarget.hasVSX()) {
       setOperationAction(ISD::LOAD, MVT::f128, Promote);
       setOperationAction(ISD::STORE, MVT::f128, Promote);
 
       AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
       AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
 
       // Set FADD/FSUB as libcall to avoid the legalizer to expand the
       // fp_to_uint and int_to_fp.
       setOperationAction(ISD::FADD, MVT::f128, LibCall);
       setOperationAction(ISD::FSUB, MVT::f128, LibCall);
 
       setOperationAction(ISD::FMUL, MVT::f128, Expand);
       setOperationAction(ISD::FDIV, MVT::f128, Expand);
       setOperationAction(ISD::FNEG, MVT::f128, Expand);
       setOperationAction(ISD::FABS, MVT::f128, Expand);
-      setOperationAction(ISD::FSIN, MVT::f128, Expand);
-      setOperationAction(ISD::FCOS, MVT::f128, Expand);
-      setOperationAction(ISD::FPOW, MVT::f128, Expand);
-      setOperationAction(ISD::FPOWI, MVT::f128, Expand);
-      setOperationAction(ISD::FREM, MVT::f128, Expand);
       setOperationAction(ISD::FSQRT, MVT::f128, Expand);
       setOperationAction(ISD::FMA, MVT::f128, Expand);
       setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
 
-      setTruncStoreAction(MVT::f128, MVT::f64, Expand);
-      setTruncStoreAction(MVT::f128, MVT::f32, Expand);
-
       // Expand the fp_extend if the target type is fp128.
       setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
       setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
 
       // Expand the fp_round if the source type is fp128.
       for (MVT VT : {MVT::f32, MVT::f64}) {
         setOperationAction(ISD::FP_ROUND, VT, Custom);
         setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);

   if (!isTypeLegal(ResVT))
     return SDValue();
 
   // Only perform combine for conversion to i64/i32 or power9 i16/i8.
   bool ValidTypeForStoreFltAsInt =
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
+  if (ResVT == MVT::f128 && !Subtarget.hasP9Vector())
+    return SDValue();
+
   if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
     return SDValue();
 
   // Extend f32 values to f64
   if (ResVT.getScalarSizeInBits() == 32) {
     Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
     DCI.AddToWorklist(Val.getNode());

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

 ;
 ; CHECK-BE-LABEL: testArray_01:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testArray_01:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    ld r5, 32(r3)
-; CHECK-P8-NEXT:    ld r4, 40(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r3, r3, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
   %0 = load fp128, fp128* %arrayidx, align 16
   ret fp128 %0
 }
 

 ; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxv v2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testArray_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r3, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r3)
-; CHECK-P8-NEXT:    ld r3, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
+; CHECK-P8-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-P8-NEXT:    addi r3, r3, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
                                                   i64 0, i64 2), align 16
   ret fp128 %0
 }
 

 ;
 ; CHECK-BE-LABEL: testStruct_02:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vmr v2, v9
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_02:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    ld r3, 144(r1)
-; CHECK-P8-NEXT:    ld r4, 152(r1)
+; CHECK-P8-NEXT:    vmr v2, v9
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
   ret fp128 %a.coerce.fca.7.extract
 }
 
 ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we

 ; CHECK-BE-NEXT:    std r7, 80(r1)
 ; CHECK-BE-NEXT:    std r8, 88(r1)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_03:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    ld r11, 128(r1)
-; CHECK-P8-NEXT:    ld r12, 136(r1)
+; CHECK-P8-NEXT:    li r11, 96
+; CHECK-P8-NEXT:    addi r12, r1, 32
 ; CHECK-P8-NEXT:    std r3, 32(r1)
 ; CHECK-P8-NEXT:    std r4, 40(r1)
 ; CHECK-P8-NEXT:    std r5, 48(r1)
 ; CHECK-P8-NEXT:    std r6, 56(r1)
-; CHECK-P8-NEXT:    mr r3, r11
-; CHECK-P8-NEXT:    mr r4, r12
+; CHECK-P8-NEXT:    lvx v2, r12, r11
 ; CHECK-P8-NEXT:    std r7, 64(r1)
 ; CHECK-P8-NEXT:    std r8, 72(r1)
 ; CHECK-P8-NEXT:    std r9, 80(r1)
 ; CHECK-P8-NEXT:    std r10, 88(r1)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a7 = getelementptr inbounds %struct.With9fp128params,

 ;
 ; CHECK-BE-LABEL: testStruct_04:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vmr v2, v5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testStruct_04:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r10
-; CHECK-P8-NEXT:    mr r3, r9
+; CHECK-P8-NEXT:    vmr v2, v5
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
   ret fp128 %a.coerce.fca.3.extract
 }
 
 ; Function Attrs: norecurse nounwind readnone

 ;
 ; CHECK-BE-LABEL: testHUnion_03:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vmr v2, v3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testHUnion_03:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r6
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    vmr v2, v3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1
   ret fp128 %a.coerce.fca.1.extract
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testHUnion_04([3 x fp128] %a.coerce) {
 ; CHECK-LABEL: testHUnion_04:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmr v2, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testHUnion_04:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vmr v2, v4
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testHUnion_04:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r8
-; CHECK-P8-NEXT:    mr r3, r7
+; CHECK-P8-NEXT:    vmr v2, v4
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2
   ret fp128 %a.coerce.fca.2.extract
 }
 
 ; Testing mixed member aggregates.

 ;
 ; CHECK-BE-LABEL: testMixedAggregate:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r8
-; CHECK-P8-NEXT:    mr r3, r7
+; CHECK-P8-NEXT:    addi r3, r1, -16
+; CHECK-P8-NEXT:    std r8, -8(r1)
+; CHECK-P8-NEXT:    std r7, -16(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
   %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
 ; CHECK-LABEL: testMixedAggregate_02:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd v2, r6, r5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testMixedAggregate_02:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrdd v2, r6, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate_02:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r6
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r3, r1, -16
+; CHECK-P8-NEXT:    std r6, -8(r1)
+; CHECK-P8-NEXT:    std r5, -16(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
   %0 = bitcast i128 %a.coerce.fca.1.extract to fp128
   ret fp128 %0
 }
 

 ; CHECK-BE-NEXT:    mtvsrd v3, r9
 ; CHECK-BE-NEXT:    xscvsdqp v3, v3
 ; CHECK-BE-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testMixedAggregate_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -96(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r4, 64
+; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    mr r30, r10
-; CHECK-P8-NEXT:    mr r29, r6
-; CHECK-P8-NEXT:    mr r28, r5
+; CHECK-P8-NEXT:    stvx v31, r1, r4 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    addi r4, r1, 48
+; CHECK-P8-NEXT:    std r6, 56(r1)
+; CHECK-P8-NEXT:    std r5, 48(r1)
+; CHECK-P8-NEXT:    lvx v31, 0, r4
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r28
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r29, r3
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r28, r4
+; CHECK-P8-NEXT:    vmr v31, v2
 ; CHECK-P8-NEXT:    bl __floatdikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r29
-; CHECK-P8-NEXT:    mr r4, r28
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 64
+; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
   %sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
   %sa.coerce.fca.1.extract = extractvalue [4 x i128] %sa.coerce, 1
   %sa.coerce.fca.3.extract = extractvalue [4 x i128] %sa.coerce, 3
   %sa.sroa.6.48.extract.shift = lshr i128 %sa.coerce.fca.3.extract, 64

 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testNestedAggregate:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    std r3, 32(r1)
-; CHECK-P8-NEXT:    std r4, 40(r1)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    mr r4, r8
+; CHECK-P8-NEXT:    li r11, 32
 ; CHECK-P8-NEXT:    std r8, 72(r1)
 ; CHECK-P8-NEXT:    std r7, 64(r1)
-; CHECK-P8-NEXT:    std r5, 48(r1)
-; CHECK-P8-NEXT:    std r6, 56(r1)
 ; CHECK-P8-NEXT:    std r9, 80(r1)
 ; CHECK-P8-NEXT:    std r10, 88(r1)
+; CHECK-P8-NEXT:    addi r7, r1, 32
+; CHECK-P8-NEXT:    lvx v2, r7, r11
+; CHECK-P8-NEXT:    std r3, 32(r1)
+; CHECK-P8-NEXT:    std r4, 40(r1)
+; CHECK-P8-NEXT:    std r5, 48(r1)
+; CHECK-P8-NEXT:    std r6, 56(r1)
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
   %0 = load fp128, fp128* %c, align 16
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_01([1 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_01:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd v2, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_01:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_01:
 ; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addi r5, r1, -16
+; CHECK-P8-NEXT:    std r4, -8(r1)
+; CHECK-P8-NEXT:    std r3, -16(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r5
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
   %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_02([1 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_02:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd v2, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_02:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_02:
 ; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addi r5, r1, -16
+; CHECK-P8-NEXT:    std r4, -8(r1)
+; CHECK-P8-NEXT:    std r3, -16(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r5
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
   %0 = bitcast i128 %a.coerce.fca.0.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @testUnion_03([4 x i128] %a.coerce) {
 ; CHECK-LABEL: testUnion_03:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd v2, r8, r7
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testUnion_03:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrdd v2, r8, r7
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testUnion_03:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r4, r8
-; CHECK-P8-NEXT:    mr r3, r7
+; CHECK-P8-NEXT:    addi r3, r1, -16
+; CHECK-P8-NEXT:    std r8, -8(r1)
+; CHECK-P8-NEXT:    std r7, -16(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 
 entry:
   %a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
   %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
   ret fp128 %0
 }
 

 ; CHECK-BE-NEXT:    xsaddqp v2, v3, v2
 ; CHECK-BE-NEXT:    lxv v3, 16(r3)
 ; CHECK-BE-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: sum_float128:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    addis r11, r2, .LCPI17_0@toc@ha
 ; CHECK-P8-NEXT:    cmpwi r3, 1
-; CHECK-P8-NEXT:    std r4, 88(r1)
-; CHECK-P8-NEXT:    std r5, 96(r1)
-; CHECK-P8-NEXT:    std r6, 104(r1)
-; CHECK-P8-NEXT:    std r7, 112(r1)
-; CHECK-P8-NEXT:    std r8, 120(r1)
-; CHECK-P8-NEXT:    std r9, 128(r1)
-; CHECK-P8-NEXT:    std r10, 136(r1)
+; CHECK-P8-NEXT:    std r4, 104(r1)
+; CHECK-P8-NEXT:    std r5, 112(r1)
+; CHECK-P8-NEXT:    std r6, 120(r1)
+; CHECK-P8-NEXT:    std r7, 128(r1)
+; CHECK-P8-NEXT:    addi r3, r11, .LCPI17_0@toc@l
+; CHECK-P8-NEXT:    std r8, 136(r1)
+; CHECK-P8-NEXT:    std r9, 144(r1)
+; CHECK-P8-NEXT:    std r10, 152(r1)
 ; CHECK-P8-NEXT:    blt cr0, .LBB17_2
 ; CHECK-P8-NEXT:  # %bb.1: # %if.end
-; CHECK-P8-NEXT:    ld r3, 88(r1)
-; CHECK-P8-NEXT:    ld r4, 96(r1)
-; CHECK-P8-NEXT:    li r5, 0
-; CHECK-P8-NEXT:    li r6, 0
+; CHECK-P8-NEXT:    addi r30, r1, 104
+; CHECK-P8-NEXT:    lvx v3, 0, r3
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r30
+; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 104(r1)
-; CHECK-P8-NEXT:    ld r6, 112(r1)
-; CHECK-P8-NEXT:    addi r7, r1, 120
-; CHECK-P8-NEXT:    std r7, 40(r1)
+; CHECK-P8-NEXT:    li r3, 16
+; CHECK-P8-NEXT:    lxvd2x vs0, r30, r3
+; CHECK-P8-NEXT:    addi r3, r1, 136
+; CHECK-P8-NEXT:    std r3, 40(r1)
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    b .LBB17_3
 ; CHECK-P8-NEXT:  .LBB17_2:
-; CHECK-P8-NEXT:    li r3, 0
-; CHECK-P8-NEXT:    li r4, 0
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:  .LBB17_3: # %cleanup
-; CHECK-P8-NEXT:    addi r1, r1, 48
+; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %ap = alloca i8*, align 8
   %0 = bitcast i8** %ap to i8*
   call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2
   %cmp = icmp slt i32 %count, 1
   br i1 %cmp, label %cleanup, label %if.end

llvm/test/CodeGen/PowerPC/f128-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
-; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -enable-soft-fp128 | FileCheck %s \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 ; Function Attrs: norecurse nounwind
 define dso_local void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpAdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v2

llvm/test/CodeGen/PowerPC/f128-bitcast.ll

 ;
 ; CHECK-BE-LABEL: getPart1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrld r3, v2
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: getPart1:
 ; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    xxswapd vs0, v2
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = bitcast fp128 %in to i128
   %a.sroa.0.0.extract.trunc = trunc i128 %0 to i64
   ret i64 %a.sroa.0.0.extract.trunc
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getPart2(fp128 %in) local_unnamed_addr {
 ; CHECK-LABEL: getPart2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: getPart2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: getPart2:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mr r3, r4
+; CHECK-P8-NEXT:    mfvsrd r3, v2
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = bitcast fp128 %in to i128
   %a.sroa.0.8.extract.shift = lshr i128 %0, 64
   %a.sroa.0.8.extract.trunc = trunc i128 %a.sroa.0.8.extract.shift to i64
   ret i64 %a.sroa.0.8.extract.trunc
 }
 

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    vaddudm v2, v2, v3
 ; CHECK-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: checkBitcast:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtfprd f0, r3
-; CHECK-P8-NEXT:    mtfprd f1, r4
-; CHECK-P8-NEXT:    xxmrghd v3, vs1, vs0
-; CHECK-P8-NEXT:    xxswapd vs0, v3
-; CHECK-P8-NEXT:    vaddudm v2, v3, v2
+; CHECK-P8-NEXT:    xxswapd vs0, v2
+; CHECK-P8-NEXT:    vaddudm v2, v2, v3
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r7
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = bitcast fp128 %in to <2 x i64>
   %1 = extractelement <2 x i64> %0, i64 0
   %2 = add <2 x i64> %0, %in2
   store <2 x i64> %2, <2 x i64> *%out, align 16
   ret i64 %1
 }
 

llvm/test/CodeGen/PowerPC/f128-compare.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
-; RUN:   -enable-soft-fp128 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 @a_qp = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 @b_qp = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local signext i32 @greater_qp() {
 ; CHECK-LABEL: greater_qp:

llvm/test/CodeGen/PowerPC/f128-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -verify-machineinstrs -ppc-asm-full-reg-names < %s \
 ; RUN:   | FileCheck %s
 ; RUN: llc -relocation-model=pic -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -verify-machineinstrs -ppc-asm-full-reg-names < %s \
-; RUN:   -enable-soft-fp128 | FileCheck %s -check-prefix=CHECK-P8
+; RUN:   | FileCheck %s -check-prefix=CHECK-P8
 
 @mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
 @swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
 @ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
 

llvm/test/CodeGen/PowerPC/f128-fma.ll

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsmaddqp v4, v2, v3
 ; CHECK-NEXT:    stxv v4, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmadd:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r8, 8(r3)
-; CHECK-P8-NEXT:    ld r9, 0(r4)
-; CHECK-P8-NEXT:    ld r10, 8(r4)
-; CHECK-P8-NEXT:    mr r28, r6
-; CHECK-P8-NEXT:    ld r30, 0(r5)
-; CHECK-P8-NEXT:    ld r29, 8(r5)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    mr r4, r8
-; CHECK-P8-NEXT:    mr r5, r9
-; CHECK-P8-NEXT:    mr r6, r10
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r6
+; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r5
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r30
-; CHECK-P8-NEXT:    mr r6, r29
+; CHECK-P8-NEXT:    vmr v3, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    std r4, 8(r28)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                    fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2)

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsmaddqp v2, v3, v4
 ; CHECK-NEXT:    stxv v2, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmadd_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r7, 0(r5)
-; CHECK-P8-NEXT:    ld r8, 8(r5)
-; CHECK-P8-NEXT:    ld r30, 0(r3)
-; CHECK-P8-NEXT:    ld r29, 8(r3)
-; CHECK-P8-NEXT:    mr r28, r6
-; CHECK-P8-NEXT:    ld r3, 0(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r4)
-; CHECK-P8-NEXT:    mr r5, r7
-; CHECK-P8-NEXT:    mr r6, r8
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lvx v2, 0, r4
+; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r6
+; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r3
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    std r4, 8(r28)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                         fp128* nocapture readonly %b,
                         fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16

 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r6
-; CHECK-P8-NEXT:    ld r6, 8(r4)
 ; CHECK-P8-NEXT:    mr r29, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 0(r29)
-; CHECK-P8-NEXT:    ld r6, 8(r29)
+; CHECK-P8-NEXT:    lvx v3, 0, r29
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    std r4, 8(r30)
+; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                         fp128* nocapture readonly %b,
                         fp128* nocapture readonly %c, fp128* nocapture %res) {

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsnmaddqp v2, v3, v4
 ; CHECK-NEXT:    stxv v2, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmadd:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -96(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r7, 0(r5)
-; CHECK-P8-NEXT:    ld r8, 8(r5)
-; CHECK-P8-NEXT:    ld r30, 0(r3)
-; CHECK-P8-NEXT:    ld r29, 8(r3)
-; CHECK-P8-NEXT:    mr r28, r6
-; CHECK-P8-NEXT:    ld r3, 0(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r4)
-; CHECK-P8-NEXT:    mr r5, r7
-; CHECK-P8-NEXT:    mr r6, r8
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r7, 64
+; CHECK-P8-NEXT:    lvx v2, 0, r4
+; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r6
+; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r3
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
-; CHECK-P8-NEXT:    xor r4, r4, r5
-; CHECK-P8-NEXT:    std r4, 8(r28)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    addi r3, r1, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 63(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 63(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    li r3, 64
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsnmaddqp v4, v2, v3
 ; CHECK-NEXT:    stxv v4, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmadd_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r6
-; CHECK-P8-NEXT:    ld r6, 8(r4)
 ; CHECK-P8-NEXT:    mr r29, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 0(r29)
-; CHECK-P8-NEXT:    ld r6, 8(r29)
+; CHECK-P8-NEXT:    lvx v3, 0, r29
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
-; CHECK-P8-NEXT:    xor r4, r4, r5
-; CHECK-P8-NEXT:    std r4, 8(r30)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    addi r3, r1, 32
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 47(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 47(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsnmsubqp v2, v3, v4
 ; CHECK-NEXT:    stxv v2, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFmsub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r7, 0(r5)
-; CHECK-P8-NEXT:    ld r8, 8(r5)
-; CHECK-P8-NEXT:    ld r30, 0(r3)
-; CHECK-P8-NEXT:    ld r29, 8(r3)
-; CHECK-P8-NEXT:    mr r28, r6
-; CHECK-P8-NEXT:    ld r3, 0(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r4)
-; CHECK-P8-NEXT:    mr r5, r7
-; CHECK-P8-NEXT:    mr r6, r8
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lvx v2, 0, r4
+; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r6
+; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r3
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    std r4, 8(r28)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16

 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r6
-; CHECK-P8-NEXT:    ld r6, 8(r4)
 ; CHECK-P8-NEXT:    mr r29, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 0(r29)
-; CHECK-P8-NEXT:    ld r6, 8(r29)
+; CHECK-P8-NEXT:    lvx v3, 0, r29
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    std r4, 8(r30)
+; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {

 ; CHECK-NEXT:    xsnegqp v3, v3
 ; CHECK-NEXT:    xsnmaddqp v2, v3, v4
 ; CHECK-NEXT:    stxv v2, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmsub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -96(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r7, 0(r5)
-; CHECK-P8-NEXT:    ld r8, 8(r5)
-; CHECK-P8-NEXT:    ld r30, 0(r3)
-; CHECK-P8-NEXT:    ld r29, 8(r3)
-; CHECK-P8-NEXT:    mr r28, r6
-; CHECK-P8-NEXT:    ld r3, 0(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r4)
-; CHECK-P8-NEXT:    mr r5, r7
-; CHECK-P8-NEXT:    mr r6, r8
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r7, 64
+; CHECK-P8-NEXT:    lvx v2, 0, r4
+; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r6
+; CHECK-P8-NEXT:    stvx v31, r1, r7 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r3
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    std r3, 0(r28)
-; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
-; CHECK-P8-NEXT:    xor r4, r4, r5
-; CHECK-P8-NEXT:    std r4, 8(r28)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    addi r3, r1, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 63(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 63(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    li r3, 64
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsnmsubqp v4, v2, v3
 ; CHECK-NEXT:    stxv v4, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpFnmsub_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r6
-; CHECK-P8-NEXT:    ld r6, 8(r4)
 ; CHECK-P8-NEXT:    mr r29, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 0(r29)
-; CHECK-P8-NEXT:    ld r6, 8(r29)
+; CHECK-P8-NEXT:    lvx v3, 0, r29
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    std r3, 0(r30)
-; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
-; CHECK-P8-NEXT:    xor r4, r4, r5
-; CHECK-P8-NEXT:    std r4, 8(r30)
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    addi r3, r1, 32
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 47(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 47(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                       fp128* nocapture readonly %b,
                       fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
 ; CHECK-NEXT:    lxvx v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: loadConstant:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    lis r3, 1
-; CHECK-P8-NEXT:    ori r3, r3, 5
-; CHECK-P8-NEXT:    rldic r4, r3, 46, 1
-; CHECK-P8-NEXT:    li r3, 0
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
   entry:
     ret fp128 0xL00000000000000004001400000000000
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant2(fp128 %a, fp128 %b) {
 ; CHECK-LABEL: loadConstant2:

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    lis r5, 1
-; CHECK-P8-NEXT:    ori r5, r5, 5
-; CHECK-P8-NEXT:    rldic r6, r5, 46, 1
-; CHECK-P8-NEXT:    li r5, 0
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
   entry:
     %add = fadd fp128 %a, %b

 ; CHECK-P8-LABEL: fp128Array:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    sldi r4, r4, 4
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    add r6, r3, r4
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    ld r5, -16(r6)
-; CHECK-P8-NEXT:    ld r6, -8(r6)
-; CHECK-P8-NEXT:    mr r3, r7
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    add r4, r3, r4
+; CHECK-P8-NEXT:    addi r4, r4, -16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                          i32 signext %loopcnt, fp128* nocapture readnone %sum) {
 entry:

 ; CHECK-NEXT:    xsaddqp v2, v2, v12
 ; CHECK-NEXT:    xsaddqp v2, v2, v13
 ; CHECK-NEXT:    xssubqp v2, v2, v0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: maxVecParam:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 208
-; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r14, -144
-; CHECK-P8-NEXT:    .cfi_offset r15, -136
-; CHECK-P8-NEXT:    .cfi_offset r16, -128
-; CHECK-P8-NEXT:    .cfi_offset r17, -120
-; CHECK-P8-NEXT:    .cfi_offset r18, -112
-; CHECK-P8-NEXT:    .cfi_offset r19, -104
-; CHECK-P8-NEXT:    .cfi_offset r20, -96
-; CHECK-P8-NEXT:    .cfi_offset r21, -88
-; CHECK-P8-NEXT:    .cfi_offset r22, -80
-; CHECK-P8-NEXT:    .cfi_offset r23, -72
-; CHECK-P8-NEXT:    .cfi_offset r24, -64
-; CHECK-P8-NEXT:    .cfi_offset r25, -56
-; CHECK-P8-NEXT:    .cfi_offset r26, -48
-; CHECK-P8-NEXT:    .cfi_offset r27, -40
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
-; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    .cfi_offset r31, -8
-; CHECK-P8-NEXT:    std r14, -144(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r16, -128(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r17, -120(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r18, -112(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r19, -104(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r20, -96(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r21, -88(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r22, -80(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r23, -72(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r24, -64(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r25, -56(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r31, -8(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -208(r1)
-; CHECK-P8-NEXT:    mr r17, r7
-; CHECK-P8-NEXT:    ld r7, 432(r1)
-; CHECK-P8-NEXT:    ld r26, 400(r1)
-; CHECK-P8-NEXT:    ld r25, 408(r1)
-; CHECK-P8-NEXT:    ld r24, 384(r1)
-; CHECK-P8-NEXT:    mr r20, r10
-; CHECK-P8-NEXT:    ld r23, 392(r1)
-; CHECK-P8-NEXT:    ld r22, 368(r1)
-; CHECK-P8-NEXT:    ld r21, 376(r1)
-; CHECK-P8-NEXT:    ld r16, 352(r1)
-; CHECK-P8-NEXT:    mr r19, r9
-; CHECK-P8-NEXT:    mr r18, r8
-; CHECK-P8-NEXT:    ld r15, 360(r1)
-; CHECK-P8-NEXT:    ld r14, 336(r1)
-; CHECK-P8-NEXT:    ld r31, 344(r1)
-; CHECK-P8-NEXT:    ld r30, 320(r1)
-; CHECK-P8-NEXT:    std r7, 56(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    ld r7, 440(r1)
-; CHECK-P8-NEXT:    ld r29, 328(r1)
-; CHECK-P8-NEXT:    ld r28, 304(r1)
-; CHECK-P8-NEXT:    ld r27, 312(r1)
-; CHECK-P8-NEXT:    std r7, 48(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    ld r7, 416(r1)
-; CHECK-P8-NEXT:    std r7, 40(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    ld r7, 424(r1)
-; CHECK-P8-NEXT:    std r7, 32(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    stdu r1, -224(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 224
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset v21, -176
+; CHECK-P8-NEXT:    .cfi_offset v22, -160
+; CHECK-P8-NEXT:    .cfi_offset v23, -144
+; CHECK-P8-NEXT:    .cfi_offset v24, -128
+; CHECK-P8-NEXT:    .cfi_offset v25, -112
+; CHECK-P8-NEXT:    .cfi_offset v26, -96
+; CHECK-P8-NEXT:    .cfi_offset v27, -80
+; CHECK-P8-NEXT:    .cfi_offset v28, -64
+; CHECK-P8-NEXT:    .cfi_offset v29, -48
+; CHECK-P8-NEXT:    .cfi_offset v30, -32
+; CHECK-P8-NEXT:    .cfi_offset v31, -16
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stvx v21, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 64
+; CHECK-P8-NEXT:    vmr v21, v4
+; CHECK-P8-NEXT:    stvx v22, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 80
+; CHECK-P8-NEXT:    vmr v22, v5
+; CHECK-P8-NEXT:    stvx v23, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 96
+; CHECK-P8-NEXT:    vmr v23, v6
+; CHECK-P8-NEXT:    stvx v24, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 112
+; CHECK-P8-NEXT:    vmr v24, v7
+; CHECK-P8-NEXT:    stvx v25, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 128
+; CHECK-P8-NEXT:    vmr v25, v8
+; CHECK-P8-NEXT:    stvx v26, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 144
+; CHECK-P8-NEXT:    vmr v26, v9
+; CHECK-P8-NEXT:    stvx v27, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 160
+; CHECK-P8-NEXT:    vmr v27, v10
+; CHECK-P8-NEXT:    stvx v28, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 176
+; CHECK-P8-NEXT:    vmr v28, v11
+; CHECK-P8-NEXT:    stvx v29, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 192
+; CHECK-P8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    li r3, 208
+; CHECK-P8-NEXT:    vmr v30, v12
+; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    addi r3, r1, 448
+; CHECK-P8-NEXT:    vmr v31, v13
+; CHECK-P8-NEXT:    lvx v29, 0, r3
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r17
-; CHECK-P8-NEXT:    mr r6, r18
+; CHECK-P8-NEXT:    vmr v3, v21
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r19
-; CHECK-P8-NEXT:    mr r6, r20
+; CHECK-P8-NEXT:    vmr v3, v22
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r28
-; CHECK-P8-NEXT:    mr r6, r27
+; CHECK-P8-NEXT:    vmr v3, v23
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r30
-; CHECK-P8-NEXT:    mr r6, r29
+; CHECK-P8-NEXT:    vmr v3, v24
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r14
-; CHECK-P8-NEXT:    mr r6, r31
+; CHECK-P8-NEXT:    vmr v3, v25
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r16
-; CHECK-P8-NEXT:    mr r6, r15
+; CHECK-P8-NEXT:    vmr v3, v26
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r22
-; CHECK-P8-NEXT:    mr r6, r21
+; CHECK-P8-NEXT:    vmr v3, v27
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r24
-; CHECK-P8-NEXT:    mr r6, r23
+; CHECK-P8-NEXT:    vmr v3, v28
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r26
-; CHECK-P8-NEXT:    mr r6, r25
+; CHECK-P8-NEXT:    vmr v3, v30
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 40(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r6, 32(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    vmr v3, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    ld r5, 56(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r6, 48(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    vmr v3, v29
 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 208
+; CHECK-P8-NEXT:    li r3, 208
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 192
+; CHECK-P8-NEXT:    lvx v30, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 176
+; CHECK-P8-NEXT:    lvx v29, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 160
+; CHECK-P8-NEXT:    lvx v28, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 144
+; CHECK-P8-NEXT:    lvx v27, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 128
+; CHECK-P8-NEXT:    lvx v26, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 112
+; CHECK-P8-NEXT:    lvx v25, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 96
+; CHECK-P8-NEXT:    lvx v24, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 80
+; CHECK-P8-NEXT:    lvx v23, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 64
+; CHECK-P8-NEXT:    lvx v22, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    lvx v21, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 224
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r31, -8(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r24, -64(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r23, -72(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r22, -80(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r21, -88(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    mtlr r0
-; CHECK-P8-NEXT:    ld r20, -96(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r19, -104(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r18, -112(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r17, -120(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r16, -128(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r15, -136(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r14, -144(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                           fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
                           fp128 %p11, fp128 %p12, fp128 %p13) {
 entry:
   %add = fadd fp128 %p1, %p2
   %add1 = fadd fp128 %add, %p3
   %add2 = fadd fp128 %add1, %p4
   %add3 = fadd fp128 %add2, %p5

 ; CHECK-NEXT:    mtvsrwa v3, r5
 ; CHECK-NEXT:    xscvsdqp v3, v3
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_01:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r5, r6
-; CHECK-P8-NEXT:    mr r6, r7
+; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r29, r3
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r28, r4
+; CHECK-P8-NEXT:    vmr v31, v2
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r29
-; CHECK-P8-NEXT:    mr r4, r28
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %add = fadd fp128 %a, %b
   %conv = sitofp i32 %i to fp128
   %add1 = fadd fp128 %add, %conv
   ret fp128 %add1
 }
 ; Function Attrs: norecurse nounwind readnone
 define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
 ; CHECK-LABEL: mixParam_01f:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    mtvsrwa v3, r3
 ; CHECK-NEXT:    xscvsdqp v3, v3
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_01f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r5, r6
-; CHECK-P8-NEXT:    mr r6, r7
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r4, 48
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r3
+; CHECK-P8-NEXT:    stvx v31, r1, r4 # 16-byte Folded Spill
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r29, r3
 ; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r28, r4
+; CHECK-P8-NEXT:    vmr v31, v2
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r29
-; CHECK-P8-NEXT:    mr r4, r28
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %add = fadd fp128 %a, %b
   %conv = sitofp i32 %i to fp128
   %add1 = fadd fp128 %add, %conv
   ret fp128 %add1
 }

 ; CHECK-NEXT:    lxv v4, 0(r8)
 ; CHECK-NEXT:    xsaddqp v2, v4, v2
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_02:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r29, -32
-; CHECK-P8-NEXT:    .cfi_offset r30, -24
 ; CHECK-P8-NEXT:    .cfi_offset f31, -8
-; CHECK-P8-NEXT:    std r29, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    mr r11, r4
-; CHECK-P8-NEXT:    lwz r4, 160(r1)
-; CHECK-P8-NEXT:    add r5, r7, r9
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    add r4, r7, r9
+; CHECK-P8-NEXT:    vmr v4, v2
+; CHECK-P8-NEXT:    stfd f31, 72(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lwz r3, 176(r1)
+; CHECK-P8-NEXT:    add r4, r4, r10
 ; CHECK-P8-NEXT:    fmr f31, f1
-; CHECK-P8-NEXT:    add r5, r5, r10
-; CHECK-P8-NEXT:    add r4, r5, r4
-; CHECK-P8-NEXT:    clrldi r4, r4, 32
-; CHECK-P8-NEXT:    std r4, 0(r6)
-; CHECK-P8-NEXT:    mr r6, r3
-; CHECK-P8-NEXT:    ld r5, 0(r8)
-; CHECK-P8-NEXT:    ld r4, 8(r8)
-; CHECK-P8-NEXT:    mr r3, r5
-; CHECK-P8-NEXT:    mr r5, r6
-; CHECK-P8-NEXT:    mr r6, r11
+; CHECK-P8-NEXT:    add r3, r4, r3
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
+; CHECK-P8-NEXT:    std r3, 0(r6)
+; CHECK-P8-NEXT:    lvx v3, 0, r8
+; CHECK-P8-NEXT:    vmr v2, v3
+; CHECK-P8-NEXT:    vmr v3, v4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    fmr f1, f31
-; CHECK-P8-NEXT:    mr r30, r3
-; CHECK-P8-NEXT:    mr r29, r4
+; CHECK-P8-NEXT:    vmr v31, v2
 ; CHECK-P8-NEXT:    bl __extenddfkf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    lfd f31, 72(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r30, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                           i16 signext %p4, fp128* nocapture readonly %p5,
                           i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
 entry:
   %conv = sext i16 %p4 to i32
   %add = add nsw i32 %conv, %p6
   %conv1 = zext i8 %p7 to i32

 ; CHECK-NEXT:    lxv v4, 0(r5)
 ; CHECK-NEXT:    xsaddqp v2, v4, v2
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_02f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r29, -32
-; CHECK-P8-NEXT:    .cfi_offset r30, -24
 ; CHECK-P8-NEXT:    .cfi_offset f31, -8
-; CHECK-P8-NEXT:    std r29, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    mr r11, r4
-; CHECK-P8-NEXT:    add r4, r6, r8
-; CHECK-P8-NEXT:    mr r6, r3
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    add r4, r4, r6
+; CHECK-P8-NEXT:    vmr v4, v2
+; CHECK-P8-NEXT:    li r9, 48
+; CHECK-P8-NEXT:    stfd f31, 72(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    add r4, r4, r7
+; CHECK-P8-NEXT:    stvx v31, r1, r9 # 16-byte Folded Spill
 ; CHECK-P8-NEXT:    fmr f31, f1
-; CHECK-P8-NEXT:    add r4, r4, r9
-; CHECK-P8-NEXT:    add r4, r4, r10
+; CHECK-P8-NEXT:    add r4, r4, r8
 ; CHECK-P8-NEXT:    clrldi r4, r4, 32
-; CHECK-P8-NEXT:    std r4, 0(r5)
-; CHECK-P8-NEXT:    ld r5, 0(r7)
-; CHECK-P8-NEXT:    ld r4, 8(r7)
-; CHECK-P8-NEXT:    mr r3, r5
-; CHECK-P8-NEXT:    mr r5, r6
-; CHECK-P8-NEXT:    mr r6, r11
+; CHECK-P8-NEXT:    std r4, 0(r3)
+; CHECK-P8-NEXT:    lvx v3, 0, r5
+; CHECK-P8-NEXT:    vmr v2, v3
+; CHECK-P8-NEXT:    vmr v3, v4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    fmr f1, f31
-; CHECK-P8-NEXT:    mr r30, r3
-; CHECK-P8-NEXT:    mr r29, r4
+; CHECK-P8-NEXT:    vmr v31, v2
 ; CHECK-P8-NEXT:    bl __extenddfkf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    lfd f31, 72(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    lfd f31, -8(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r30, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                                   i16 signext %p4, fp128* nocapture readonly %p5,
                                   i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
 entry:
   %conv = sext i16 %p4 to i32
   %add = add nsw i32 %conv, %p6
   %conv1 = zext i8 %p7 to i32

 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpdp v2, v2
 ; CHECK-NEXT:    stxsd v2, 0(r5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    ld r6, 168(r1)
-; CHECK-P8-NEXT:    std r4, 8(r9)
-; CHECK-P8-NEXT:    std r3, 0(r9)
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    ld r4, 184(r1)
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r9
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r5
+; CHECK-P8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
 ; CHECK-P8-NEXT:    mr r3, r10
-; CHECK-P8-NEXT:    mr r28, r5
-; CHECK-P8-NEXT:    stvx v2, 0, r6
-; CHECK-P8-NEXT:    ld r30, 0(r9)
-; CHECK-P8-NEXT:    ld r29, 8(r9)
+; CHECK-P8-NEXT:    stvx v3, 0, r4
+; CHECK-P8-NEXT:    lvx v31, 0, r9
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __trunckfdf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    stfdx f1, 0, r28
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stfdx f1, 0, r30
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                          fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
                          <4 x i32>* nocapture %vec2) {
 entry:
   store fp128 %f1, fp128* %f2, align 16
   store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
   %0 = load fp128, fp128* %f2, align 16

 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpdp v2, v2
 ; CHECK-NEXT:    stxsd v2, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: mixParam_03f:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -80(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r28, -32
-; CHECK-P8-NEXT:    .cfi_offset r29, -24
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -64(r1)
-; CHECK-P8-NEXT:    std r4, 8(r6)
-; CHECK-P8-NEXT:    std r3, 0(r6)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    mr r28, r5
-; CHECK-P8-NEXT:    stvx v2, 0, r9
-; CHECK-P8-NEXT:    ld r30, 0(r6)
-; CHECK-P8-NEXT:    ld r29, 8(r6)
+; CHECK-P8-NEXT:    .cfi_offset v31, -32
+; CHECK-P8-NEXT:    li r6, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r4
+; CHECK-P8-NEXT:    stvx v3, 0, r7
+; CHECK-P8-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    mr r30, r3
+; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    stvx v31, r1, r6 # 16-byte Folded Spill
+; CHECK-P8-NEXT:    lvx v31, 0, r4
 ; CHECK-P8-NEXT:    bl __floatsikf
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    mr r5, r3
-; CHECK-P8-NEXT:    mr r6, r4
-; CHECK-P8-NEXT:    mr r3, r30
-; CHECK-P8-NEXT:    mr r4, r29
+; CHECK-P8-NEXT:    vmr v3, v2
+; CHECK-P8-NEXT:    vmr v2, v31
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __trunckfdf2
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    stfdx f1, 0, r28
-; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    li r3, 48
+; CHECK-P8-NEXT:    stfdx f1, 0, r30
+; CHECK-P8-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    lvx v31, r1, r3 # 16-byte Folded Reload
+; CHECK-P8-NEXT:    addi r1, r1, 80
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
-; CHECK-P8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                                  fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
                                  <4 x i32>* nocapture %vec2) {
 entry:
   store fp128 %f1, fp128* %f2, align 16
   store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
   %0 = load fp128, fp128* %f2, align 16

 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: noopt_call_crash:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -32(r1)
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P8-NEXT:    stdu r1, -96(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    bl in
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl out
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    li r3, 0
-; CHECK-P8-NEXT:    addi r1, r1, 32
+; CHECK-P8-NEXT:    addi r1, r1, 96
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %call = call fp128 @in()
   call void @out(fp128 %call)
   ret i32 0
 }
 
 declare void @out(fp128)
 declare fp128 @in()
 
 attributes #0 = { noinline optnone }

llvm/test/CodeGen/PowerPC/f128-rounding.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
-; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -enable-soft-fp128 | FileCheck %s \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 define void @qp_trunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qp_trunc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xsrqpi 1, v2, v2, 1
 ; CHECK-NEXT:    stxv v2, 0(r4)

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

 ;
 ; CHECK-P8-LABEL: qpConv2sdw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2sdw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r29, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sldi r4, r30, 3
 ; CHECK-P8-NEXT:    stdx r3, r29, r4
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2udw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixunskfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixunskfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2udw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixunskfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixunskfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r29, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 0(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixunskfdi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sldi r4, r30, 3
 ; CHECK-P8-NEXT:    stdx r3, r29, r4
 ; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2sw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2sw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2uw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixunskfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixunskfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2uw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixunskfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixunskfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2shw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sth r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2shw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sth r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2uhw:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sth r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2uhw_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    sth r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2sb:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stb r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2sb_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    extsw r3, r3
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stb r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ;
 ; CHECK-P8-LABEL: qpConv2ub:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    ld r5, 0(r3)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mr r30, r3
 ; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r5, 32(r4)
-; CHECK-P8-NEXT:    ld r4, 40(r4)
-; CHECK-P8-NEXT:    mr r3, r5
+; CHECK-P8-NEXT:    addi r4, r4, 32
+; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stb r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8-LABEL: qpConv2ub_03:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -32(r1)
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld r7, 0(r3)
-; CHECK-P8-NEXT:    ld r6, .LC0@toc@l(r4)
-; CHECK-P8-NEXT:    ld r4, 8(r3)
-; CHECK-P8-NEXT:    mr r3, r7
-; CHECK-P8-NEXT:    ld r5, 16(r6)
-; CHECK-P8-NEXT:    ld r6, 24(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-P8-NEXT:    addi r4, r4, 16
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    .cfi_offset r30, -16
 ; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    ld r9, 0(r3)
-; CHECK-P8-NEXT:    ld r7, 8(r3)
-; CHECK-P8-NEXT:    ld r8, 0(r4)
-; CHECK-P8-NEXT:    ld r6, 8(r4)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    mr r30, r5
-; CHECK-P8-NEXT:    mr r3, r9
-; CHECK-P8-NEXT:    mr r4, r7
-; CHECK-P8-NEXT:    mr r5, r8
 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    bl __fixkfsi
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stb r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s\
 ; RUN:   -check-prefix=P8
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \
 ; RUN:   -check-prefix=P9
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -enable-soft-fp128 -mattr=-vsx \
+; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx \
 ; RUN:   | FileCheck %s -check-prefix=NOVSX
 
 declare i1 @llvm.experimental.constrained.fptosi.i1.f128(fp128, metadata)
 declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata)
 declare i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128, metadata)
 declare i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128, metadata)
 declare i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128, metadata)
 declare i1 @llvm.experimental.constrained.fptoui.i1.f128(fp128, metadata)

 define i1 @q_to_u1(fp128 %m) #0 {
 ; P8-LABEL: q_to_u1:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    .cfi_def_cfa_offset 112
 ; P8-NEXT:    .cfi_offset lr, 16
-; P8-NEXT:    bl __fixunskfsi
+; P8-NEXT:    bl __fixkfsi
 ; P8-NEXT:    nop
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: q_to_u1:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    xscvqpswz v2, v2
 ; P9-NEXT:    mfvsrwz r3, v2
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: q_to_u1:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    .cfi_def_cfa_offset 32
 ; NOVSX-NEXT:    .cfi_offset lr, 16
-; NOVSX-NEXT:    bl __fixkfsi
+; NOVSX-NEXT:    bl __fixunskfsi
 ; NOVSX-NEXT:    nop
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call i1 @llvm.experimental.constrained.fptoui.i1.f128(fp128 %m, metadata !"fpexcept.strict") #0
   ret i1 %conv

 define fp128 @u1_to_q(i1 zeroext %m) #0 {
 ; P8-LABEL: u1_to_q:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    .cfi_def_cfa_offset 112
 ; P8-NEXT:    .cfi_offset lr, 16
-; P8-NEXT:    bl __floatunsikf
+; P8-NEXT:    bl __floatsikf
 ; P8-NEXT:    nop
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: u1_to_q:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    mtvsrwa v2, r3
 ; P9-NEXT:    xscvsdqp v2, v2
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: u1_to_q:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    .cfi_def_cfa_offset 32
 ; NOVSX-NEXT:    .cfi_offset lr, 16
-; NOVSX-NEXT:    bl __floatsikf
+; NOVSX-NEXT:    bl __floatunsikf
 ; NOVSX-NEXT:    nop
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call fp128 @llvm.experimental.constrained.uitofp.f128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret fp128 %conv

llvm/test/CodeGen/PowerPC/fp-strict-f128.ll

 ; CHECK-NEXT:    xsmsubqp v4, v2, v3
 ; CHECK-NEXT:    vmr v2, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fmsub_f128:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -32(r1)
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P8-NEXT:    stdu r1, -48(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    li r9, 1
-; CHECK-P8-NEXT:    rldic r9, r9, 63, 0
-; CHECK-P8-NEXT:    xor r8, r8, r9
+; CHECK-P8-NEXT:    addi r3, r1, 32
+; CHECK-P8-NEXT:    stvx v4, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 47(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 47(r1)
+; CHECK-P8-NEXT:    lvx v4, 0, r3
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    addi r1, r1, 32
+; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
   %neg = fneg fp128 %f2
   %res = call fp128 @llvm.experimental.constrained.fma.f128(
                         fp128 %f0, fp128 %f1, fp128 %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   ret fp128 %res
 }
 
 define fp128 @fnmadd_f128(fp128 %f0, fp128 %f1, fp128 %f2) #0 {
 ; CHECK-LABEL: fnmadd_f128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsnmaddqp v4, v2, v3
 ; CHECK-NEXT:    vmr v2, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fnmadd_f128:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -32(r1)
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P8-NEXT:    stdu r1, -48(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    li r5, 1
-; CHECK-P8-NEXT:    rldic r5, r5, 63, 0
-; CHECK-P8-NEXT:    xor r4, r4, r5
-; CHECK-P8-NEXT:    addi r1, r1, 32
+; CHECK-P8-NEXT:    addi r3, r1, 32
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 47(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 47(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
   %fma = call fp128 @llvm.experimental.constrained.fma.f128(
                         fp128 %f0, fp128 %f1, fp128 %f2,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg fp128 %fma
   ret fp128 %res
 }
 
 define fp128 @fnmsub_f128(fp128 %f0, fp128 %f1, fp128 %f2) #0 {
 ; CHECK-LABEL: fnmsub_f128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsnmsubqp v4, v2, v3
 ; CHECK-NEXT:    vmr v2, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: fnmsub_f128:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    mflr r0
-; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-P8-NEXT:    .cfi_offset lr, 16
-; CHECK-P8-NEXT:    .cfi_offset r30, -16
-; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-P8-NEXT:    std r0, 16(r1)
-; CHECK-P8-NEXT:    stdu r1, -48(r1)
-; CHECK-P8-NEXT:    li r9, 1
-; CHECK-P8-NEXT:    rldic r30, r9, 63, 0
-; CHECK-P8-NEXT:    xor r8, r8, r30
+; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    addi r3, r1, 32
+; CHECK-P8-NEXT:    stvx v4, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 47(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 47(r1)
+; CHECK-P8-NEXT:    lvx v4, 0, r3
 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
-; CHECK-P8-NEXT:    xor r4, r4, r30
-; CHECK-P8-NEXT:    addi r1, r1, 48
+; CHECK-P8-NEXT:    addi r3, r1, 48
+; CHECK-P8-NEXT:    stvx v2, 0, r3
+; CHECK-P8-NEXT:    lbz r4, 63(r1)
+; CHECK-P8-NEXT:    xori r4, r4, 128
+; CHECK-P8-NEXT:    stb r4, 63(r1)
+; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    addi r1, r1, 64
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
-; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
   %neg = fneg fp128 %f2
   %fma = call fp128 @llvm.experimental.constrained.fma.f128(
                         fp128 %f0, fp128 %f1, fp128 %neg,
                         metadata !"round.dynamic",
                         metadata !"fpexcept.strict") #0
   %res = fneg fp128 %fma

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
-; RUN:   < %s -enable-soft-fp128 -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \
+; RUN:   < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \
 ; RUN:   -check-prefix=P8
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 \
 ; RUN:   | FileCheck %s -check-prefix=P9
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \
 ; RUN:   FileCheck %s -check-prefix=NOVSX
 

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=CHECK-PWR8    \
 ; RUN:   -implicit-check-not "\<setb\>"
 
 ; Test different patterns with type i64
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setb1(i64 %a, i64 %b) {
+; CHECK-LABEL: setb1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb1:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb1
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setb2(i64 %a, i64 %b) {
+; CHECK-LABEL: setb2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb2:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb2
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setb3(i64 %a, i64 %b) {
+; CHECK-LABEL: setb3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb3:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb3:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb3
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setb4(i64 %a, i64 %b) {
+; CHECK-LABEL: setb4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb4:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb4:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb4
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb5(i64 %a, i64 %b) {
+; CHECK-LABEL: setb5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb5:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r4, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subc r8, r4, r3
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb5:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb5
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
 define i64 @setb6(i64 %a, i64 %b) {
+; CHECK-LABEL: setb6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb6:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r4, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subc r8, r4, r3
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb6:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb6
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setb7(i64 %a, i64 %b) {
+; CHECK-LABEL: setb7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb7:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r4, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subc r8, r4, r3
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp slt i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb7:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb7
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setb8(i64 %a, i64 %b) {
+; CHECK-LABEL: setb8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb8:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r4, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subc r8, r4, r3
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp slt i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb8:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb8
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
 define i64 @setb9(i64 %a, i64 %b) {
+; CHECK-LABEL: setb9:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb9:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subfic r6, r6, 0
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r3, r6, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb9:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb9
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt
 define i64 @setb10(i64 %a, i64 %b) {
+; CHECK-LABEL: setb10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb10:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subfic r6, r6, 0
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r3, r6, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb10:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb10
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt
 define i64 @setb11(i64 %a, i64 %b) {
+; CHECK-LABEL: setb11:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb11:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subfic r6, r6, 0
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r3, r6, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb11:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb11
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt
 define i64 @setb12(i64 %a, i64 %b) {
+; CHECK-LABEL: setb12:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb12:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subfic r6, r6, 0
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r3, r6, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb12:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb12
-; CHECK-PWR8-DAG: xor
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
 define i64 @setb13(i64 %a, i64 %b) {
+; CHECK-LABEL: setb13:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb13:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r3, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subc r8, r3, r4
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r6, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp slt i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb13:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb13
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
 define i64 @setb14(i64 %a, i64 %b) {
+; CHECK-LABEL: setb14:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb14:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r3, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subc r8, r3, r4
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r6, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp slt i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb14:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb14
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
 define i64 @setb15(i64 %a, i64 %b) {
+; CHECK-LABEL: setb15:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb15:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r3, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subc r8, r3, r4
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r6, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp sgt i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb15:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb15
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb16(i64 %a, i64 %b) {
+; CHECK-LABEL: setb16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb16:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r3, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subc r8, r3, r4
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r6, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp sgt i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb16:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb16
-; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq
 define i64 @setb17(i64 %a, i64 %b) {
+; CHECK-LABEL: setb17:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb17:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    li r6, 1
+; CHECK-PWR8-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r3, r4
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb17:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb17
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setgt), seteq
 define i64 @setb18(i64 %a, i64 %b) {
+; CHECK-LABEL: setb18:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb18:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    li r6, 1
+; CHECK-PWR8-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp sgt i64 %a, %b
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb18:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb18
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setlt), seteq
 define i64 @setb19(i64 %a, i64 %b) {
+; CHECK-LABEL: setb19:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb19:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    li r6, 1
+; CHECK-PWR8-NEXT:    isellt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r3, r4
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp slt i64 %b, %a
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb19:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb19
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setlt), seteq
 define i64 @setb20(i64 %a, i64 %b) {
+; CHECK-LABEL: setb20:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb20:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    li r6, 1
+; CHECK-PWR8-NEXT:    isellt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp slt i64 %b, %a
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb20:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb20
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setlt), seteq
 define i64 @setb21(i64 %a, i64 %b) {
+; CHECK-LABEL: setb21:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb21:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    li r6, -1
+; CHECK-PWR8-NEXT:    isellt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r3, r4
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp slt i64 %a, %b
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb21:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb21
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setlt), seteq
 define i64 @setb22(i64 %a, i64 %b) {
+; CHECK-LABEL: setb22:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb22:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    li r6, -1
+; CHECK-PWR8-NEXT:    isellt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp slt i64 %a, %b
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb22:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb22
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
 define i64 @setb23(i64 %a, i64 %b) {
+; CHECK-LABEL: setb23:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb23:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    li r6, -1
+; CHECK-PWR8-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r3, r4
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp sgt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb23:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb23
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setb24(i64 %a, i64 %b) {
+; CHECK-LABEL: setb24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb24:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    li r6, -1
+; CHECK-PWR8-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp sgt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb24:
-; CHECK-NOT: li
-; CHECK-NOT: cmpld
-; CHECK-NOT: isel
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb24
-; CHECK-PWR8: cmpd
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmpld
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 ; end all patterns testing for i64
 
 ; Test with swapping the input parameters
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setb25(i64 %a, i64 %b) {
+; CHECK-LABEL: setb25:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r4, r3
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb25:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb25:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK-NOT: cmpd
-; CHECK: cmpd {{c?r?(0, )?}}r4, r3
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb25
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setb26(i64 %a, i64 %b) {
+; CHECK-LABEL: setb26:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r4, r3
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb26:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb26:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r4, r3
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb26
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; Test with different scalar integer type for selected value
 ; i32/i16/i8 rather than i64 above
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setb27(i64 %a, i64 %b) {
+; CHECK-LABEL: setb27:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb27:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i32
   %t4 = select i1 %t1, i32 -1, i32 %t3
   %t5 = sext i32 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb27:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: extsw
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb27
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: extsw
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setb28(i64 %a, i64 %b) {
+; CHECK-LABEL: setb28:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb28:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    addic r7, r6, -1
+; CHECK-PWR8-NEXT:    cmpd r4, r3
+; CHECK-PWR8-NEXT:    subfe r6, r7, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i16
   %t4 = select i1 %t1, i16 -1, i16 %t3
   %t5 = sext i16 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb28:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: addic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: extsw
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb28
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: addic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: extsw
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb29(i64 %a, i64 %b) {
+; CHECK-LABEL: setb29:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setb29:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    sradi r6, r4, 63
+; CHECK-PWR8-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subc r8, r4, r3
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    adde r6, r7, r6
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    isellt r3, r5, r6
+; CHECK-PWR8-NEXT:    clrldi r3, r3, 56
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i8
   %t4 = select i1 %t1, i8 -1, i8 %t3
   %t5 = zext i8 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb29:
-; CHECK-NOT: sradi
-; CHECK-NOT: rldicl
-; CHECK-NOT: li
-; CHECK: cmpd {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: adde
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setb29
-; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: adde
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; Testings to cover different comparison opcodes
 ; Test with integer type i32/i16/i8 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setbsw1(i32 %a, i32 %b) {
+; CHECK-LABEL: setbsw1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsw1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmpw r3, r4
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r3, r6, 1
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i32 %a, %b
   %t2 = icmp ne i32 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw1:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsw1
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setbsw2(i32 %a, i32 %b) {
+; CHECK-LABEL: setbsw2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsw2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmpw r4, r3
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r3, r6, 1
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i32 %b, %a
   %t2 = icmp ne i32 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw2:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsw2
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
 define i64 @setbsw3(i32 %a, i32 %b) {
+; CHECK-LABEL: setbsw3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsw3:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpw r4, r3
+; CHECK-PWR8-NEXT:    li r6, -1
+; CHECK-PWR8-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR8-NEXT:    cmplw r3, r4
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r5
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i32 %a, %b
   %t2 = icmp sgt i32 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw3:
-; CHECK-NOT: li
-; CHECK: cmpw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK-NOT: cmplw
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsw3
-; CHECK-PWR8: cmpw
-; CHECK-PWR8: isel
-; CHECK-PWR8: cmplw
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setbsh1(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: setbsh1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsh1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmpw r3, r4
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r3, r6, 1
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i16 %a, %b
   %t2 = icmp ne i16 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsh1:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsh1
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setbsh2(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: setbsh2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsh2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmpw r4, r3
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r3, r6, 1
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i16 %b, %a
   %t2 = icmp ne i16 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsh2:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsh2
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbsc1(i8 %a, i8 %b) {
+; CHECK-LABEL: setbsc1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    extsb r4, r4
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsc1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    extsb r4, r4
+; CHECK-PWR8-NEXT:    extsb r3, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    extsw r4, r4
+; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    sub r6, r4, r3
+; CHECK-PWR8-NEXT:    cmpw r3, r4
+; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i8 %a, %b
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc1:
-; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
-; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
-; CHECK-NOT: li
-; CHECK-NOT: sub
-; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: rldicl
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsc1
-; CHECK-PWR8-DAG: extsb
-; CHECK-PWR8-DAG: extsb
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
 define i64 @setbsc2(i8 %a, i8 %b) {
+; CHECK-LABEL: setbsc2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    extsb r4, r4
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsc2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    extsb r4, r4
+; CHECK-PWR8-NEXT:    extsb r3, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    extsw r4, r4
+; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    sub r6, r4, r3
+; CHECK-PWR8-NEXT:    cmpw r4, r3
+; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp sgt i8 %b, %a
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc2:
-; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
-; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
-; CHECK-NOT: li
-; CHECK-NOT: sub
-; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: rldicl
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsc2
-; CHECK-PWR8-DAG: extsb
-; CHECK-PWR8-DAG: extsb
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbsc3(i4 %a, i4 %b) {
+; CHECK-LABEL: setbsc3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slwi r4, r4, 28
+; CHECK-NEXT:    slwi r3, r3, 28
+; CHECK-NEXT:    srawi r4, r4, 28
+; CHECK-NEXT:    srawi r3, r3, 28
+; CHECK-NEXT:    cmpw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbsc3:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    slwi r4, r4, 28
+; CHECK-PWR8-NEXT:    slwi r3, r3, 28
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    srawi r4, r4, 28
+; CHECK-PWR8-NEXT:    srawi r3, r3, 28
+; CHECK-PWR8-NEXT:    extsw r4, r4
+; CHECK-PWR8-NEXT:    extsw r3, r3
+; CHECK-PWR8-NEXT:    sub r6, r4, r3
+; CHECK-PWR8-NEXT:    cmpw r3, r4
+; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i4 %a, %b
   %t2 = icmp slt i4 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc3:
-; CHECK-DAG: slwi [[RA:r[0-9]+]], r3, 28
-; CHECK-DAG: slwi [[RB:r[0-9]+]], r4, 28
-; CHECK-NOT: li
-; CHECK-DAG: srawi [[RA1:r[0-9]+]], [[RA]], 28
-; CHECK-DAG: srawi [[RB1:r[0-9]+]], [[RB]], 28
-; CHECK-NOT: sub
-; CHECK: cmpw {{c?r?(0, )?}}[[RA1]], [[RB1]]
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: rldicl
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbsc3
-; CHECK-PWR8-DAG: slwi
-; CHECK-PWR8-DAG: slwi
-; CHECK-PWR8-DAG: srawi
-; CHECK-PWR8-DAG: srawi
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: extsw
-; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; Test with unsigned integer type i64/i32/i16/i8 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt
 define i64 @setbud1(i64 %a, i64 %b) {
+; CHECK-LABEL: setbud1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpld r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbud1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    subc r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    subfe r6, r4, r4
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    neg r3, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ugt i64 %b, %a
   %t2 = icmp ult i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud1:
-; CHECK-NOT: li
-; CHECK: cmpld {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subc
-; CHECK-NOT: subfe
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbud1
-; CHECK-PWR8-DAG: subc
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8-DAG: cmpld
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt
 define i64 @setbud2(i64 %a, i64 %b) {
+; CHECK-LABEL: setbud2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpld r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbud2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    subfic r6, r6, 0
+; CHECK-PWR8-NEXT:    cmpld r3, r4
+; CHECK-PWR8-NEXT:    subfe r3, r6, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ugt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud2:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmpld {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfic
-; CHECK-NOT: subfe
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbud2
-; CHECK-PWR8-DAG: cmpld
-; CHECK-PWR8-DAG: subfic
-; CHECK-PWR8-DAG: subfe
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setugt), seteq
 define i64 @setbud3(i64 %a, i64 %b) {
+; CHECK-LABEL: setbud3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpld r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbud3:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cmpld r4, r3
+; CHECK-PWR8-NEXT:    li r3, -1
+; CHECK-PWR8-NEXT:    iselgt r3, r3, r5
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp ugt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud3:
-; CHECK-NOT: li
-; CHECK: cmpld {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: li
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbud3
-; CHECK-PWR8-DAG: cmpld
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8-DAG: li
-; CHECK-PWR8: isel
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setult
 define i64 @setbuw1(i32 %a, i32 %b) {
+; CHECK-LABEL: setbuw1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmplw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbuw1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmplw r4, r3
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r3, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ult i32 %b, %a
   %t2 = icmp ne i32 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuw1:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmplw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbuw1
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: cmplw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setugt
 define i64 @setbuw2(i32 %a, i32 %b) {
+; CHECK-LABEL: setbuw2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmplw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbuw2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    cmplw r3, r4
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r3, r6
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ugt i32 %a, %b
   %t2 = icmp ne i32 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuw2:
-; CHECK-NOT: xor
-; CHECK-NOT: li
-; CHECK: cmplw {{c?r?(0, )?}}r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbuw2
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8-DAG: cmplw
-; CHECK-PWR8-DAG: srwi
-; CHECK-PWR8-DAG: xori
-; CHECK-PWR8-DAG: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult
 define i64 @setbuh(i16 %a, i16 %b) {
+; CHECK-LABEL: setbuh:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi r4, r4, 16
+; CHECK-NEXT:    clrlwi r3, r3, 16
+; CHECK-NEXT:    cmplw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbuh:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    clrlwi r3, r3, 16
+; CHECK-PWR8-NEXT:    clrlwi r4, r4, 16
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    xor r6, r4, r3
+; CHECK-PWR8-NEXT:    cmplw r4, r3
+; CHECK-PWR8-NEXT:    cntlzw r6, r6
+; CHECK-PWR8-NEXT:    srwi r6, r6, 5
+; CHECK-PWR8-NEXT:    xori r6, r6, 1
+; CHECK-PWR8-NEXT:    neg r3, r6
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ult i16 %b, %a
   %t2 = icmp ne i16 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuh:
-; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
-; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
-; CHECK-NOT: li
-; CHECK-NOT: xor
-; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: cntlzw
-; CHECK-NOT: srwi
-; CHECK-NOT: xori
-; CHECK-NOT: neg
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbuh
-; CHECK-PWR8: clrlwi
-; CHECK-PWR8: clrlwi
-; CHECK-PWR8-DAG: cmplw
-; CHECK-PWR8-DAG: cntlzw
-; CHECK-PWR8: srwi
-; CHECK-PWR8: xori
-; CHECK-PWR8: neg
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt
 define i64 @setbuc(i8 %a, i8 %b) {
+; CHECK-LABEL: setbuc:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi r4, r4, 24
+; CHECK-NEXT:    clrlwi r3, r3, 24
+; CHECK-NEXT:    cmplw r3, r4
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbuc:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    clrlwi r3, r3, 24
+; CHECK-PWR8-NEXT:    clrlwi r4, r4, 24
+; CHECK-PWR8-NEXT:    li r5, 1
+; CHECK-PWR8-NEXT:    clrldi r6, r3, 32
+; CHECK-PWR8-NEXT:    clrldi r7, r4, 32
+; CHECK-PWR8-NEXT:    sub r6, r6, r7
+; CHECK-PWR8-NEXT:    cmplw r3, r4
+; CHECK-PWR8-NEXT:    sradi r6, r6, 63
+; CHECK-PWR8-NEXT:    iselgt r3, r5, r6
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp ugt i8 %a, %b
   %t2 = icmp ult i8 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuc:
-; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
-; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
-; CHECK-NOT: li
-; CHECK-NOT: clrldi
-; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: sub
-; CHECK-NOT: sradi
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbuc
-; CHECK-PWR8: clrlwi
-; CHECK-PWR8: clrlwi
-; CHECK-PWR8-DAG: clrldi
-; CHECK-PWR8-DAG: clrldi
-; CHECK-PWR8-DAG: cmplw
-; CHECK-PWR8: sradi
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; Test with float/double/float128 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbf1(float %a, float %b) {
+; CHECK-LABEL: setbf1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbf1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
+; CHECK-PWR8-NEXT:    fcmpu cr1, f1, f2
+; CHECK-PWR8-NEXT:    li r3, 0
+; CHECK-PWR8-NEXT:    li r4, 1
+; CHECK-PWR8-NEXT:    isellt r3, r4, r3
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan olt float %a, %b
   %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf1:
-; CHECK-NOT: li
-; CHECK: fcmpu cr0, f1, f2
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK-NOT: li
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbf1
-; CHECK-PWR8: isel
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setbf2(float %a, float %b) {
+; CHECK-LABEL: setbf2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbf2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
+; CHECK-PWR8-NEXT:    li r3, 0
+; CHECK-PWR8-NEXT:    li r4, 1
+; CHECK-PWR8-NEXT:    isellt r3, r4, r3
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan ogt float %b, %a
   %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf2:
-; CHECK-NOT: li
-; CHECK: fcmpu cr0, f1, f2
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK-NOT: li
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbf2
-; CHECK-PWR8: isel
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setbdf1(double %a, double %b) {
+; CHECK-LABEL: setbdf1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbdf1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xscmpudp cr0, f2, f1
+; CHECK-PWR8-NEXT:    li r3, 1
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan oeq double %b, %a
   %t2 = fcmp nnan ogt double %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbdf1:
-; CHECK: xscmpudp cr0, f1, f2
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: li
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbdf1
-; CHECK-PWR8: isel
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbdf2(double %a, double %b) {
+; CHECK-LABEL: setbdf2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbdf2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    fcmpu cr0, f2, f1
+; CHECK-PWR8-NEXT:    xscmpudp cr1, f2, f1
+; CHECK-PWR8-NEXT:    li r3, 0
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    iselgt r3, r4, r3
+; CHECK-PWR8-NEXT:    li r4, 1
+; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan olt double %b, %a
   %t2 = fcmp nnan ogt double %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbdf2:
-; CHECK-NOT: fcmpu
-; CHECK-NOT: li
-; CHECK: xscmpudp cr0, f1, f2
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: li
-; CHECK-NOT: isel
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbdf2
-; CHECK-PWR8: isel
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 define i64 @setbf128(fp128 %a, fp128 %b) {
+; CHECK-LABEL: setbf128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xscmpuqp cr0, v2, v3
+; CHECK-NEXT:    setb r3, cr0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbf128:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    mflr r0
+; CHECK-PWR8-NEXT:    std r0, 16(r1)
+; CHECK-PWR8-NEXT:    stdu r1, -96(r1)
+; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 96
+; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
+; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
+; CHECK-PWR8-NEXT:    .cfi_offset v30, -48
+; CHECK-PWR8-NEXT:    .cfi_offset v31, -32
+; CHECK-PWR8-NEXT:    li r3, 48
+; CHECK-PWR8-NEXT:    std r30, 80(r1) # 8-byte Folded Spill
+; CHECK-PWR8-NEXT:    stvx v30, r1, r3 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    li r3, 64
+; CHECK-PWR8-NEXT:    vmr v30, v2
+; CHECK-PWR8-NEXT:    stvx v31, r1, r3 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    vmr v31, v3
+; CHECK-PWR8-NEXT:    bl __ltkf2
+; CHECK-PWR8-NEXT:    nop
+; CHECK-PWR8-NEXT:    vmr v2, v30
+; CHECK-PWR8-NEXT:    srawi r30, r3, 31
+; CHECK-PWR8-NEXT:    vmr v3, v31
+; CHECK-PWR8-NEXT:    bl __gtkf2
+; CHECK-PWR8-NEXT:    nop
+; CHECK-PWR8-NEXT:    li r4, 1
+; CHECK-PWR8-NEXT:    cmpwi r3, 0
+; CHECK-PWR8-NEXT:    iselgt r3, r4, r30
+; CHECK-PWR8-NEXT:    li r4, 64
+; CHECK-PWR8-NEXT:    ld r30, 80(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    lvx v31, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    li r4, 48
+; CHECK-PWR8-NEXT:    lvx v30, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    addi r1, r1, 96
+; CHECK-PWR8-NEXT:    ld r0, 16(r1)
+; CHECK-PWR8-NEXT:    mtlr r0
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan ogt fp128 %a, %b
   %t2 = fcmp nnan olt fp128 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf128:
-; CHECK-NOT: li
-; CHECK: xscmpuqp cr0, v2, v3
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: isel
-; CHECK-NOT: li
-; CHECK: blr
-; CHECK-PWR8-LABEL: setbf128
-; CHECK-PWR8: isel
-; CHECK-PWR8: blr
 }
 
 ; Some cases we can't leverage setb
 
 define i64 @setbn1(i64 %a, i64 %b) {
+; CHECK-LABEL: setbn1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor r5, r3, r4
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    cntlzd r5, r5
+; CHECK-NEXT:    rldicl r5, r5, 58, 63
+; CHECK-NEXT:    isellt r3, r3, r5
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbn1:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    xor r6, r3, r4
+; CHECK-PWR8-NEXT:    li r5, -1
+; CHECK-PWR8-NEXT:    cntlzd r6, r6
+; CHECK-PWR8-NEXT:    cmpd r3, r4
+; CHECK-PWR8-NEXT:    rldicl r3, r6, 58, 63
+; CHECK-PWR8-NEXT:    isellt r3, r5, r3
+; CHECK-PWR8-NEXT:    blr
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp eq i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn1:
-; CHECK-NOT: {{\<setb\>}}
-; CHECK: isel
-; CHECK: blr
 }
 
 define i64 @setbn2(double %a, double %b) {
+; CHECK-LABEL: setbn2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    cror 4*cr5+lt, un, eq
+; CHECK-NEXT:    xscmpudp cr0, f1, f2
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    isellt r3, r4, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbn2:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2
+; CHECK-PWR8-NEXT:    xscmpudp cr1, f1, f2
+; CHECK-PWR8-NEXT:    li r3, 1
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    cror 4*cr5+lt, un, eq
+; CHECK-PWR8-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr1+lt
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp olt double %a, %b
   %t2 = fcmp one double %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn2:
-; CHECK-NOT: {{\<setb\>}}
-; CHECK: isel
-; CHECK: blr
 }
 
 define i64 @setbn3(float %a, float %b) {
+; CHECK-LABEL: setbn3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    iseleq r3, 0, r3
+; CHECK-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbn3:
+; CHECK-PWR8:       # %bb.0:
+; CHECK-PWR8-NEXT:    fcmpu cr0, f1, f2
+; CHECK-PWR8-NEXT:    li r3, 1
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-PWR8-NEXT:    iseleq r3, 0, r3
+; CHECK-PWR8-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp ult float %a, %b
   %t2 = fcmp une float %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn3:
-; CHECK-NOT: {{\<setb\>}}
-; CHECK: isel
-; CHECK: blr
 }
 
 ; Verify this case doesn't crash
 define void @setbn4(i128 %0, i32* %sel.out) {
-entry:
 ; CHECK-LABEL: setbn4:
-; CHECK-NOT: {{\<setb\>}}
-; CHECK: isel
-; CHECK: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r6, 1
+; CHECK-NEXT:    cmpdi cr1, r3, 0
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    rldic r6, r6, 48, 15
+; CHECK-NEXT:    cmpld r4, r6
+; CHECK-NEXT:    crandc 4*cr5+lt, gt, eq
+; CHECK-NEXT:    crandc 4*cr5+gt, eq, 4*cr1+eq
+; CHECK-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; CHECK-NEXT:    rldicl. r4, r4, 16, 48
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    iseleq r3, r4, r3
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: setbn4:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    li r6, 1
+; CHECK-PWR8-NEXT:    cmpdi cr1, r3, 0
+; CHECK-PWR8-NEXT:    li r3, 1
+; CHECK-PWR8-NEXT:    rldic r6, r6, 48, 15
+; CHECK-PWR8-NEXT:    cmpld r4, r6
+; CHECK-PWR8-NEXT:    crandc 4*cr5+lt, gt, eq
+; CHECK-PWR8-NEXT:    crandc 4*cr5+gt, eq, 4*cr1+eq
+; CHECK-PWR8-NEXT:    rldicl. r4, r4, 16, 48
+; CHECK-PWR8-NEXT:    li r4, -1
+; CHECK-PWR8-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; CHECK-PWR8-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-PWR8-NEXT:    iseleq r3, r4, r3
+; CHECK-PWR8-NEXT:    stw r3, 0(r5)
+; CHECK-PWR8-NEXT:    blr
+entry:
   %c1 = icmp ult i128 %0, 5192296858534827628530496329220096
   %c2 = icmp ugt i128 %0, 5192296858534827628530496329220096
   %ext = zext i1 %c2 to i32
   %sel = select i1 %c1, i32 -1, i32 %ext
   store i32 %sel, i32* %sel.out, align 4
   ret void
 }

llvm/test/CodeGen/PowerPC/store_fptoi.ll

 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr 0
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR8-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    std 0, 16(1)
 ; CHECK-PWR8-NEXT:    stdu 1, -48(1)
-; CHECK-PWR8-NEXT:    ld 5, 0(3)
-; CHECK-PWR8-NEXT:    ld 6, 8(3)
+; CHECK-PWR8-NEXT:    lvx 2, 0, 3
 ; CHECK-PWR8-NEXT:    mr 30, 4
-; CHECK-PWR8-NEXT:    mr 3, 5
-; CHECK-PWR8-NEXT:    mr 4, 6
 ; CHECK-PWR8-NEXT:    bl __fixkfdi
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    std 3, 0(30)
 ; CHECK-PWR8-NEXT:    addi 1, 1, 48
 ; CHECK-PWR8-NEXT:    ld 0, 16(1)
 ; CHECK-PWR8-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    mtlr 0
 ; CHECK-PWR8-NEXT:    blr

 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr 0
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR8-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    std 0, 16(1)
 ; CHECK-PWR8-NEXT:    stdu 1, -48(1)
-; CHECK-PWR8-NEXT:    ld 5, 0(3)
-; CHECK-PWR8-NEXT:    ld 6, 8(3)
+; CHECK-PWR8-NEXT:    lvx 2, 0, 3
 ; CHECK-PWR8-NEXT:    mr 30, 4
-; CHECK-PWR8-NEXT:    mr 3, 5
-; CHECK-PWR8-NEXT:    mr 4, 6
 ; CHECK-PWR8-NEXT:    bl __fixkfsi
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    stw 3, 0(30)
 ; CHECK-PWR8-NEXT:    addi 1, 1, 48
 ; CHECK-PWR8-NEXT:    ld 0, 16(1)
 ; CHECK-PWR8-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    mtlr 0
 ; CHECK-PWR8-NEXT:    blr

 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr 0
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR8-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    std 0, 16(1)
 ; CHECK-PWR8-NEXT:    stdu 1, -48(1)
-; CHECK-PWR8-NEXT:    ld 5, 0(3)
-; CHECK-PWR8-NEXT:    ld 6, 8(3)
+; CHECK-PWR8-NEXT:    lvx 2, 0, 3
 ; CHECK-PWR8-NEXT:    mr 30, 4
-; CHECK-PWR8-NEXT:    mr 3, 5
-; CHECK-PWR8-NEXT:    mr 4, 6
 ; CHECK-PWR8-NEXT:    bl __fixunskfdi
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    std 3, 0(30)
 ; CHECK-PWR8-NEXT:    addi 1, 1, 48
 ; CHECK-PWR8-NEXT:    ld 0, 16(1)
 ; CHECK-PWR8-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    mtlr 0
 ; CHECK-PWR8-NEXT:    blr

 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr 0
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR8-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    std 0, 16(1)
 ; CHECK-PWR8-NEXT:    stdu 1, -48(1)
-; CHECK-PWR8-NEXT:    ld 5, 0(3)
-; CHECK-PWR8-NEXT:    ld 6, 8(3)
+; CHECK-PWR8-NEXT:    lvx 2, 0, 3
 ; CHECK-PWR8-NEXT:    mr 30, 4
-; CHECK-PWR8-NEXT:    mr 3, 5
-; CHECK-PWR8-NEXT:    mr 4, 6
 ; CHECK-PWR8-NEXT:    bl __fixunskfsi
 ; CHECK-PWR8-NEXT:    nop
 ; CHECK-PWR8-NEXT:    stw 3, 0(30)
 ; CHECK-PWR8-NEXT:    addi 1, 1, 48
 ; CHECK-PWR8-NEXT:    ld 0, 16(1)
 ; CHECK-PWR8-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    mtlr 0
 ; CHECK-PWR8-NEXT:    blr