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Differential D91977

[RISCV] Remove unused VM register class
ClosedPublic

Authored by craig.topper on Nov 23 2020, 9:49 AM.

Details

Reviewers
evandro
HsiangKai
asb
luismarques
frasercrmck
lenary
Commits
rG03dab46d7f73: [RISCV] Remove unused VM register class
Summary

Nothing references this class today so it looks like some leftover.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 23 2020, 9:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 23 2020, 9:49 AM
Herald added subscribers: NickHung, apazos, sameer.abuasal and 21 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 23 2020, 9:49 AM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 23 2020, 9:49 AM
evandro accepted this revision.Nov 23 2020, 11:15 AM
This revision is now accepted and ready to land.Nov 23 2020, 11:15 AM
Closed by commit rG03dab46d7f73: [RISCV] Remove unused VM register class (authored by craig.topper). · Explain WhyNov 23 2020, 2:27 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG03dab46d7f73: [RISCV] Remove unused VM register class.
Herald added a subscriber: jrtc27. · View Herald TranscriptNov 23 2020, 2:27 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
7 lines

Diff 307198

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64, def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64,
(add V8M8, V16M8, V24M8, V0M8)> { (add V8M8, V16M8, V24M8, V0M8)> {
let Size = 512; let Size = 512;
} }
def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>; def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>;
def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add
(sequence "V%u", 25, 31),
(sequence "V%u", 8, 24),
(sequence "V%u", 0, 7))> {
let Size = 64;
}
def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> { def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> {
let Size = 64; let Size = 64;
} }