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Differential D91666

[NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests
ClosedPublic

Authored by scott.linder on Nov 17 2020, 4:23 PM.

Details

Reviewers
rampitec
t-tye
arsenm
kzhuravl
nhaehnle
Commits
rG0fe4b8e4b5b3: [NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests
Summary

These tests implicitly depend on the target supporting generic pointers,
so to prepare for testing them on GFX6 (which lacks FLAT) remove the
dependency where possible.

Diff Detail

Unit TestsFailed

TimeTest
350 mslinux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp

Event Timeline

scott.linder created this revision.Nov 17 2020, 4:23 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 17 2020, 4:23 PM
Herald added subscribers: llvm-commits, kerbowa, t-tye and 6 others. · View Herald Transcript
scott.linder requested review of this revision.Nov 17 2020, 4:23 PM
Herald added a subscriber: wdng. · View Herald TranscriptNov 17 2020, 4:23 PM
scott.linder added a child revision: D91545: [AMDGPU] Extend and reorganize memory legalizer tests.Nov 17 2020, 4:26 PM
scott.linder added reviewers: rampitec, t-tye, arsenm, kzhuravl, nhaehnle.
rampitec accepted this revision.Nov 17 2020, 4:37 PM

LGTM

This revision is now accepted and ready to land.Nov 17 2020, 4:37 PM
Harbormaster completed remote builds in B79195: Diff 305920.Nov 17 2020, 5:08 PM
This revision was landed with ongoing or failed builds.Nov 18 2020, 12:53 PM
Closed by commit rG0fe4b8e4b5b3: [NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests (authored by scott.linder). · Explain Why
This revision was automatically updated to reflect the committed changes.
scott.linder added a commit: rG0fe4b8e4b5b3: [NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
24 lines
24 lines

Diff 305920

llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll

Show First 20 Lines • Show All 448 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}nontemporal_private_0: ; GCN-LABEL: {{^}}nontemporal_private_0:
; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}} ; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}} ; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_private_0 ; GFX10: .amdhsa_kernel nontemporal_private_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32 addrspace(5)* %in, i32* %out) { i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1: ; GCN-LABEL: {{^}}nontemporal_private_1:
; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}} ; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}} ; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_private_1 ; GFX10: .amdhsa_kernel nontemporal_private_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32 addrspace(5)* %in, i32* %out) { i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_0: ; GCN-LABEL: {{^}}nontemporal_global_0:
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}}
; GFX10: .amdhsa_kernel nontemporal_global_0 ; GFX10: .amdhsa_kernel nontemporal_global_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(1)* %in, i32* %out) { i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_1: ; GCN-LABEL: {{^}}nontemporal_global_1:
; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX9: global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX9: global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX10: global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}} ; GFX10: global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_global_1 ; GFX10: .amdhsa_kernel nontemporal_global_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(1)* %in, i32* %out) { i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
%val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_0: ; GCN-LABEL: {{^}}nontemporal_local_0:
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
; GFX10: .amdhsa_kernel nontemporal_local_0 ; GFX10: .amdhsa_kernel nontemporal_local_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(3)* %in, i32* %out) { i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_1: ; GCN-LABEL: {{^}}nontemporal_local_1:
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
; GFX10: .amdhsa_kernel nontemporal_local_1 ; GFX10: .amdhsa_kernel nontemporal_local_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(3)* %in, i32* %out) { i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
%val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_0: ; GCN-LABEL: {{^}}nontemporal_flat_0:
; GFX89: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX89: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] slc{{$}} ; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_flat_0 ; GFX10: .amdhsa_kernel nontemporal_flat_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
▲ Show 20 Lines • Show All 472 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}nontemporal_private_0: ; GCN-LABEL: {{^}}nontemporal_private_0:
; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}} ; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}} ; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_private_0 ; GFX10: .amdhsa_kernel nontemporal_private_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32* %in, i32 addrspace(5)* %out) { i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry: entry:
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(5)* %out, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1: ; GCN-LABEL: {{^}}nontemporal_private_1:
; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}} ; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}} ; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_private_1 ; GFX10: .amdhsa_kernel nontemporal_private_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32* %in, i32 addrspace(5)* %out) { i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_0: ; GCN-LABEL: {{^}}nontemporal_global_0:
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} glc slc{{$}} ; GFX9: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} glc slc{{$}}
; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} slc{{$}} ; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_global_0 ; GFX10: .amdhsa_kernel nontemporal_global_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32* %in, i32 addrspace(1)* %out) { i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(1)* %out, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_1: ; GCN-LABEL: {{^}}nontemporal_global_1:
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX9: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}} ; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
; GFX10: .amdhsa_kernel nontemporal_global_1 ; GFX10: .amdhsa_kernel nontemporal_global_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32* %in, i32 addrspace(1)* %out) { i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_0: ; GCN-LABEL: {{^}}nontemporal_local_0:
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
; GFX10: .amdhsa_kernel nontemporal_local_0 ; GFX10: .amdhsa_kernel nontemporal_local_0
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32* %in, i32 addrspace(3)* %out) { i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry: entry:
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(3)* %out, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_1: ; GCN-LABEL: {{^}}nontemporal_local_1:
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
; GFX10: .amdhsa_kernel nontemporal_local_1 ; GFX10: .amdhsa_kernel nontemporal_local_1
; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0 ; GFX10WGP-NOT: .amdhsa_workgroup_processor_mode 0
; GFX10CU: .amdhsa_workgroup_processor_mode 0 ; GFX10CU: .amdhsa_workgroup_processor_mode 0
; GFX10-NOT: .amdhsa_memory_ordered 0 ; GFX10-NOT: .amdhsa_memory_ordered 0
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32* %in, i32 addrspace(3)* %out) { i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4 %val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_0: ; GCN-LABEL: {{^}}nontemporal_flat_0:
; GFX89: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX89: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX10: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} slc{{$}} ; GFX10: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} slc{{$}}
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