[PowerPC] [Clang] Fix alignment of 128-bit floating types

[qiucf]

Summary

According to ELF v2 ABI, both IEEE 128-bit and IBM extended floating point variables should be quad-word (16 bytes) aligned. Previously, only vector types are considered aligned as quad-word on Power.

Without this fix, IEEE 128-bit fp will be passed incorrectly in va_arg cases.

(the patch is not patchable since I generated it for easier review, the case is a new file)

[qiucf]

Use another branch

[rjmccall]

I assume this has always been taken care of properly in the backend, so this is just a fix for va_arg treatment? If so, LGTM.

[qiucf]

In D91596#2404514, @rjmccall wrote:

I assume this has always been taken care of properly in the backend, so this is just a fix for va_arg treatment? If so, LGTM.

Yes. That's just fix for va_arg. Thanks!

[hubert.reinterpretcast]

Reverting this patch makes va_arg with the default 128-bit (double-double) long double work again:

#include <stdarg.h>
void abort(void);

void foo(int x, ...) {
  va_list ap;
  va_start(ap, x);
  long double ans = va_arg(ap, long double);
  if (ans != 42.L) abort();
}

int main(void) {
  foo(0, 42.L);
}

This patch caused the above to abort.

[qiucf]

The regression should be fixed in rG3fca6a7844b5

clang/lib/CodeGen/TargetInfo.cpp

   // passed via reference, smaller types are not aligned).
   if (IsQPXVectorTy(Ty)) {
     if (getContext().getTypeSize(Ty) > 128)
       return CharUnits::fromQuantity(32);
 
     return CharUnits::fromQuantity(16);
   } else if (Ty->isVectorType()) {
     return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
+  } else if (Ty->isRealFloatingType() && getContext().getTypeSize(Ty) == 128) {
+    // IEEE 128-bit floating numbers are also stored in vector registers.
+    // And both IEEE quad-precision and IBM extended double (ppc_fp128) should
+    // be quad-word aligned.
+    return CharUnits::fromQuantity(16);
   }
 
   // For single-element float/vector structs, we consider the whole type
   // to have the same alignment requirements as its single element.
   const Type *AlignAsType = nullptr;
   const Type *EltType = isSingleElementStruct(Ty, getContext());
   if (EltType) {
     const BuiltinType *BT = EltType->getAs<BuiltinType>();

clang/test/CodeGen/ppc64le-varargs-f128.c

 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
 // RUN:   -target-cpu pwr9 -target-feature +float128 -mabi=ieeelongdouble \
 // RUN:   -o - %s | FileCheck %s -check-prefix=IEEE
 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
 // RUN:   -target-cpu pwr9 -target-feature +float128 \
 // RUN:   -o - %s | FileCheck %s -check-prefix=IBM
 
 #include <stdarg.h>
 
 // IEEE-LABEL: define fp128 @f128(i32 signext %n, ...)
 // IEEE: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to fp128*
-// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 8
+// IEEE: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IEEE: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IEEE: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to fp128*
+// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 16
 // IEEE: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 __float128 f128(int n, ...) {
   va_list ap;
   va_start(ap, n);
   __float128 x = va_arg(ap, __float128);
   va_end(ap);
   return x;
 }
 
 // IEEE-LABEL: define fp128 @long_double(i32 signext %n, ...)
 // IEEE: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to fp128*
-// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 8
+// IEEE: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IEEE: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IEEE: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to fp128*
+// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 16
 // IEEE: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 
 // IBM-LABEL: define ppc_fp128 @long_double(i32 signext %n, ...)
 // IBM: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IBM: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to ppc_fp128*
-// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 8
+// IBM: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IBM: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IBM: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IBM: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to ppc_fp128*
+// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 16
 // IBM: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 long double long_double(int n, ...) {
   va_list ap;
   va_start(ap, n);
   long double x = va_arg(ap, long double);
   va_end(ap);
   return x;
 }