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Differential D89796

[AMDGPU] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans
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Authored by Paul-C-Anagnostopoulos on Oct 20 2020, 7:55 AM.

Details

Reviewers
lattner
nhaehnle
tstellar
rampitec
Commits
rG332ff48deea1: [AMDGPU] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans
Summary

After adding the !not operator, I'm making a pass over the various targets to clean up things like !if(!eq(boolean, 1) and !eq(boolean 0). I'm pushing patches one target at a time.

Diff Detail

Unit TestsFailed

TimeTest
110 mslinux > Polly.ScopInfo/NonAffine::non-affine-loop-condition-dependent-access_3.ll

Event Timeline

Paul-C-Anagnostopoulos created this revision.Oct 20 2020, 7:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2020, 7:55 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 7 others. · View Herald Transcript
Paul-C-Anagnostopoulos requested review of this revision.Oct 20 2020, 7:55 AM
Herald added a subscriber: wdng. · View Herald TranscriptOct 20 2020, 7:55 AM
Harbormaster completed remote builds in B75705: Diff 299359.Oct 20 2020, 9:03 AM
rampitec accepted this revision.Oct 20 2020, 10:44 AM

LGTM, thanks!

This revision is now accepted and ready to land.Oct 20 2020, 10:44 AM
This revision was landed with ongoing or failed builds.Oct 20 2020, 1:24 PM
Closed by commit rG332ff48deea1: [AMDGPU] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans (authored by Paul-C-Anagnostopoulos). · Explain Why
This revision was automatically updated to reflect the committed changes.
Paul-C-Anagnostopoulos added a commit: rG332ff48deea1: [AMDGPU] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans.
foad added a subscriber: foad.Oct 21 2020, 7:15 AM

This inspired me to do some further cleanups in rGf6a5699c6cb5.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
44 lines

Diff 299359

llvm/lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 1,645 Lines • ▼ Show 20 Linesclass getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> { Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
dag ret = dag ret =
!if (!eq(NumSrcArgs, 0), !if (!eq(NumSrcArgs, 0),
// VOP1 without input operands (V_NOP, V_CLREXCP) // VOP1 without input operands (V_NOP, V_CLREXCP)
(ins), (ins),
/* else */ /* else */
!if (!eq(NumSrcArgs, 1), !if (!eq(NumSrcArgs, 1),
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP1 with modifiers // VOP1 with modifiers
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
clampmod0:$clamp, omod0:$omod) clampmod0:$clamp, omod0:$omod)
/* else */, /* else */,
// VOP1 without modifiers // VOP1 without modifiers
!if (!eq(HasIntClamp, 1), !if (HasIntClamp,
(ins Src0RC:$src0, clampmod0:$clamp), (ins Src0RC:$src0, clampmod0:$clamp),
(ins Src0RC:$src0)) (ins Src0RC:$src0))
/* endif */ ), /* endif */ ),
!if (!eq(NumSrcArgs, 2), !if (!eq(NumSrcArgs, 2),
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP 2 with modifiers // VOP 2 with modifiers
!if( !eq(HasOMod, 1), !if(HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
clampmod0:$clamp, omod0:$omod), clampmod0:$clamp, omod0:$omod),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
clampmod0:$clamp)) clampmod0:$clamp))
/* else */, /* else */,
// VOP2 without modifiers // VOP2 without modifiers
!if (!eq(HasIntClamp, 1), !if (HasIntClamp,
(ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp), (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
(ins Src0RC:$src0, Src1RC:$src1)) (ins Src0RC:$src0, Src1RC:$src1))
/* endif */ ) /* endif */ )
/* NumSrcArgs == 3 */, /* NumSrcArgs == 3 */,
!if (!eq(HasModifiers, 1), !if (HasModifiers,
!if (!eq(HasSrc2Mods, 1), !if (HasSrc2Mods,
// VOP3 with modifiers // VOP3 with modifiers
!if (!eq(HasOMod, 1), !if (HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2, Src2Mod:$src2_modifiers, Src2RC:$src2,
clampmod0:$clamp, omod0:$omod), clampmod0:$clamp, omod0:$omod),
!if (!eq(HasIntClamp, 1), !if (HasIntClamp,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2, Src2Mod:$src2_modifiers, Src2RC:$src2,
clampmod0:$clamp), clampmod0:$clamp),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2Mod:$src2_modifiers, Src2RC:$src2))), Src2Mod:$src2_modifiers, Src2RC:$src2))),
// VOP3 with modifiers except src2 // VOP3 with modifiers except src2
!if (!eq(HasOMod, 1), !if (HasOMod,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2, clampmod0:$clamp, omod0:$omod), Src2RC:$src2, clampmod0:$clamp, omod0:$omod),
!if (!eq(HasIntClamp, 1), !if (HasIntClamp,
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2, clampmod0:$clamp), Src2RC:$src2, clampmod0:$clamp),
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
Src2RC:$src2)))) Src2RC:$src2))))
/* else */, /* else */,
// VOP3 without modifiers // VOP3 without modifiers
!if (!eq(HasIntClamp, 1), !if (HasIntClamp,
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod0:$clamp), (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod0:$clamp),
(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)) (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
/* endif */ )))); /* endif */ ))));
} }
/// XXX - src1 may only allow VGPRs? /// XXX - src1 may only allow VGPRs?
// The modifiers (except clamp) are dummy operands for the benefit of // The modifiers (except clamp) are dummy operands for the benefit of
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesclass getInsDPP <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
int NumSrcArgs, bit HasModifiers, int NumSrcArgs, bit HasModifiers,
Operand Src0Mod, Operand Src1Mod> { Operand Src0Mod, Operand Src1Mod> {
dag ret = !if (!eq(NumSrcArgs, 0), dag ret = !if (!eq(NumSrcArgs, 0),
// VOP1 without input operands (V_NOP) // VOP1 without input operands (V_NOP)
(ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl), bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
!if (!eq(NumSrcArgs, 1), !if (!eq(NumSrcArgs, 1),
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP1_DPP with modifiers // VOP1_DPP with modifiers
(ins DstRC:$old, Src0Mod:$src0_modifiers, (ins DstRC:$old, Src0Mod:$src0_modifiers,
Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
/* else */, /* else */,
// VOP1_DPP without modifiers // VOP1_DPP without modifiers
(ins DstRC:$old, Src0RC:$src0, (ins DstRC:$old, Src0RC:$src0,
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
/* endif */) /* endif */)
/* NumSrcArgs == 2 */, /* NumSrcArgs == 2 */,
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP2_DPP with modifiers // VOP2_DPP with modifiers
(ins DstRC:$old, (ins DstRC:$old,
Src0Mod:$src0_modifiers, Src0RC:$src0, Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
/* else */, /* else */,
// VOP2_DPP without modifiers // VOP2_DPP without modifiers
Show All 14 Lines
class getInsDPP8 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC, class getInsDPP8 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
int NumSrcArgs, bit HasModifiers, int NumSrcArgs, bit HasModifiers,
Operand Src0Mod, Operand Src1Mod> { Operand Src0Mod, Operand Src1Mod> {
dag ret = !if (!eq(NumSrcArgs, 0), dag ret = !if (!eq(NumSrcArgs, 0),
// VOP1 without input operands (V_NOP) // VOP1 without input operands (V_NOP)
(ins dpp8:$dpp8, FI:$fi), (ins dpp8:$dpp8, FI:$fi),
!if (!eq(NumSrcArgs, 1), !if (!eq(NumSrcArgs, 1),
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP1_DPP with modifiers // VOP1_DPP with modifiers
(ins DstRC:$old, Src0Mod:$src0_modifiers, (ins DstRC:$old, Src0Mod:$src0_modifiers,
Src0RC:$src0, dpp8:$dpp8, FI:$fi) Src0RC:$src0, dpp8:$dpp8, FI:$fi)
/* else */, /* else */,
// VOP1_DPP without modifiers // VOP1_DPP without modifiers
(ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi) (ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi)
/* endif */) /* endif */)
/* NumSrcArgs == 2 */, /* NumSrcArgs == 2 */,
!if (!eq(HasModifiers, 1), !if (HasModifiers,
// VOP2_DPP with modifiers // VOP2_DPP with modifiers
(ins DstRC:$old, (ins DstRC:$old,
Src0Mod:$src0_modifiers, Src0RC:$src0, Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
dpp8:$dpp8, FI:$fi) dpp8:$dpp8, FI:$fi)
/* else */, /* else */,
// VOP2_DPP without modifiers // VOP2_DPP without modifiers
(ins DstRC:$old, (ins DstRC:$old,
Src0RC:$src0, Src1RC:$src1, dpp8:$dpp8, FI:$fi) Src0RC:$src0, Src1RC:$src1, dpp8:$dpp8, FI:$fi)
/* endif */))); /* endif */)));
} }
// Ins for SDWA // Ins for SDWA
class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs, class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs,
bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod, bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod,
ValueType DstVT> { ValueType DstVT> {
dag ret = !if(!eq(NumSrcArgs, 0), dag ret = !if(!eq(NumSrcArgs, 0),
// VOP1 without input operands (V_NOP) // VOP1 without input operands (V_NOP)
(ins), (ins),
!if(!eq(NumSrcArgs, 1), !if(!eq(NumSrcArgs, 1),
// VOP1 // VOP1
!if(!eq(HasSDWAOMod, 0), !if(!not(HasSDWAOMod),
// VOP1_SDWA without omod // VOP1_SDWA without omod
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
clampmod:$clamp, clampmod:$clamp,
dst_sel:$dst_sel, dst_unused:$dst_unused, dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel), src0_sel:$src0_sel),
// VOP1_SDWA with omod // VOP1_SDWA with omod
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
clampmod:$clamp, omod:$omod, clampmod:$clamp, omod:$omod,
dst_sel:$dst_sel, dst_unused:$dst_unused, dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel)), src0_sel:$src0_sel)),
!if(!eq(NumSrcArgs, 2), !if(!eq(NumSrcArgs, 2),
!if(!eq(DstVT.Size, 1), !if(!eq(DstVT.Size, 1),
// VOPC_SDWA // VOPC_SDWA
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel), clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
// VOP2_SDWA // VOP2_SDWA
!if(!eq(HasSDWAOMod, 0), !if(!not(HasSDWAOMod),
// VOP2_SDWA without omod // VOP2_SDWA without omod
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
Src1Mod:$src1_modifiers, Src1RC:$src1, Src1Mod:$src1_modifiers, Src1RC:$src1,
clampmod:$clamp, clampmod:$clamp,
dst_sel:$dst_sel, dst_unused:$dst_unused, dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel, src1_sel:$src1_sel), src0_sel:$src0_sel, src1_sel:$src1_sel),
// VOP2_SDWA with omod // VOP2_SDWA with omod
(ins Src0Mod:$src0_modifiers, Src0RC:$src0, (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesclass getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
string src1 = !if(!eq(NumSrcArgs, 1), "", string src1 = !if(!eq(NumSrcArgs, 1), "",
!if(!eq(NumSrcArgs, 2), " $src1_modifiers", !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
" $src1_modifiers,")); " $src1_modifiers,"));
string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", ""); string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
string iclamp = !if(HasIntClamp, "$clamp", ""); string iclamp = !if(HasIntClamp, "$clamp", "");
string ret = string ret =
!if(!eq(HasModifiers, 0), !if(!not(HasModifiers),
getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp, getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", "")); dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
} }
// Returns the assembly string for the inputs and outputs of a VOP3P // Returns the assembly string for the inputs and outputs of a VOP3P
// instruction. // instruction.
class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers, class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
bit HasClamp, ValueType DstVT = i32> { bit HasClamp, ValueType DstVT = i32> {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines string dst = !if(HasDst,
!if(!eq(DstVT.Size, 1), !if(!eq(DstVT.Size, 1),
"$sdst", "$sdst",
"$vdst"), "$vdst"),
""); // use $sdst for VOPC ""); // use $sdst for VOPC
string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
string src1 = !if(!eq(NumSrcArgs, 1), "", string src1 = !if(!eq(NumSrcArgs, 1), "",
!if(!eq(NumSrcArgs, 2), " $src1_modifiers", !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
" $src1_modifiers,")); " $src1_modifiers,"));
string args = !if(!eq(HasModifiers, 0), string args = !if(!not(HasModifiers),
getAsm32<0, NumSrcArgs, DstVT>.ret, getAsm32<0, NumSrcArgs, DstVT>.ret,
", "#src0#src1); ", "#src0#src1);
string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
} }
class getAsmDPP16 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { class getAsmDPP16 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
string ret = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret#"$fi"; string ret = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret#"$fi";
} }
class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
string dst = !if(HasDst, string dst = !if(HasDst,
!if(!eq(DstVT.Size, 1), !if(!eq(DstVT.Size, 1),
"$sdst", "$sdst",
"$vdst"), "$vdst"),
""); // use $sdst for VOPC ""); // use $sdst for VOPC
string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
string src1 = !if(!eq(NumSrcArgs, 1), "", string src1 = !if(!eq(NumSrcArgs, 1), "",
!if(!eq(NumSrcArgs, 2), " $src1_modifiers", !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
" $src1_modifiers,")); " $src1_modifiers,"));
string args = !if(!eq(HasModifiers, 0), string args = !if(!not(HasModifiers),
getAsm32<0, NumSrcArgs, DstVT>.ret, getAsm32<0, NumSrcArgs, DstVT>.ret,
", "#src0#src1); ", "#src0#src1);
string ret = dst#args#"$dpp8$fi"; string ret = dst#args#"$dpp8$fi";
} }
class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> { class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
string dst = !if(HasDst, string dst = !if(HasDst,
!if(!eq(DstVT.Size, 1), !if(!eq(DstVT.Size, 1),
Show All 26 Linesclass getAsmSDWA9 <bit HasDst, bit HasOMod, int NumSrcArgs,
ValueType DstVT = i32> { ValueType DstVT = i32> {
string dst = !if(HasDst, string dst = !if(HasDst,
!if(!eq(DstVT.Size, 1), !if(!eq(DstVT.Size, 1),
"$sdst", // VOPC "$sdst", // VOPC
"$vdst"), // VOP1/2 "$vdst"), // VOP1/2
""); "");
string src0 = "$src0_modifiers"; string src0 = "$src0_modifiers";
string src1 = "$src1_modifiers"; string src1 = "$src1_modifiers";
string out_mods = !if(!eq(HasOMod, 0), "$clamp", "$clamp$omod"); string out_mods = !if(!not(HasOMod), "$clamp", "$clamp$omod");
string args = !if(!eq(NumSrcArgs, 0), "", string args = !if(!eq(NumSrcArgs, 0), "",
!if(!eq(NumSrcArgs, 1), !if(!eq(NumSrcArgs, 1),
", "#src0, ", "#src0,
", "#src0#", "#src1 ", "#src0#", "#src1
) )
); );
string sdwa = !if(!eq(NumSrcArgs, 0), "", string sdwa = !if(!eq(NumSrcArgs, 0), "",
!if(!eq(NumSrcArgs, 1), !if(!eq(NumSrcArgs, 1),
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines