[ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate (alternative approach)

[evgeny777]

Summary

As suggested by @andreadb in D89458

[andreadb]

LGTM.

The patch is mostly a mechanical change (i.e. a lot of boilerplate to introduce a new scheduling predicate).

@dmgreen has already verified in D89458 that the ARM changes in the mca test are good.

llvm/lib/MC/MCSchedule.cpp

77

not sure if this is more than 80-cols.

123

same.

llvm/tools/llvm-mca/Views/InstructionInfoView.cpp

106–107

80-col

[dmgreen]

Sounds good to me. Thanks

llvm/include/llvm/MC/MCSubtargetInfo.h

public:
 
   /// Get scheduling itinerary of a CPU.
   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
 
   /// Initialize an InstrItineraryData instance.
   void initInstrItins(InstrItineraryData &InstrItins) const;
 
   /// Resolve a variant scheduling class for the given MCInst and CPU.
-  virtual unsigned
-  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
+  virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
+                                            const MCInst *MI,
+                                            const MCInstrInfo *MCII,
                                             unsigned CPUID) const {
     return 0;
   }
 
   /// Check whether the CPU string is valid.
   bool isCPUStringValid(StringRef CPU) const {
     auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
   }

llvm/include/llvm/Target/TargetInstrPredicate.td

 // it is lowering predicates for MCInst or MachineInstr.
 //
 // In this context, `MCInstFn` and `MachineInstrFn` are both function names.
 class CheckFunctionPredicate<string MCInstFn, string MachineInstrFn> : MCInstPredicate {
   string MCInstFnName = MCInstFn;
   string MachineInstrFnName = MachineInstrFn;
 }
 
+// Similar to CheckFunctionPredicate. However it assumes that MachineInstrFn is
+// a method in TargetInstrInfo, and MCInstrFn takes an extra pointer to
+// MCInstrInfo.
+//
+// It Expands to:
+//  - TIIPointer->MachineInstrFn(MI)
+//  - MCInstrFn(MI, MCII);
+class CheckFunctionPredicateWithTII<string MCInstFn, string MachineInstrFn, string
+TIIPointer = "TII"> : MCInstPredicate {
+  string MCInstFnName = MCInstFn;
+  string TIIPtrName = TIIPointer;
+  string MachineInstrFnName = MachineInstrFn;
+}
+
 // Used to classify machine instructions based on a machine instruction
 // predicate.
 //
 // Let IC be an InstructionEquivalenceClass definition, and MI a machine
 // instruction.  We say that MI belongs to the equivalence class described by IC
 // if and only if the following two conditions are met:
 //  a) MI's opcode is in the `opcodes` set, and
 //  b) `Predicate` evaluates to true when applied to MI.

llvm/lib/MC/MCSchedule.cpp

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
                                       const MCInst &Inst) const {
   unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
   const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
   if (!SCDesc->isValid())
     return 0;
 
   unsigned CPUID = getProcessorID();
   while (SCDesc->isVariant()) {
-    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
+    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
     SCDesc = getSchedClassDesc(SchedClass);
   }
 
   if (SchedClass)
     return MCSchedModel::computeInstrLatency(STI, *SCDesc);
 
   llvm_unreachable("unsupported variant scheduling class");
 }
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
 
   // If there's no valid class, assume that the instruction executes/completes
   // at the maximum issue width.
   if (!SCDesc->isValid())
     return 1.0 / IssueWidth;
 
   unsigned CPUID = getProcessorID();
   while (SCDesc->isVariant()) {
-    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
+    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
     SCDesc = getSchedClassDesc(SchedClass);
   }
 
   if (SchedClass)
     return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
 
   llvm_unreachable("unsupported variant scheduling class");
 }

llvm/lib/MCA/InstrBuilder.cpp

InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   // Then obtain the scheduling class information from the instruction.
   unsigned SchedClassID = MCDesc.getSchedClass();
   bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant();
 
   // Try to solve variant scheduling classes.
   if (IsVariant) {
     unsigned CPUID = SM.getProcessorID();
     while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
-      SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
+      SchedClassID =
+          STI.resolveVariantSchedClass(SchedClassID, &MCI, &MCII, CPUID);
 
     if (!SchedClassID) {
       return make_error<InstructionError<MCInst>>(
           "unable to resolve scheduling class for write variant.", MCI);
     }
   }
 
   // Check if this instruction is supported. Otherwise, report an error.

llvm/lib/Target/ARM/ARMSchedule.td

def : PredicateProlog<[{
   const ARMBaseInstrInfo *TII =
     static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
   (void)TII;
   const ARMSubtarget *STI =
     static_cast<const ARMSubtarget*>(SchedModel->getSubtargetInfo());
   (void)STI;
 }]>;
 
-def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(*MI)}]>;
+def IsPredicated : CheckFunctionPredicateWithTII<
+  "ARM_MC::isPredicated",
+  "isPredicated"
+>;
+def IsPredicatedPred : MCSchedPredicate<IsPredicated>;
 
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
 
+bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
+
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

if (TT.isOSWindows()) {
     if (!ARMArchFeature.empty())
       ARMArchFeature += ",";
     ARMArchFeature += "+noarm";
   }
 
   return ARMArchFeature;
 }
 
+bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
+  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
+  int PredOpIdx = Desc.findFirstPredOperandIdx();
+  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
+}
+
 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = std::string(FS);

llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsr #9
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, asr #4
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, ror #6
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        mvneq r2, r3
 # CHECK-NEXT:  1      1     0.50                        mvnseq  r2, r3, lsl #10
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsl r7
 # CHECK-NEXT:  1      1     0.50                        mvns  r5, r6, lsr r7
-# CHECK-NEXT:  1      1     0.50                        mvngt r5, r6, asr r7
-# CHECK-NEXT:  1      1     0.50                        mvnslt  r5, r6, ror r7
+# CHECK-NEXT:  1      2     0.50                        mvngt r5, r6, asr r7
+# CHECK-NEXT:  1      2     0.50                        mvnslt  r5, r6, ror r7
 # CHECK-NEXT:  0      0     0.00    *      *      U     nop
 # CHECK-NEXT:  0      0     0.00    *      *      U     nopgt
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        orr r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        orr r4, r5, r6, lsr #5

 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        orr r4, r4, r5, rrx
 # CHECK-NEXT:  1      1     0.50                        orrseq  r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orrne r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        orrseq  r4, r5, r6, lsl #5
-# CHECK-NEXT:  1      2     1.00                        orrlo r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        orrlo r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        orrshi  r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        orrhs r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orrseq  r4, r4, r5
-# CHECK-NEXT:  1      2     1.00                        orrne r6, r6, r7, asr r9
-# CHECK-NEXT:  1      2     1.00                        orrslt  r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     0.50                        orrne r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     0.50                        orrslt  r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        orrsgt  r4, r4, r5, rrx
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #15

 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsblo r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, ror #5
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, asr r9
-# CHECK-NEXT:  1      2     1.00                        rsble r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        rsble r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        rsb r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                  U     rsb r4, r4, r5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsbne r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, ror #5
-# CHECK-NEXT:  1      2     1.00                        rsbgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     0.50                        rsbgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, rrx
 # CHECK-NEXT:  1      1     0.50                        rsbs  r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        rsbs  r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        rsc r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        rsc r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        rsc r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                  U     rsc r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsclo r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, ror #5
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, asr r9
-# CHECK-NEXT:  1      2     1.00                        rscle r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        rscle r6, r7, r8, ror r9
 # CHECK-NEXT:  1      1     0.50                        rsc r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                  U     rsc r4, r4, r5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rscne r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, ror #5
-# CHECK-NEXT:  1      2     1.00                        rscgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     0.50                        rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  1      1     0.50                        rrx r0, r1
 # CHECK-NEXT:  1      1     0.50                        rrx sp, pc
 # CHECK-NEXT:  1      1     0.50                        rrx pc, lr
 # CHECK-NEXT:  1      1     0.50                        rrx lr, sp
 # CHECK-NEXT:  1      1     0.50                        rrxs  r0, r1
 # CHECK-NEXT:  1      1     0.50                        rrxs  sp, pc
 # CHECK-NEXT:  1      1     0.50                        rrxs  pc, lr
 # CHECK-NEXT:  1      1     0.50                        rrxs  lr, sp
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd16  r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     sadd16gt  r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     sadd16gt  r1, r2, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd8 r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     sadd8le r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     sadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     sasx  r9, r12, r0
-# CHECK-NEXT:  2      3     1.00    *      *      U     sasxeq  r9, r12, r0
+# CHECK-NEXT:  2      5     1.00    *      *      U     sasxeq  r9, r12, r0
 # CHECK-NEXT:  1      1     0.50                        sbc r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        sbc r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        sbc r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        sbc r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, asr #5

 # CHECK-NEXT:  1      2     1.00                        sbc r4, r4, r5, ror #5
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, ror r9
 # CHECK-NEXT:  1      1     0.50                  U     sbfx  r4, r5, #16, #1
 # CHECK-NEXT:  1      1     0.50                  U     sbfxgt  r4, r5, #16, #16
 # CHECK-NEXT:  1      1     0.50    *                   sel r9, r2, r1
-# CHECK-NEXT:  1      1     0.50    *                   selne r9, r2, r1
+# CHECK-NEXT:  1      2     0.50    *                   selne r9, r2, r1
 # CHECK-NEXT:  0      0     0.00                  U     setend  be
 # CHECK-NEXT:  0      0     0.00                  U     setend  le
 # CHECK-NEXT:  0      0     0.00    *      *      U     sev
 # CHECK-NEXT:  0      0     0.00    *      *      U     seveq
 # CHECK-NEXT:  1      2     1.00                        shadd16 r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd16gt r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd8  r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd8gt  r4, r8, r2

 # CHECK-NEXT:  0      0     0.00                  U     srsia sp!, #5
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, lsl #31
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, asr #32
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, asr #1
 # CHECK-NEXT:  1      2     1.00                        ssat16  r2, #1, r7
 # CHECK-NEXT:  1      2     1.00                        ssat16  r3, #16, r5
 # CHECK-NEXT:  2      3     1.00    *      *      U     ssax  r2, r3, r4
-# CHECK-NEXT:  2      3     1.00    *      *      U     ssaxlt  r2, r3, r4
+# CHECK-NEXT:  2      5     1.00    *      *      U     ssaxlt  r2, r3, r4
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub16  r1, r0, r6
-# CHECK-NEXT:  2      2     1.00    *      *      U     ssub16ne  r5, r3, r2
+# CHECK-NEXT:  2      4     1.00    *      *      U     ssub16ne  r5, r3, r2
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub8 r9, r2, r4
-# CHECK-NEXT:  2      2     1.00    *      *      U     ssub8eq r5, r1, r2
+# CHECK-NEXT:  2      4     1.00    *      *      U     ssub8eq r5, r1, r2
 # CHECK-NEXT:  1      2     1.00           *            stm r2, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stm r3, {r1, r3, r4, r5, r6, lr}
 # CHECK-NEXT:  1      2     1.00           *            stmib r4, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stmda r5, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stmdb r6, {r1, r3, r4, r5, r6, r8}
 # CHECK-NEXT:  1      2     1.00           *            stmdb sp, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  2      2     1.00           *            stm r8!, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  2      2     1.00           *            stmib r9!, {r1, r3, r4, r5, r6, sp}

 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, ror #5
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, ror r9
 # CHECK-NEXT:  2      2     1.00    *      *      U     uadd16  r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     uadd16gt  r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     uadd16gt  r1, r2, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     uadd8 r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     uadd8le r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     uadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     uasx  r9, r12, r0
-# CHECK-NEXT:  2      3     1.00    *      *      U     uasxeq  r9, r12, r0
+# CHECK-NEXT:  2      5     1.00    *      *      U     uasxeq  r9, r12, r0
 # CHECK-NEXT:  1      1     0.50                  U     ubfx  r4, r5, #16, #1
 # CHECK-NEXT:  1      1     0.50                  U     ubfxgt  r4, r5, #16, #16
 # CHECK-NEXT:  1      2     1.00                        uhadd16 r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd16gt r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd8  r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd8gt  r4, r8, r2
 # CHECK-NEXT:  2      3     1.00                        uhasx r4, r8, r2
 # CHECK-NEXT:  2      3     1.00                        uhasxgt r4, r8, r2

 # CHECK-NEXT:  1      2     1.00                        usat  r8, #1, r10
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #4, r10
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #5, r10, lsl #31
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #31, r10, asr #32
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #16, r10, asr #1
 # CHECK-NEXT:  1      2     1.00                        usat16  r2, #2, r7
 # CHECK-NEXT:  1      2     1.00                        usat16  r3, #15, r5
 # CHECK-NEXT:  2      3     1.00    *      *      U     usax  r2, r3, r4
-# CHECK-NEXT:  2      3     1.00    *      *      U     usaxne  r2, r3, r4
+# CHECK-NEXT:  2      5     1.00    *      *      U     usaxne  r2, r3, r4
 # CHECK-NEXT:  2      2     1.00    *      *      U     usub16  r4, r2, r7
-# CHECK-NEXT:  2      2     1.00    *      *      U     usub16hi  r1, r1, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     usub16hi  r1, r1, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     usub8 r1, r8, r5
-# CHECK-NEXT:  2      2     1.00    *      *      U     usub8le r9, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     usub8le r9, r2, r3
 # CHECK-NEXT:  1      2     1.00                        uxtab r2, r3, r4
 # CHECK-NEXT:  1      2     1.00                        uxtab r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        uxtablt r6, r2, r9, ror #8
 # CHECK-NEXT:  1      2     1.00                        uxtab r5, r1, r4, ror #16
 # CHECK-NEXT:  1      2     1.00                        uxtab r7, r8, r3, ror #24
 # CHECK-NEXT:  1      4     1.00                        uxtab16ge r0, r1, r4
 # CHECK-NEXT:  1      4     1.00                        uxtab16 r6, r2, r7
 # CHECK-NEXT:  1      4     1.00                        uxtab16 r3, r5, r8, ror #8

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT: 8.00   158.50 158.50 171.00 497.00 12.00   -      -
+# CHECK-NEXT: 8.00   162.00 162.00 171.00 490.00 12.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #983040

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r4, r4, r5, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq  r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrne r4, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrseq  r4, r5, r6, lsl #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrlo r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrlo r6, r7, r8, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrshi  r4, r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrhs r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq  r4, r4, r5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrne r6, r6, r7, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrslt  r6, r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrne r6, r6, r7, asr r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrslt  r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrsgt  r4, r4, r5, rrx
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #15

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsblo r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsble r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsble r6, r7, r8, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb r4, r4, r5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbne r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, ror #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs  r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs  r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsclo r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscle r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rscle r6, r7, r8, ror r9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r4, r5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscne r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, ror #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx r0, r1
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx sp, pc
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx pc, lr
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx lr, sp
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  r0, r1

llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp

: SchedClassId(ResolvedSchedClassId),
       NonRedundantWriteProcRes(getNonRedundantWriteProcRes(*SCDesc, STI)),
       IdealizedProcResPressure(computeIdealizedProcResPressure(
           STI.getSchedModel(), NonRedundantWriteProcRes)) {
   assert((SCDesc == nullptr || !SCDesc->isVariant()) &&
          "ResolvedSchedClass should never be variant");
 }
 
 static unsigned ResolveVariantSchedClassId(const MCSubtargetInfo &STI,
+                                           const MCInstrInfo &InstrInfo,
                                            unsigned SchedClassId,
                                            const MCInst &MCI) {
   const auto &SM = STI.getSchedModel();
-  while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant())
-    SchedClassId =
-        STI.resolveVariantSchedClass(SchedClassId, &MCI, SM.getProcessorID());
+  while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant()) {
+    SchedClassId = STI.resolveVariantSchedClass(SchedClassId, &MCI, &InstrInfo,
+                                                SM.getProcessorID());
+  }
   return SchedClassId;
 }
 
 std::pair<unsigned /*SchedClassId*/, bool /*WasVariant*/>
 ResolvedSchedClass::resolveSchedClassId(const MCSubtargetInfo &SubtargetInfo,
                                         const MCInstrInfo &InstrInfo,
                                         const MCInst &MCI) {
   unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
   const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel()
                                               .getSchedClassDesc(SchedClassId)
                                               ->isVariant();
-  SchedClassId = ResolveVariantSchedClassId(SubtargetInfo, SchedClassId, MCI);
+  SchedClassId =
+      ResolveVariantSchedClassId(SubtargetInfo, InstrInfo, SchedClassId, MCI);
   return std::make_pair(SchedClassId, WasVariant);
 }
 
 // Returns a ProxResIdx by id or name.
 static unsigned findProcResIdx(const MCSubtargetInfo &STI,
                                const StringRef NameOrId) {
   // Interpret the key as an ProcResIdx.
   unsigned ProcResIdx = 0;

llvm/tools/llvm-mca/Views/InstructionInfoView.cpp

for (auto I : zip(getSource(), IIVD)) {
     const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
 
     // Obtain the scheduling class information from the instruction.
     unsigned SchedClassID = MCDesc.getSchedClass();
     unsigned CPUID = SM.getProcessorID();
 
     // Try to solve variant scheduling classes.
     while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
-      SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);
+      SchedClassID =
+          STI.resolveVariantSchedClass(SchedClassID, &Inst, &MCII, CPUID);
 
     const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
     IIVDEntry.NumMicroOpcodes = SCDesc.NumMicroOps;
     IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
     // Add extra latency due to delays in the forwarding data paths.
     IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles(
         STI.getReadAdvanceEntries(SCDesc));
     IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc);
     IIVDEntry.mayLoad = MCDesc.mayLoad();
     IIVDEntry.mayStore = MCDesc.mayStore();
     IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
   }
 }
 } // namespace mca.
 } // namespace llvm

llvm/utils/TableGen/PredicateExpander.h

public:
   void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
                                bool IsCheckAll);
   void expandTIIFunctionCall(raw_ostream &OS, StringRef MethodName);
   void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
   void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
   void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
   void expandCheckFunctionPredicate(raw_ostream &OS, StringRef MCInstFn,
                                     StringRef MachineInstrFn);
+  void expandCheckFunctionPredicateWithTII(raw_ostream &OS, StringRef MCInstFn,
+                                           StringRef MachineInstrFn,
+                                           StringRef TIIPtr);
   void expandCheckNonPortable(raw_ostream &OS, StringRef CodeBlock);
   void expandPredicate(raw_ostream &OS, const Record *Rec);
   void expandReturnStatement(raw_ostream &OS, const Record *Rec);
   void expandOpcodeSwitchCase(raw_ostream &OS, const Record *Rec);
   void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
                                    const Record *Default);
   void expandStatement(raw_ostream &OS, const Record *Rec);
 };

llvm/utils/TableGen/PredicateExpander.cpp

OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
      << "getOperand(" << OpIndex << ").isReg() ";
 }
 
 void PredicateExpander::expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) {
   OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
      << "getOperand(" << OpIndex << ").isImm() ";
 }
 
+void PredicateExpander::expandCheckFunctionPredicateWithTII(
+    raw_ostream &OS, StringRef MCInstFn, StringRef MachineInstrFn,
+    StringRef TIIPtr) {
+  if (!shouldExpandForMC()) {
+    OS << (TIIPtr.empty() ? "TII" : TIIPtr) << "->" << MachineInstrFn;
+    OS << (isByRef() ? "(MI)" : "(*MI)");
+    return;
+  }
+
+  OS << MCInstFn << (isByRef() ? "(MI" : "(*MI") << ", MCII)";
+}
+
 void PredicateExpander::expandCheckFunctionPredicate(raw_ostream &OS,
                                                      StringRef MCInstFn,
                                                      StringRef MachineInstrFn) {
   OS << (shouldExpandForMC() ? MCInstFn : MachineInstrFn)
      << (isByRef() ? "(MI)" : "(*MI)");
 }
 
 void PredicateExpander::expandCheckNonPortable(raw_ostream &OS,
void PredicateExpander::expandPredicate(raw_ostream &OS, const Record *Rec) {
   if (Rec->isSubClassOf("CheckAll"))
     return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
                                    /* AllOf */ true);
 
   if (Rec->isSubClassOf("CheckAny"))
     return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
                                    /* AllOf */ false);
 
-  if (Rec->isSubClassOf("CheckFunctionPredicate"))
+  if (Rec->isSubClassOf("CheckFunctionPredicate")) {
     return expandCheckFunctionPredicate(
         OS, Rec->getValueAsString("MCInstFnName"),
         Rec->getValueAsString("MachineInstrFnName"));
+  }
+
+  if (Rec->isSubClassOf("CheckFunctionPredicateWithTII")) {
+    return expandCheckFunctionPredicateWithTII(
+        OS, Rec->getValueAsString("MCInstFnName"),
+        Rec->getValueAsString("MachineInstrFnName"),
+        Rec->getValueAsString("TIIPtrName"));
+  }
 
   if (Rec->isSubClassOf("CheckNonPortable"))
     return expandCheckNonPortable(OS, Rec->getValueAsString("CodeBlock"));
 
   if (Rec->isSubClassOf("TIIPredicate"))
     return expandTIIFunctionCall(OS, Rec->getValueAsString("FunctionName"));
 
   llvm_unreachable("No known rules to expand this MCInstPredicate");

llvm/utils/TableGen/SubtargetEmitter.cpp

void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
 
   // Emit target predicates.
   emitSchedModelHelpersImpl(OS);
 
   OS << "} // " << ClassName << "::resolveSchedClass\n\n";
 
   OS << "unsigned " << ClassName
      << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
-     << " unsigned CPUID) const {\n"
+     << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
      << "  return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);\n"
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
      << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
 
   STIPredicateExpander PE(Target);
   PE.setClassPrefix(ClassName);
   PE.setExpandDefinition(true);
   PE.setByRef(false);
   PE.setIndentLevel(0);
 
void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
   }
 
   OS << "}\n";
 }
 
 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
-     << "    const MCInst *MI, unsigned CPUID) {\n";
+     << "    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
   emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
   OS << "}\n";
   OS << "} // end namespace " << Target << "_MC\n\n";
 
   OS << "struct " << Target
      << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
   OS << "  " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
      << "    StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
      << "    ArrayRef<SubtargetFeatureKV> PF,\n"
      << "    ArrayRef<SubtargetSubTypeKV> PD,\n"
      << "    const MCWriteProcResEntry *WPR,\n"
      << "    const MCWriteLatencyEntry *WL,\n"
      << "    const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
      << "    const unsigned *OC, const unsigned *FP) :\n"
      << "      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,\n"
      << "                      WPR, WL, RA, IS, OC, FP) { }\n\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
-     << "      const MCInst *MI, unsigned CPUID) const override {\n"
+     << "      const MCInst *MI, const MCInstrInfo *MCII,\n"
+     << "      unsigned CPUID) const override {\n"
      << "    return " << Target << "_MC"
-     << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); \n";
+     << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID); \n";
   OS << "  }\n";
   if (TGT.getHwModes().getNumModeIds() > 1)
     OS << "  unsigned getHwMode() const override;\n";
   OS << "};\n";
   EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
 }
 
 void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) {
#endif
   OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
   OS << "#undef GET_SUBTARGETINFO_HEADER\n\n";
 
   std::string ClassName = Target + "GenSubtargetInfo";
   OS << "namespace llvm {\n";
   OS << "class DFAPacketizer;\n";
   OS << "namespace " << Target << "_MC {\n"
      << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
-     << " const MCInst *MI, unsigned CPUID);\n"
+     << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
      << "} // end namespace " << Target << "_MC\n\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
      << "StringRef TuneCPU, StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,"
-     << " const MCInst *MI, unsigned CPUID) const override;\n"
+     << " const MCInst *MI, const MCInstrInfo *MCII,"
+     << " unsigned CPUID) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n";
   if (TGT.getHwModes().getNumModeIds() > 1)
     OS << "  unsigned getHwMode() const override;\n";
 
   STIPredicateExpander PE(Target);
   PE.setByRef(false);
   for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())