[ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate

[evgeny777]

Summary

Depends on D89458

[evgeny777]

Rebased

[dmgreen]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

193

It's not possible to check this is a Def?

I see a mvneq is not changed though. I'm guessing that predicate info is not added to MCInsts?

[andreadb]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

193

To check if a machine operand is a definition you need the MCInstrDesc.
But then, to obtain the MCInstrDesc you need to query the MCInstrInfo (method get()).

I think that it should be possible to use the new predicate introduced by D89553 to define functions that also check if operands are definitons.

[evgeny777]

Addressed.
@dmgreen There is no predicate for basic (w/o shift) moves in A57 model, that's why mvneq is not touched.

[dmgreen]

Alright. I hadn't seen that the variant for IsCPSRDefinedAndPredicatedPred == IsPredicatedPred for MVN's too.

Thanks for adding the def check. LGTM.

llvm/lib/Target/ARM/ARMSchedule.td

 }]>;
 
 def IsPredicated : CheckFunctionPredicateWithTII<
   "ARM_MC::isPredicated",
   "isPredicated"
 >;
 def IsPredicatedPred : MCSchedPredicate<IsPredicated>;
 
+def IsCPSRDefined : CheckFunctionPredicateWithTII<
+  "ARM_MC::isCPSRDefined",
+  "ARMBaseInstrInfo::isCPSRDefined"
+>;
+
+def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;
 def IIC_iALUsir    : InstrItinClass;

llvm/lib/Target/ARM/ARMScheduleA57.td

 // The Cortex-A57 is a traditional superscalar microprocessor with a
 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
 // much wider out-of-order issue stage, this produced a need to carefully
 // schedule micro-ops so that all three decoded each cycle are successfully
 // issued as the reservation station(s) simply don't stay occupied for long.
 // Therefore, IssueWidth is set to the narrower of the two at three, while still
 // modeling the machine as out-of-order.
 
-def IsCPSRDefinedPred : SchedPredicate<[{TII->isCPSRDefined(*MI)}]>;
+def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;
 def IsCPSRDefinedAndPredicatedPred :
-  SchedPredicate<[{TII->isCPSRDefined(*MI) && TII->isPredicated(*MI)}]>;
+    MCSchedPredicate<IsCPSRDefinedAndPredicated>;
 
 // Cortex A57 rev. r1p0 or later (false = r0px)
 def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
 
 // If Addrmode3 contains register offset (not immediate)
 def IsLdrAm3RegOffPred :
   SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 1)}]>;
 // The same predicate with operand offset 2 and 3:

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class raw_ostream;
 class raw_pwrite_stream;
 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
 
 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
+bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 }
 
 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
   const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
   int PredOpIdx = Desc.findFirstPredOperandIdx();
   return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
 }
 
+bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
+  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
+  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
+    const MCOperand &MO = MI.getOperand(I);
+    if (MO.isReg() && MO.getReg() == ARM::CPSR &&
+        Desc.OpInfo[I].isOptionalDef())
+      return true;
+  }
+  return false;
+}
+
 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = std::string(FS);

llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

 # CHECK-NEXT:  1      1     0.50                        mvn r2, r3
 # CHECK-NEXT:  1      1     0.50                        mvns  r2, r3
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsl #19
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsr #9
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, asr #4
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, ror #6
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        mvneq r2, r3
-# CHECK-NEXT:  1      1     0.50                        mvnseq  r2, r3, lsl #10
+# CHECK-NEXT:  1      2     1.00                        mvnseq  r2, r3, lsl #10
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsl r7
-# CHECK-NEXT:  1      1     0.50                        mvns  r5, r6, lsr r7
+# CHECK-NEXT:  1      2     1.00                        mvns  r5, r6, lsr r7
 # CHECK-NEXT:  1      2     0.50                        mvngt r5, r6, asr r7
 # CHECK-NEXT:  1      2     0.50                        mvnslt  r5, r6, ror r7
 # CHECK-NEXT:  0      0     0.00    *      *      U     nop
 # CHECK-NEXT:  0      0     0.00    *      *      U     nopgt
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, r6

 # CHECK-NEXT:  1      2     0.50                        rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  1      1     0.50                        rrx r0, r1
 # CHECK-NEXT:  1      1     0.50                        rrx sp, pc
 # CHECK-NEXT:  1      1     0.50                        rrx pc, lr
 # CHECK-NEXT:  1      1     0.50                        rrx lr, sp
-# CHECK-NEXT:  1      1     0.50                        rrxs  r0, r1
-# CHECK-NEXT:  1      1     0.50                        rrxs  sp, pc
-# CHECK-NEXT:  1      1     0.50                        rrxs  pc, lr
-# CHECK-NEXT:  1      1     0.50                        rrxs  lr, sp
+# CHECK-NEXT:  1      2     1.00                        rrxs  r0, r1
+# CHECK-NEXT:  1      2     1.00                        rrxs  sp, pc
+# CHECK-NEXT:  1      2     1.00                        rrxs  pc, lr
+# CHECK-NEXT:  1      2     1.00                        rrxs  lr, sp
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd16  r1, r2, r3
 # CHECK-NEXT:  2      4     1.00    *      *      U     sadd16gt  r1, r2, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd8 r1, r2, r3
 # CHECK-NEXT:  2      4     1.00    *      *      U     sadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     sasx  r9, r12, r0
 # CHECK-NEXT:  2      5     1.00    *      *      U     sasxeq  r9, r12, r0
 # CHECK-NEXT:  1      1     0.50                        sbc r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        sbc r7, r8, #-2147483638

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT: 8.00   162.00 162.00 171.00 490.00 12.00   -      -
+# CHECK-NEXT: 8.00   159.00 159.00 171.00 496.00 12.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #983040

 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns  r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, lsl #19
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, lsr #9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, asr #4
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, ror #6
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvneq r2, r3
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvnseq  r2, r3, lsl #10
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mvnseq  r2, r3, lsl #10
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvn r5, r6, lsl r7
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvns  r5, r6, lsr r7
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     mvns  r5, r6, lsr r7
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvngt r5, r6, asr r7
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     mvnslt  r5, r6, ror r7
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     nop
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     nopgt
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orr r4, r5, r6

 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx r0, r1
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx sp, pc
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx pc, lr
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx lr, sp
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  r0, r1
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  sp, pc
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  pc, lr
-# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  lr, sp
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rrxs  r0, r1
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rrxs  sp, pc
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rrxs  pc, lr
+# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rrxs  lr, sp
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd16  r1, r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd16gt  r1, r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd8 r1, r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sadd8le r1, r2, r3
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sasx  r9, r12, r0
 # CHECK-NEXT:  -     0.50   0.50    -     1.00    -      -      -     sasxeq  r9, r12, r0
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     sbc r7, r8, #-2147483638