[ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate

[evgeny777]

Summary

Patch allows llvm-mca to correcty detect latencies of conditional ops.

[evgeny777]

Removed wrongly added file from diff

[andreadb]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

183–186

It is unfortunate that the MCSchedPredicate framework is not expressive enough to let users define predicates on MCInstrDesc.

Your idea of adding an extra field (a MCInstrDesc pointer) to MCInst does solve the issue.
To be honest, at the moment I don't think that there are other ways to fix this issue. The only alternative is to expand/improve the MCSchedPredicate framework. However, it is not a simple task, and it would requires modifications to the SubtargetEmitter, the InstructionInfoEmitter and the PredicateExpander.

[evgeny777]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

183–186

The only alternative is to expand/improve the MCSchedPredicate framework. However, it is not a simple task, and it would requires modifications to the SubtargetEmitter, the InstructionInfoEmitter and the PredicateExpander.

I tried adding extra parameter (MCInstrInfo) to resolveVariantSchedClass and resolveVariantSchedClassImpl, updating SubtargetEmitter and all callers (llvm-mca, llvm-exegesis, etc) respectively. However I didn't like the result much due to

• lots of code modification
• all MC predicates will have two parameters, which codegen predicates have only one, so PredicateExpander should be modified (like you said)
• most of MC predicates likely won't need MCInstrDesc.

Looking at MachineInstr I found getDesc/setDesc and decided to use similar approach for MCInst.

[evgeny777]

Removed commented line of code

[andreadb]

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

183–186

Yeah.

I agree with you that having a pointer to the instruction descriptor is quite convenient. It simplifies some interactions and avoids that we always keep around a reference to the MCInstrInfo. So, if other people are happy with it, then I am OK too.

Yesterday I was trying to prototype something to workaround that issue, and I think I ended up doing exactly the same modifications (i.e. adding an extra MCInstrInfo* operand to resolveVariantSchedClass).
However I think (although I didn't test it yet) that you can probably implement something simpler by introducing only a new predicate, and not having to touch existing predicates.

The main problem in your case was that CheckFunctionPredicate is not very good because it assumes a single operand in input to the function (i.e. a MachineInstr/MCInst operand).

We could introduce a CheckFunctionPredicateWithMCII<string MCInstFn, string MachineInstrFn>

which is similar in principle to CheckFunctionPredicate, but it assumes that the MachineInstrFn is a method of TII, and MCInstrFn is just a normal function that also takes a pointer to MCII in input. So, something that expands to either of:

• TII->MachineInstrFn(MI);
• MCInstFn(MI, MCII).

Basically, same idea, but extra MCII operand.
That would obviously require that MCII is accessible somehow (hence the need of that change to the signature of resolveVariantSchedClass - so that MCII is always available).

If that works, then your new function would be become like this:

bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo* MCII) {
  const MCInstrDesc& Desc = MCII->get(MI.getOpcode());
  int PredOpIdx = Desc.findFirstPredOperandIdx();
  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
}

In conclusion:
I am not against the idea of adding an extra field to MCInst since it may be useful in general (maybe not just for mca).
It definitely simplifies writing portable predicates that can be used by mca. It is a pragmatic approach after all, and - as you wrote - we already do something similar in MachineInstr.

An alternative approach, would require a change to the resolveVariant signature, and the introduction of a new predicate. As you wrote , the downside is that it introduces code modifications in a few places (at least in the SubtargetEmitter, MCSchedule.h (functionalities that need to resolve scheduling classes to compute latency/throughput), and llvm-mca/exegesis (since those obviously need to resolve latency/throughput). That being said, those are mostly mechanical changes (I personally don't think it is a problem to change those tools).

[evgeny777]

The main problem in your case was that CheckFunctionPredicate is not very good because it assumes a single operand in input to the function (i.e. a MachineInstr/MCInst operand).

Exactly :). When I realized that new CheckFunction-like predicate should be introduced to cope with changed function signature I switch to getDesc/setDesc approach. Ok, let's wait for others.

[andreadb]

For the record, this is how your patch would look like if you decided to add a new predicate.

alternative-approach.diff27 KBDownload

I am just trying to be helpful by showing how the alternative approach would look like (in case, if people decide that it is not a good idea to add an extra field to MCInst).

P.s.: I still think that your approach is simpler.

[evgeny777]

Thanks! I've created D89553 for this

[dmgreen]

ARM changes look good to me.

This adds an extra pointer into MCInst? So something like changing an instruction from 32byte + 16bytes per operand to 40bytes + 16bytes per operand. I'm not sure how much a change like that would matter, but if we have the other patch and we don't know of any other uses for Desc, perhaps that is the more conservative route. I don't have a very strong opinions either way though.

[andreadb]

I have been thinking a bit more about this patch.
D89553 is surprisingly less complicated than I have originally thought it was. It definitely touches more files. However the majority of the changes are very mechanical (mostly boilerplate required for the new MCSchedPredicate to work). It is also a non-controversial change, since it doesn't modify the layout of MCInst.
Bonus point: by changing the signature of resolveVariantSchedClass() we potentially enable future developments in the area of MCSchedPredicate (and mca). Basically that change would make it possible for users to declare new predicates on MCinstrDesc (which is definitely not a bad thing!).

The more I look at D89553, the more I feel confident that it may be the right way to go. So, if you and @dmgreen are also happy with D89553, then please consider committing that patch instead of this one.

Thanks!

[evgeny777]

D89553 was pushed instead

llvm/include/llvm/MC/MCInst.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCINST_H
 #define LLVM_MC_MCINST_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/SMLoc.h"
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 
 namespace llvm {
 
 class MCExpr;
class MCInst {
   unsigned Opcode = 0;
   // These flags could be used to pass some info from one target subcomponent
   // to another, for example, from disassembler to asm printer. The values of
   // the flags have any sense on target level only (e.g. prefixes on x86).
   unsigned Flags = 0;
 
   SMLoc Loc;
   SmallVector<MCOperand, 8> Operands;
+  const MCInstrDesc *Desc = nullptr;
 
 public:
   MCInst() = default;
 
   void setOpcode(unsigned Op) { Opcode = Op; }
   unsigned getOpcode() const { return Opcode; }
 
+  void setDesc(const MCInstrDesc *D) { Desc = D; }
+  const MCInstrDesc *getDesc() const { return Desc; }
+
   void setFlags(unsigned F) { Flags = F; }
   unsigned getFlags() const { return Flags; }
 
   void setLoc(SMLoc loc) { Loc = loc; }
   SMLoc getLoc() const { return Loc; }
 
   const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
   MCOperand &getOperand(unsigned i) { return Operands[i]; }

llvm/lib/Target/ARM/ARMSchedule.td

def : PredicateProlog<[{
   const ARMBaseInstrInfo *TII =
     static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
   (void)TII;
   const ARMSubtarget *STI =
     static_cast<const ARMSubtarget*>(SchedModel->getSubtargetInfo());
   (void)STI;
 }]>;
 
-def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(*MI)}]>;
+def IsPredicated : CheckFunctionPredicate<
+  "ARM_MC::isPredicated",
+  "TII->isPredicated"
+>;
+def IsPredicatedPred : MCSchedPredicate<IsPredicated>;
 
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case Match_Success:
     forwardVPTPosition();
 
     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
     // doesn't actually encode.
     if (Inst.getOpcode() == ARM::ITasm)
       return false;
 
     Inst.setLoc(IDLoc);
+    Inst.setDesc(&MII.get(Inst.getOpcode()));
     if (PendConditionalInstruction) {
       PendingConditionalInsts.push_back(Inst);
       if (isITBlockFull() || isITBlockTerminator(Inst))
         flushPendingInstructions(Out);
     } else {
       Out.emitInstruction(Inst, getSTI());
     }
     return false;

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
 
+bool isPredicated(const MCInst &MI);
+
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

if (TT.isOSWindows()) {
     if (!ARMArchFeature.empty())
       ARMArchFeature += ",";
     ARMArchFeature += "+noarm";
   }
 
   return ARMArchFeature;
 }
 
+bool ARM_MC::isPredicated(const MCInst &MI) {
+  int PredOpIdx = MI.getDesc()->findFirstPredOperandIdx();
+  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
+}
+
 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = std::string(FS);

llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsr #9
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, asr #4
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, ror #6
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        mvneq r2, r3
 # CHECK-NEXT:  1      1     0.50                        mvnseq  r2, r3, lsl #10
 # CHECK-NEXT:  1      1     0.50                        mvn r5, r6, lsl r7
 # CHECK-NEXT:  1      1     0.50                        mvns  r5, r6, lsr r7
-# CHECK-NEXT:  1      1     0.50                        mvngt r5, r6, asr r7
-# CHECK-NEXT:  1      1     0.50                        mvnslt  r5, r6, ror r7
+# CHECK-NEXT:  1      2     0.50                        mvngt r5, r6, asr r7
+# CHECK-NEXT:  1      2     0.50                        mvnslt  r5, r6, ror r7
 # CHECK-NEXT:  0      0     0.00    *      *      U     nop
 # CHECK-NEXT:  0      0     0.00    *      *      U     nopgt
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        orr r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        orr r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        orr r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        orr r4, r5, r6, lsr #5

 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        orr r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        orr r4, r4, r5, rrx
 # CHECK-NEXT:  1      1     0.50                        orrseq  r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orrne r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        orrseq  r4, r5, r6, lsl #5
-# CHECK-NEXT:  1      2     1.00                        orrlo r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        orrlo r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        orrshi  r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        orrhs r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        orrseq  r4, r4, r5
-# CHECK-NEXT:  1      2     1.00                        orrne r6, r6, r7, asr r9
-# CHECK-NEXT:  1      2     1.00                        orrslt  r6, r6, r7, ror r9
+# CHECK-NEXT:  1      2     0.50                        orrne r6, r6, r7, asr r9
+# CHECK-NEXT:  1      2     0.50                        orrslt  r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        orrsgt  r4, r4, r5, rrx
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  1      2     1.00                        pkhbt r2, r2, r3
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  1      2     1.00                        pkhtb r2, r2, r3, asr #15

 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsblo r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, ror #5
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r7, r8, asr r9
-# CHECK-NEXT:  1      2     1.00                        rsble r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        rsble r6, r7, r8, ror r9
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r5, r6, rrx
 # CHECK-NEXT:  1      1     0.50                        rsb r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                  U     rsb r4, r4, r5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsbne r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, ror #5
-# CHECK-NEXT:  1      2     1.00                        rsbgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     0.50                        rsbgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        rsb r6, r6, r7, ror r9
 # CHECK-NEXT:  1      2     1.00                        rsb r4, r4, r5, rrx
 # CHECK-NEXT:  1      1     0.50                        rsbs  r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        rsbs  r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        rsc r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        rsc r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        rsc r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                  U     rsc r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsclo r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r5, r6, ror #5
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r7, r8, asr r9
-# CHECK-NEXT:  1      2     1.00                        rscle r6, r7, r8, ror r9
+# CHECK-NEXT:  1      2     0.50                        rscle r6, r7, r8, ror r9
 # CHECK-NEXT:  1      1     0.50                        rsc r5, r5, #61440
 # CHECK-NEXT:  1      1     0.50                  U     rsc r4, r4, r5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, lsl #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rscne r4, r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        rsc r4, r4, r5, ror #5
-# CHECK-NEXT:  1      2     1.00                        rscgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  1      2     0.50                        rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  1      1     0.50                        rrx r0, r1
 # CHECK-NEXT:  1      1     0.50                        rrx sp, pc
 # CHECK-NEXT:  1      1     0.50                        rrx pc, lr
 # CHECK-NEXT:  1      1     0.50                        rrx lr, sp
 # CHECK-NEXT:  1      1     0.50                        rrxs  r0, r1
 # CHECK-NEXT:  1      1     0.50                        rrxs  sp, pc
 # CHECK-NEXT:  1      1     0.50                        rrxs  pc, lr
 # CHECK-NEXT:  1      1     0.50                        rrxs  lr, sp
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd16  r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     sadd16gt  r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     sadd16gt  r1, r2, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     sadd8 r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     sadd8le r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     sadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     sasx  r9, r12, r0
-# CHECK-NEXT:  2      3     1.00    *      *      U     sasxeq  r9, r12, r0
+# CHECK-NEXT:  2      5     1.00    *      *      U     sasxeq  r9, r12, r0
 # CHECK-NEXT:  1      1     0.50                        sbc r4, r5, #61440
 # CHECK-NEXT:  1      1     0.50                        sbc r7, r8, #-2147483638
 # CHECK-NEXT:  1      1     0.50                        sbc r7, r8, #40, #2
 # CHECK-NEXT:  1      1     0.50                        sbc r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsl #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, lsr #5
 # CHECK-NEXT:  1      2     1.00                        sbc r4, r5, r6, asr #5

 # CHECK-NEXT:  1      2     1.00                        sbc r4, r4, r5, ror #5
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        sbc r6, r6, r7, ror r9
 # CHECK-NEXT:  1      1     0.50                  U     sbfx  r4, r5, #16, #1
 # CHECK-NEXT:  1      1     0.50                  U     sbfxgt  r4, r5, #16, #16
 # CHECK-NEXT:  1      1     0.50    *                   sel r9, r2, r1
-# CHECK-NEXT:  1      1     0.50    *                   selne r9, r2, r1
+# CHECK-NEXT:  1      2     0.50    *                   selne r9, r2, r1
 # CHECK-NEXT:  0      0     0.00                  U     setend  be
 # CHECK-NEXT:  0      0     0.00                  U     setend  le
 # CHECK-NEXT:  0      0     0.00    *      *      U     sev
 # CHECK-NEXT:  0      0     0.00    *      *      U     seveq
 # CHECK-NEXT:  1      2     1.00                        shadd16 r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd16gt r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd8  r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        shadd8gt  r4, r8, r2

 # CHECK-NEXT:  0      0     0.00                  U     srsia sp!, #5
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, lsl #31
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, asr #32
 # CHECK-NEXT:  1      2     1.00                        ssat  r8, #1, r10, asr #1
 # CHECK-NEXT:  1      2     1.00                        ssat16  r2, #1, r7
 # CHECK-NEXT:  1      2     1.00                        ssat16  r3, #16, r5
 # CHECK-NEXT:  2      3     1.00    *      *      U     ssax  r2, r3, r4
-# CHECK-NEXT:  2      3     1.00    *      *      U     ssaxlt  r2, r3, r4
+# CHECK-NEXT:  2      5     1.00    *      *      U     ssaxlt  r2, r3, r4
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub16  r1, r0, r6
-# CHECK-NEXT:  2      2     1.00    *      *      U     ssub16ne  r5, r3, r2
+# CHECK-NEXT:  2      4     1.00    *      *      U     ssub16ne  r5, r3, r2
 # CHECK-NEXT:  2      2     1.00    *      *      U     ssub8 r9, r2, r4
-# CHECK-NEXT:  2      2     1.00    *      *      U     ssub8eq r5, r1, r2
+# CHECK-NEXT:  2      4     1.00    *      *      U     ssub8eq r5, r1, r2
 # CHECK-NEXT:  1      2     1.00           *            stm r2, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stm r3, {r1, r3, r4, r5, r6, lr}
 # CHECK-NEXT:  1      2     1.00           *            stmib r4, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stmda r5, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  1      2     1.00           *            stmdb r6, {r1, r3, r4, r5, r6, r8}
 # CHECK-NEXT:  1      2     1.00           *            stmdb sp, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  2      2     1.00           *            stm r8!, {r1, r3, r4, r5, r6, sp}
 # CHECK-NEXT:  2      2     1.00           *            stmib r9!, {r1, r3, r4, r5, r6, sp}

 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, lsr #5
 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, asr #5
 # CHECK-NEXT:  1      2     1.00                        tst r4, r5, ror #5
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, lsl r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, lsr r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, asr r9
 # CHECK-NEXT:  1      2     1.00                        tst r6, r7, ror r9
 # CHECK-NEXT:  2      2     1.00    *      *      U     uadd16  r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     uadd16gt  r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     uadd16gt  r1, r2, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     uadd8 r1, r2, r3
-# CHECK-NEXT:  2      2     1.00    *      *      U     uadd8le r1, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     uadd8le r1, r2, r3
 # CHECK-NEXT:  2      3     1.00    *      *      U     uasx  r9, r12, r0
-# CHECK-NEXT:  2      3     1.00    *      *      U     uasxeq  r9, r12, r0
+# CHECK-NEXT:  2      5     1.00    *      *      U     uasxeq  r9, r12, r0
 # CHECK-NEXT:  1      1     0.50                  U     ubfx  r4, r5, #16, #1
 # CHECK-NEXT:  1      1     0.50                  U     ubfxgt  r4, r5, #16, #16
 # CHECK-NEXT:  1      2     1.00                        uhadd16 r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd16gt r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd8  r4, r8, r2
 # CHECK-NEXT:  1      2     1.00                        uhadd8gt  r4, r8, r2
 # CHECK-NEXT:  2      3     1.00                        uhasx r4, r8, r2
 # CHECK-NEXT:  2      3     1.00                        uhasxgt r4, r8, r2

 # CHECK-NEXT:  1      2     1.00                        usat  r8, #1, r10
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #4, r10
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #5, r10, lsl #31
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #31, r10, asr #32
 # CHECK-NEXT:  1      2     1.00                        usat  r8, #16, r10, asr #1
 # CHECK-NEXT:  1      2     1.00                        usat16  r2, #2, r7
 # CHECK-NEXT:  1      2     1.00                        usat16  r3, #15, r5
 # CHECK-NEXT:  2      3     1.00    *      *      U     usax  r2, r3, r4
-# CHECK-NEXT:  2      3     1.00    *      *      U     usaxne  r2, r3, r4
+# CHECK-NEXT:  2      5     1.00    *      *      U     usaxne  r2, r3, r4
 # CHECK-NEXT:  2      2     1.00    *      *      U     usub16  r4, r2, r7
-# CHECK-NEXT:  2      2     1.00    *      *      U     usub16hi  r1, r1, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     usub16hi  r1, r1, r3
 # CHECK-NEXT:  2      2     1.00    *      *      U     usub8 r1, r8, r5
-# CHECK-NEXT:  2      2     1.00    *      *      U     usub8le r9, r2, r3
+# CHECK-NEXT:  2      4     1.00    *      *      U     usub8le r9, r2, r3
 # CHECK-NEXT:  1      2     1.00                        uxtab r2, r3, r4
 # CHECK-NEXT:  1      2     1.00                        uxtab r4, r5, r6
 # CHECK-NEXT:  1      2     1.00                        uxtablt r6, r2, r9, ror #8
 # CHECK-NEXT:  1      2     1.00                        uxtab r5, r1, r4, ror #16
 # CHECK-NEXT:  1      2     1.00                        uxtab r7, r8, r3, ror #24
 # CHECK-NEXT:  1      4     1.00                        uxtab16ge r0, r1, r4
 # CHECK-NEXT:  1      4     1.00                        uxtab16 r6, r2, r7
 # CHECK-NEXT:  1      4     1.00                        uxtab16 r3, r5, r8, ror #8

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT: 8.00   158.50 158.50 171.00 497.00 12.00   -      -
+# CHECK-NEXT: 8.00   162.00 162.00 171.00 490.00 12.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #15
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #240
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #3840
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     adc r1, r2, #983040

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orr r4, r4, r5, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq  r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrne r4, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrseq  r4, r5, r6, lsl #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrlo r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrlo r6, r7, r8, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrshi  r4, r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrhs r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrseq  r4, r4, r5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrne r6, r6, r7, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrslt  r6, r6, r7, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrne r6, r6, r7, asr r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     orrslt  r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     orrsgt  r4, r4, r5, rrx
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3, lsl #15
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhbt r2, r2, r3
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #31
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     pkhtb r2, r2, r3, asr #15

 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsblo r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r7, r8, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsble r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsble r6, r7, r8, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r5, r6, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsb r4, r4, r5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbne r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, ror #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsbgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r6, r6, r7, ror r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsb r4, r4, r5, rrx
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs  r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsbs  r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r7, r8, #-2147483638
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r7, r8, #40, #2
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r5, r6
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsclo r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r5, r6, ror #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r7, r8, asr r9
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscle r6, r7, r8, ror r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rscle r6, r7, r8, ror r9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r5, r5, #61440
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rsc r4, r4, r5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, lsl #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscne r4, r4, r5, lsr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, asr #5
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r4, r4, r5, ror #5
-# CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rscgt r6, r6, r7, lsl r9
+# CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rscgt r6, r6, r7, lsl r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, lsr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, asr r9
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -     rsc r6, r6, r7, ror r9
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx r0, r1
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx sp, pc
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx pc, lr
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrx lr, sp
 # CHECK-NEXT:  -     0.50   0.50    -      -      -      -      -     rrxs  r0, r1