[WebAssembly] Emulate v128.const efficiently

[tlively]

Summary

v128.const was recently implemented in V8, but until it rolls into Chrome
stable, we can't enable it in the WebAssembly backend without breaking origin
trial users. So far we have been lowering build_vectors that would otherwise
have been lowered to v128.const to splats followed by sequences of replace_lane
instructions to initialize each lane individually. That produces large and
inefficient code, so this patch introduces new logic to lower integer vector
constants to a single i64x2.splat where possible, with at most a single
i64x2.replace_lane following it if necessary.

Adapted from a patch authored by @omnisip.

[aheejin]

Nice idea! I believe this approach will be better in most cases; the only possible downside I can think of is something like this. In our test case there's this test:

define <4 x i32> @splat_common_const_i32x4() {
  ret <4 x i32> <i32 undef, i32 3, i32 3, i32 1>
}

This is compiled to this currently:

i32.const	$push0=, 3
i32x4.splat	$push1=, $pop0
i32.const	$push2=, 1
i32x4.replace_lane	$push3=, $pop1, 3, $pop2

After this patch this becomes:

i64.const	$push0=, 12884901888
i64x2.splat	$push1=, $pop0
i64.const	$push2=, 4294967299
i64x2.replace_lane	$push3=, $pop1, 1, $pop2

The number of instructions is the same, but because we are now using i64.const rather than i32.const, can this increase the code size?

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1586

It'd be easier to read to have a little more comments here on what we are trying to do and why it is always better than the simpler splatting-and-replacing option which already existed. Something like this. (Also it might be a good idea to link this issue in the CL/commit description for full reference).

1601

What does getLimitedValue do and why is it necessary?

[tlively]

In D88591#2306093, @aheejin wrote:

The number of instructions is the same, but because we are now using i64.const rather than i32.const, can this increase the code size?

Yes, you're right code size can increase. However, once we enable v128.const by default, the code size will increase even more. We've generally been trying to optimize SIMD code to minimize the number of instructions (and more generally maximize performance) rather than minimizing code size, so I don't think this is a problem.

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1586

Sounds good. I will elaborate here.

1601

It gets the constant value, capping it so that it fits in a uint64_t. It's similar to getZExtValue, but doesn't assert if the value happens to be too large to fit in a uint64_t for some reason.

[tlively]

• Elaborate commment

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1601

Given that our biggest lane is 64 bits, do we need this then? (I'm not against using this as a safe measure or anything; I'm just trying to understand what this function does)

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1601

No, I think we could have just as well used getZExtVal, but I don't think that's any clearer.

[hubert.reinterpretcast]

This patch appears to be the likely cause of big endian hosts failing with a timeout:

• http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/35450
• http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/54746

This is what shows on our AIX-hosted bot:

buildbot-user 19006934  7538476 120 07:48:02      - 68:54 /buildbot/buildbot-user/buildbot-worker/worker/LLVM-Master-AIX-Release-powerpc64le-gnu-linux/build/bin/llc -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128
buildbot-user 30541264  7538476   0 07:48:02      -  0:00 /buildbot/buildbot-user/buildbot-worker/worker/LLVM-Master-AIX-Release-powerpc64le-gnu-linux/build/bin/FileCheck /buildbot/buildbot-user/buildbot-worker/worker/LLVM-Master-AIX-Release-powerpc64le-gnu-linux/llvm/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll --check-prefixes=CHECK,SIMD-VM
buildbot-user  7538476 17762386   0 07:48:01      -  0:00 /bin/bash /buildbot/buildbot-user/buildbot-worker/worker/LLVM-Master-AIX-Release-powerpc64le-gnu-linux/build/test/CodeGen/WebAssembly/Output/simd-build-vector.ll.script

[hubert.reinterpretcast]

@uweigand, fyi re: clang-s390x-linux bot: https://reviews.llvm.org/D88591#2308590.

[max-kudr]

Please address buildbot failure: http://lab.llvm.org:8011/builders/lldb-x64-windows-ninja/builds/19311/steps/build/logs/stdio

E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1589): error C2100: illegal indirection
E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1590): error C2100: illegal indirection

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1594

More comments or assertions about the expected range for ByteStep could be helpful.

1595

More comments of assertions about the expected number of loop iterations and the relationship to ByteStep could be helpful.

[stefanp]

I can confirm that this changeset is causing the timeout on the clang-ppc64be-linux buildbot.
The following was run on a Big Endian Power PC machine.

Without the change:

$ ./bin/llvm-lit test/CodeGen/WebAssembly/simd-build-vector.ll
-- Testing: 1 tests, 1 workers --
PASS: LLVM :: CodeGen/WebAssembly/simd-build-vector.ll (1 of 1)Testing Time: 0.31s
  Passed: 1

With the change (I killed it after 200 seconds)

$ ./bin/llvm-lit test/CodeGen/WebAssembly/simd-build-vector.ll
-- Testing: 1 tests, 1 workers --
^C  interrupted by user, skipping remaining testsTesting Time: 201.41s
  Skipped: 1

[tlively]

@stefanp Yikes, I must have messed up the endianness handling here. Will revert and investigate.

[efriedma]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

I think this byte_swap isn't doing the right thing; it's in the wrong width.

There are a couple of reasonable ways to write this:

1. Construct an std::array<uint8_t, 16>/std::array<ulittle16_t, 8>/std::array<ulittle32_t, 4>, and memcpy from it to an std::array<ulittle64_t, 2>.
2. Don't type-pun at all; something like:

for (int i = 0; i < NumElements; ++i)
  Result[i / (NumElements / 2)] |= Elements[i] << ElementWidth * (i  % (NumElements / 2);

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

When I wrote this, I checked the implementation of byte swap. It's a template that derives the byte_swap from the value type. In this case, getLimitedValue returns u64. It should be right. It makes me wonder since webassembly is guaranteed to be little endian if a conversion occurs before this happens.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1595

@tlively @hubert.reinterpretcast the byte step exists to simplify the branching logic that would exist if we had to do masking for each integer type. It takes advantage of little endian to always capture the least significant bits relevant to the typed integer in question.

[dweber]

This comment was removed by dweber.

[dweber]

In D88591#2308659, @max-kudr wrote:

Please address buildbot failure: http://lab.llvm.org:8011/builders/lldb-x64-windows-ninja/builds/19311/steps/build/logs/stdio

E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1589): error C2100: illegal indirection
E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1590): error C2100: illegal indirection

This issue is caused by VS not accepting the initializer list on the machine running the build. It appears to be broken in VS up through v19.24. But starts working with v19.25. This can be resolved by using the {{0,0}} initializer syntax with std::array.

[tlively]

In D88591#2309812, @dweber wrote:

In D88591#2308659, @max-kudr wrote:

Please address buildbot failure: http://lab.llvm.org:8011/builders/lldb-x64-windows-ninja/builds/19311/steps/build/logs/stdio

E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1589): error C2100: illegal indirection
E:\build_slave\lldb-x64-windows-ninja\llvm-project\llvm\lib\Target\WebAssembly\WebAssemblyISelLowering.cpp(1590): error C2100: illegal indirection

This issue is caused by VS not accepting the initializer list on the machine running the build. It appears to be broken in VS up through v19.24. But starts working with v19.25. This can be resolved by using the {{0,0}} initializer syntax with std::array.

Thanks for looking into this!

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

Splatted represents a different value on big endian systems at this point.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

@hubert.reinterpretcast If you remove the byte_swap function all together, do you still get the same issue?

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

I mean, from code inspection, without needing to assume anything weird on the original byte_swap.

Using half the width as an example (4 elements of 16 bits):
Values:

0x1234 0x5678 0x1234 0x5678

Resulting bytes in storage:

0x34 0x12 0x78 0x56 // 0x34 0x12 0x78 0x56
0xff 0xff 0xff 0xff // 0xff 0xff 0xff 0xff

Request constant from value with bytes:

0x34 0x12 0x78 0x56

i.e., on little endian systems, request constant with value:

0x56781234

or, on big endian systems, request constant with value:

0x34127856

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1634

Similarly for I64s[1] here.

[efriedma]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

Oh, you're extending to u64, putting a little-endian u64 into memory, and copying the first N bits. That's effectively the same as putting a little-endian uN into memory. But I guess that leaves you with a problem at the other end: the elements of I64s are never swapped back from little-endian to native endianness.

In any case, the interaction between the endianness and the pointer manipulation is hard to follow; I'd suggest rewriting it even if the current implementation were correct.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

@hubert.reinterpretcast the reason I ask is because webassembly assumes little endian. On big endian machines, the constant could have been converted before we do anything here -- especially since the developer using emscripten is taught there is no other byte order but little endian. If that's the case, the byte swap could be creating the problem.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

(the above byte_swap on a little endian machine will always produce the original parameter without fail).

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

They're not supposed to be converted back to native endianness unless there's something I misunderstand about the implementation. If two byte swaps are required, I'm pretty sure none is required.

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

I'm working on a rewrite that uses @efriedma's suggestion to not use type punning above, by the way.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

You could just change ByteStep to IntegerWidthInBytes if it's really a clarification change.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

Two byte swaps would definitely be safe though.

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

The first byte_swap is necessary. The following makes the case pass:

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 8474e50..5a94041 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1586,8 +1586,10 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
     // we can construct the 128-bit constant from a pair of i64s using a splat
     // followed by at most one i64x2.replace_lane. Also keep track of the lanes
     // that actually matter so we can avoid the replace_lane in more cases.
-    std::array<uint64_t, 2> I64s({0, 0});
-    std::array<uint64_t, 2> ConstLaneMasks({0, 0});
+    using llvm::support::ulittle64_t;
+    const ulittle64_t ulittle64_zero(0);
+    std::array<ulittle64_t, 2> I64s({ulittle64_zero, ulittle64_zero});
+    std::array<ulittle64_t, 2> ConstLaneMasks({ulittle64_zero, ulittle64_zero});
     uint8_t *I64Bytes = reinterpret_cast<uint8_t *>(I64s.data());
     uint8_t *MaskBytes = reinterpret_cast<uint8_t *>(ConstLaneMasks.data());
     unsigned I = 0;

[hubert.reinterpretcast]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1603

I'm working on a rewrite that uses @efriedma's suggestion to not use type punning above, by the way.

I am guessing that a memcpy into a ulittle64_t would be preferred for getting the desired 64-bit value that would produce the right memory image on the target machine.

[dweber]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1631

Excellent. If you fix the std:;array initializer syntax to be {{0,0}} instead of ({0,0}) it'll compile and work on VS too.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/WasmEHFuncInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsWebAssembly.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Endian.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-lower"
 
 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
if (NumSwizzleLanes >= NumSplatLanes &&
     Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc,
                          SwizzleIndices);
     auto Swizzled = std::make_pair(SwizzleSrc, SwizzleIndices);
     IsLaneConstructed = [&, Swizzled](size_t I, const SDValue &Lane) {
       return Swizzled == GetSwizzleSrcs(I, Lane);
     };
   } else if (NumConstantLanes >= NumSplatLanes &&
              Subtarget->hasUnimplementedSIMD128()) {
+    // If we support v128.const, emit it directly
     SmallVector<SDValue, 16> ConstLanes;
     for (const SDValue &Lane : Op->op_values()) {
       if (IsConstant(Lane)) {
         ConstLanes.push_back(Lane);
       } else if (LaneT.isFloatingPoint()) {
         ConstLanes.push_back(DAG.getConstantFP(0, DL, LaneT));
       } else {
         ConstLanes.push_back(DAG.getConstant(0, DL, LaneT));
       }
     }
     Result = DAG.getBuildVector(VecT, DL, ConstLanes);
-    IsLaneConstructed = [&](size_t _, const SDValue &Lane) {
+    IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
       return IsConstant(Lane);
     };
+  } else if (NumConstantLanes >= NumSplatLanes && VecT.isInteger()) {
+    // Otherwise, if this is an integer vector, pack the lane values together so
+    // we can construct the 128-bit constant from a pair of i64s using a splat
+    // followed by at most one i64x2.replace_lane. Also keep track of the lanes
+    // that actually matter so we can avoid the replace_lane in more cases.
+    std::array<uint64_t, 2> I64s({0, 0});
+    std::array<uint64_t, 2> ConstLaneMasks({0, 0});
+    uint8_t *I64Bytes = reinterpret_cast<uint8_t *>(I64s.data());
+    uint8_t *MaskBytes = reinterpret_cast<uint8_t *>(ConstLaneMasks.data());
+    unsigned I = 0;
+    size_t ByteStep = VecT.getScalarSizeInBits() / 8;
+    for (const SDValue &Lane : Op->op_values()) {
+      if (IsConstant(Lane)) {
+        using llvm::support::little;
+        using llvm::support::endian::byte_swap;
+        // The endianness of the compiler matters here. We want to enforce
+        // little endianness so that the bytes of a smaller integer type will
+        // occur first in the uint64_t.
+        auto *Const = cast<ConstantSDNode>(Lane.getNode());
+        uint64_t Val = byte_swap(Const->getLimitedValue(), little);
+        uint8_t *ValPtr = reinterpret_cast<uint8_t *>(&Val);
+        std::copy(ValPtr, ValPtr + ByteStep, I64Bytes + I * ByteStep);
+        uint64_t Mask = uint64_t(-1LL);
+        uint8_t *MaskPtr = reinterpret_cast<uint8_t *>(&Mask);
+        std::copy(MaskPtr, MaskPtr + ByteStep, MaskBytes + I * ByteStep);
+      }
+      ++I;
+    }
+    // Check whether all constant lanes in the second half of the vector are
+    // equivalent in the first half or vice versa to determine whether splatting
+    // either side will be sufficient to materialize the constant. As a special
+    // case, if the first and second halves have no constant lanes in common, we
+    // can just combine them.
+    bool FirstHalfSufficient = (I64s[0] & ConstLaneMasks[1]) == I64s[1];
+    bool SecondHalfSufficient = (I64s[1] & ConstLaneMasks[0]) == I64s[0];
+    bool CombinedSufficient = (ConstLaneMasks[0] & ConstLaneMasks[1]) == 0;
+
+    uint64_t Splatted;
+    if (SecondHalfSufficient) {
+      Splatted = I64s[1];
+    } else if (CombinedSufficient) {
+      Splatted = I64s[0] | I64s[1];
+    } else {
+      Splatted = I64s[0];
+    }
+
+    Result = DAG.getSplatBuildVector(MVT::v2i64, DL,
+                                     DAG.getConstant(Splatted, DL, MVT::i64));
+    if (!FirstHalfSufficient && !SecondHalfSufficient && !CombinedSufficient) {
+      Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v2i64, Result,
+                           DAG.getConstant(I64s[1], DL, MVT::i64),
+                           DAG.getConstant(1, DL, MVT::i32));
     }
-  if (!Result) {
+    Result = DAG.getBitcast(VecT, Result);
+    IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
+      return IsConstant(Lane);
+    };
+  } else {
     // Use a splat, but possibly a load_splat
     LoadSDNode *SplattedLoad;
     if ((SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
         SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) {
       Result = DAG.getMemIntrinsicNode(
           WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList(VecT),
           {SplattedLoad->getChain(), SplattedLoad->getBasePtr(),
            SplattedLoad->getOffset()},
           SplattedLoad->getMemoryVT(), SplattedLoad->getMemOperand());
     } else {
       Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
     }
-    IsLaneConstructed = [&](size_t _, const SDValue &Lane) {
+    IsLaneConstructed = [&SplatValue](size_t _, const SDValue &Lane) {
       return Lane == SplatValue;
     };
   }
 
+  assert(Result);
+  assert(IsLaneConstructed);
+
   // Add replace_lane instructions for any unhandled values
   for (size_t I = 0; I < Lanes; ++I) {
     const SDValue &Lane = Op->getOperand(I);
     if (!Lane.isUndef() && !IsLaneConstructed(I, Lane))
       Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
                            DAG.getConstant(I, DL, MVT::i32));
   }
 

llvm/test/CodeGen/WebAssembly/simd-build-vector.ll

 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes=CHECK,UNIMP
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes=CHECK,SIMD-VM
 
 ; Test that the logic to choose between v128.const vector
 ; initialization and splat vector initialization and to optimize the
 ; choice of splat value works correctly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
+; CHECK-LABEL:  emulated_const_trivial_splat:
+; CHECK-NEXT:   .functype       emulated_const_trivial_splat () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: return  $pop1
+; UNIMP: v128.const
+define <4 x i32> @emulated_const_trivial_splat() {
+  ret <4 x i32> <i32 1, i32 2, i32 1, i32 2>
+}
+
+; CHECK-LABEL:  emulated_const_first_sufficient:
+; CHECK-NEXT:   .functype       emulated_const_first_sufficient () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: return  $pop1
+; UNIMP: v128.const
+define <4 x i32> @emulated_const_first_sufficient() {
+  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 2>
+}
+
+; CHECK-LABEL:  emulated_const_second_sufficient:
+; CHECK-NEXT:   .functype       emulated_const_second_sufficient () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: return  $pop1
+; UNIMP: v128.const
+define <4 x i32> @emulated_const_second_sufficient() {
+  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 2>
+}
+
+; CHECK-LABEL:  emulated_const_combined_sufficient:
+; CHECK-NEXT:   .functype       emulated_const_combined_sufficient () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: return  $pop1
+; UNIMP: v128.const
+define <4 x i32> @emulated_const_combined_sufficient() {
+  ret <4 x i32> <i32 1, i32 undef, i32 undef, i32 2>
+}
+
+; CHECK-LABEL:  emulated_const_either_sufficient:
+; CHECK-NEXT:   .functype       emulated_const_either_sufficient () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 1
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: return  $pop1
+; UNIMP: v128.const
+define <4 x i32> @emulated_const_either_sufficient() {
+  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 undef>
+}
+
+; CHECK-LABEL: emulated_const_neither_sufficient:
+; CHECK-NEXT:   .functype       emulated_const_neither_sufficient () -> (v128)
+; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
+; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
+; SIMD-VM-NEXT: i64.const       $push2=, 17179869184
+; SIMD-VM-NEXT: i64x2.replace_lane      $push3=, $pop1, 1, $pop2
+; SIMD-VM-NEXT: return  $pop3
+define <4 x i32> @emulated_const_neither_sufficient() {
+  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 4>
+}
+
 ; CHECK-LABEL: same_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_i16x8 (i32) -> (v128)
 ; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
 ; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
 ; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i16x8.splat
+; SIMD-VM: i64x2.splat
 define <8 x i16> @same_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>,
     i16 %x,
     i32 5
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: different_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_i16x8 (i32) -> (v128)
 ; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
 ; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
 ; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i16x8.splat
+; SIMD-VM: i64x2.splat
 define <8 x i16> @different_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 1, i16 -2, i16 3, i16 -4, i16 5, i16 -6, i16 7, i16 -8>,
     i16 %x,
     i32 5
   ret <8 x i16> %v
 }
 
%v = insertelement
     i32 2
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: splat_common_const_i32x4:
 ; CHECK-NEXT:  .functype       splat_common_const_i32x4 () -> (v128)
 ; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0, 3, 3, 1
 ; UNIMP-NEXT:  return          $pop[[L0]]
-; SIMD-VM: i32x4.splat
+; SIMD-VM: i64x2.splat
 define <4 x i32> @splat_common_const_i32x4() {
   ret <4 x i32> <i32 undef, i32 3, i32 3, i32 1>
 }
 
 ; CHECK-LABEL: splat_common_arg_i16x8:
 ; CHECK-NEXT:  .functype       splat_common_arg_i16x8 (i32, i32, i32) -> (v128)
 ; CHECK-NEXT:  i16x8.splat     $push[[L0:[0-9]+]]=, $2
 ; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 0, $1

 
 ; CHECK-LABEL: mashup_const_i8x16:
 ; CHECK-NEXT:  .functype       mashup_const_i8x16 (v128, v128, i32) -> (v128)
 ; UNIMP:       v128.const      $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0
 ; UNIMP:       i8x16.replace_lane
 ; UNIMP:       i8x16.replace_lane
 ; UNIMP:       i8x16.replace_lane
 ; UNIMP:       return
-; SIMD-VM: i8x16.splat
+; SIMD-VM: i64x2.splat
 define <16 x i8> @mashup_const_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
   ; swizzle 0
   %m0 = extractelement <16 x i8> %mask, i32 0
   %s0 = extractelement <16 x i8> %src, i8 %m0
   %v0 = insertelement <16 x i8> undef, i8 %s0, i32 0
   ; splat 3
   %v1 = insertelement <16 x i8> %v0, i8 %splatted, i32 3
   ; splat 12