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Differential D88186

[AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base.
ClosedPublic

Authored by efriedma on Sep 23 2020, 3:15 PM.

Details

Reviewers
sdesmalen
huihuiz
paulwalker-arm
awarzynski
kmclaughlin
Commits
rG4600e2105142: [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base.
Summary

The intrinsics don't have any pointer arguments, so "argmemonly" makes optimizations think they don't write to memory at all.

Diff Detail

Event Timeline

efriedma created this revision.Sep 23 2020, 3:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 23 2020, 3:15 PM
Herald added subscribers: psnobl, asbirlea, kristof.beyls, tschuett. · View Herald Transcript
efriedma requested review of this revision.Sep 23 2020, 3:15 PM
efriedma updated this revision to Diff 293875.Sep 23 2020, 3:25 PM

Fix test

Harbormaster completed remote builds in B72727: Diff 293875.Sep 23 2020, 4:02 PM
Harbormaster completed remote builds in B72725: Diff 293871.
paulwalker-arm accepted this revision.Sep 24 2020, 4:10 AM
This revision is now accepted and ready to land.Sep 24 2020, 4:10 AM
Closed by commit rG4600e2105142: [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base. (authored by efriedma). · Explain WhySep 25 2020, 4:01 PM
This revision was automatically updated to reflect the committed changes.
efriedma added a commit: rG4600e2105142: [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base..

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
4 lines
test/
Transforms/
LICM/
AArch64/
49 lines

Diff 293875

llvm/include/llvm/IR/IntrinsicsAArch64.td

Show First 20 Lines • Show All 1,294 Lines • ▼ Show 20 Lines
class AdvSIMD_GatherLoad_VS_Intrinsic class AdvSIMD_GatherLoad_VS_Intrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[ [
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyvector_ty, llvm_anyvector_ty,
llvm_i64_ty llvm_i64_ty
], ],
[IntrReadMem, IntrArgMemOnly]>; [IntrReadMem]>;
class AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic class AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[ [
llvm_anyvector_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>, LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty> LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
Show All 12 Lines
class AdvSIMD_ScatterStore_VS_Intrinsic class AdvSIMD_ScatterStore_VS_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[ [
llvm_anyvector_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyvector_ty, llvm_i64_ty llvm_anyvector_ty, llvm_i64_ty
], ],
[IntrWriteMem, IntrArgMemOnly]>; [IntrWriteMem]>;
class SVE_gather_prf_SV class SVE_gather_prf_SV
: Intrinsic<[], : Intrinsic<[],
[ [
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate
llvm_ptr_ty, // Base address llvm_ptr_ty, // Base address
llvm_anyvector_ty, // Offsets llvm_anyvector_ty, // Offsets
▲ Show 20 Lines • Show All 1,062 Lines • Show Last 20 Lines

llvm/test/Transforms/LICM/AArch64/sve-load-hoist.ll

Show All 20 Linesfor.body:
%inc = add nuw nsw i32 %i, 1 %inc = add nuw nsw i32 %i, 1
%cmp = icmp ult i32 %inc, %n %cmp = icmp ult i32 %inc, %n
br i1 %cmp, label %for.body, label %for.end br i1 %cmp, label %for.body, label %for.end
for.end: for.end:
ret void ret void
} }
define void @no_hoist_gather(<vscale x 2 x i32>* %out_ptr, <vscale x 2 x i32>* %in_ptr, <vscale x 2 x i64> %ptr_vec, i64 %n, <vscale x 2 x i1> %pred) {
; CHECK-LABEL: @no_hoist_gather(
; CHECK: entry:
; CHECK-NOT: llvm.aarch64.sve.ld1.gather.scalar.offset
; CHECK: for.body:
; CHECK: llvm.aarch64.sve.ld1.gather.scalar.offset
entry:
br label %for.body
for.body:
%i = phi i64 [0, %entry], [%inc, %for.body]
%gather = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64> %ptr_vec, i64 0)
%in_ptr_gep = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %in_ptr, i64 %i
%in_ptr_load = load <vscale x 2 x i32>, <vscale x 2 x i32>* %in_ptr_gep, align 8
%sum = add <vscale x 2 x i32> %gather, %in_ptr_load
%out_ptr_gep = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %out_ptr, i64 %i
store <vscale x 2 x i32> %sum, <vscale x 2 x i32>* %out_ptr_gep, align 8
%inc = add nuw nsw i64 %i, 1
%cmp = icmp ult i64 %inc, %n
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
define void @no_hoist_scatter(<vscale x 2 x i32>* %out_ptr, <vscale x 2 x i32>* %in_ptr, <vscale x 2 x i64> %ptr_vec, i64 %n, <vscale x 2 x i1> %pred) {
; CHECK-LABEL: @no_hoist_scatter(
; CHECK: entry:
; CHECK-NOT: load
; CHECK: for.body:
; CHECK: load
entry:
br label %for.body
for.body:
%i = phi i64 [0, %entry], [%inc, %for.body]
%in_ptr_load = load <vscale x 2 x i32>, <vscale x 2 x i32>* %in_ptr, align 8
call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %in_ptr_load, <vscale x 2 x i1> %pred, <vscale x 2 x i64> %ptr_vec, i64 %i)
%inc = add nuw nsw i64 %i, 1
%cmp = icmp ult i64 %inc, %n
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
declare {}* @llvm.invariant.start.p0i8(i64, i8* nocapture) nounwind readonly declare {}* @llvm.invariant.start.p0i8(i64, i8* nocapture) nounwind readonly
declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)