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Differential D88145

[ARM] Added more patterns to generate SSAT/USAT with shift
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Authored by MeeraN on Sep 23 2020, 5:35 AM.

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Reviewers
dmgreen
SjoerdMeijer
samparker
pbarrio
fhahn
Commits
rG675431b98787: [ARM] Added more patterns to generate SSAT/USAT with shift
Summary

Added patterns to generate an SSAT or USAT with shift for
SSAT/USAT instructions that are matched from IR patterns.

Diff Detail

Event Timeline

MeeraN created this revision.Sep 23 2020, 5:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 23 2020, 5:35 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
MeeraN requested review of this revision.Sep 23 2020, 5:35 AM
Harbormaster completed remote builds in B72646: Diff 293703.Sep 23 2020, 5:35 AM
dmgreen added inline comments.Sep 23 2020, 10:14 AM
llvm/lib/Target/ARM/ARMInstrInfo.td
4101

Can you rename ARMssatnoshift to just ARMssat (or something similar). The "noshift" doesn't really need to be part of the node name.

MeeraN updated this revision to Diff 294059.Sep 24 2020, 7:52 AM

Renamed ARMssatnoshift and ARMusatnoshift to ARMssat and ARMusat

dmgreen accepted this revision.Sep 25 2020, 2:06 AM

LGTM. Thanks

This revision is now accepted and ready to land.Sep 25 2020, 2:06 AM
Closed by commit rG675431b98787: [ARM] Added more patterns to generate SSAT/USAT with shift (authored by MeeraN). · Explain WhySep 28 2020, 7:51 AM
This revision was automatically updated to reflect the committed changes.
MeeraN marked an inline comment as done.
MeeraN added a commit: rG675431b98787: [ARM] Added more patterns to generate SSAT/USAT with shift.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
ARMInstrInfo.td
ARMInstrInfo.td
8 lines
ARMInstrThumb2.td
ARMInstrThumb2.td
9 lines
test/
CodeGen/
ARM/
ssat-with-shift.ll
ssat-with-shift.ll
28 lines
usat-with-shift.ll
usat-with-shift.ll
28 lines
Thumb2/
mve-satmul-loops.ll
mve-satmul-loops.ll
21 lines

Diff 293703

llvm/lib/Target/ARM/ARMInstrInfo.td

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def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos), def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
(SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
(SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : ARMPat<(ARMssatnoshift (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
dmgreenUnsubmitted
Done
ReplyInline Actions

Can you rename ARMssatnoshift to just ARMssat (or something similar). The "noshift" doesn't really need to be part of the node name.

dmgreen: Can you rename ARMssatnoshift to just ARMssat (or something similar). The "noshift" doesn't…
(SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
def : ARMPat<(ARMssatnoshift (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
def : ARMPat<(ARMusatnoshift (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
def : ARMPat<(ARMusatnoshift (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Bitwise Instructions. // Bitwise Instructions.
// //
defm AND : AsI1_bin_irs<0b0000, "and", defm AND : AsI1_bin_irs<0b0000, "and",
IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;
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llvm/lib/Target/ARM/ARMInstrThumb2.td

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def : T2Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos), def : T2Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
(t2SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; (t2SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : T2Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), def : T2Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
(t2SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; (t2SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
(t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : T2Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), def : T2Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
(t2USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; (t2USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : T2Pat<(ARMssatnoshift (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
(t2SSAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : T2Pat<(ARMssatnoshift (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(t2SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
def : T2Pat<(ARMusatnoshift (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
(t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : T2Pat<(ARMusatnoshift (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(t2USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Shift and rotate Instructions. // Shift and rotate Instructions.
// //
defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>; defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>; defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>; defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
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llvm/test/CodeGen/ARM/ssat-with-shift.ll

Show All 18 Lines
; CHECK-NEXT: ssat r0, #8, r0, asr #7 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shr = ashr i32 %num, 7 %shr = ashr i32 %num, 7
%0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8) %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)
ret i32 %0 ret i32 %0
} }
define arm_aapcs_vfpcc i32 @ssat_lsl_32bit(i32 %num){
; CHECK-LABEL: ssat_lsl_32bit:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #16, r0, lsl #15
; CHECK-NEXT: bx lr
entry:
%shl = shl nsw i32 %num, 15
%0 = icmp sgt i32 %shl, -32768
%1 = select i1 %0, i32 %shl, i32 -32768
%2 = icmp slt i32 %1, 32767
%3 = select i1 %2, i32 %1, i32 32767
ret i32 %3
}
define arm_aapcs_vfpcc i32 @ssat_asr_32bit(i32 %num){
; CHECK-LABEL: ssat_asr_32bit:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ssat r0, #16, r0, asr #15
; CHECK-NEXT: bx lr
entry:
%shr = ashr i32 %num, 15
%0 = icmp sgt i32 %shr, -32768
%1 = select i1 %0, i32 %shr, i32 -32768
%2 = icmp slt i32 %1, 32767
%3 = select i1 %2, i32 %1, i32 32767
ret i32 %3
}
declare i32 @llvm.arm.ssat(i32, i32) declare i32 @llvm.arm.ssat(i32, i32)

llvm/test/CodeGen/ARM/usat-with-shift.ll

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; CHECK-NEXT: usat r0, #7, r0, asr #2 ; CHECK-NEXT: usat r0, #7, r0, asr #2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shr = ashr i32 %num, 2 %shr = ashr i32 %num, 2
%0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7) %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
ret i32 %0 ret i32 %0
} }
define arm_aapcs_vfpcc i32 @usat_lsl_32bit(i32 %num){
; CHECK-LABEL: usat_lsl_32bit:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: usat r0, #15, r0, lsl #15
; CHECK-NEXT: bx lr
entry:
%shl = shl nsw i32 %num, 15
%0 = icmp sgt i32 %shl, 0
%1 = select i1 %0, i32 %shl, i32 0
%2 = icmp slt i32 %1, 32767
%3 = select i1 %2, i32 %1, i32 32767
ret i32 %3
}
define arm_aapcs_vfpcc i32 @usat_asr_32bit(i32 %num){
; CHECK-LABEL: usat_asr_32bit:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: usat r0, #15, r0, asr #15
; CHECK-NEXT: bx lr
entry:
%shr = ashr i32 %num, 15
%0 = icmp sgt i32 %shr, 0
%1 = select i1 %0, i32 %shr, i32 0
%2 = icmp slt i32 %1, 32767
%3 = select i1 %2, i32 %1, i32 32767
ret i32 %3
}
declare i32 @llvm.arm.usat(i32, i32) declare i32 @llvm.arm.usat(i32, i32)

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

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; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB5_7: @ %for.body ; CHECK-NEXT: .LBB5_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsh r0, [r12], #2 ; CHECK-NEXT: ldrsh r0, [r12], #2
; CHECK-NEXT: ldrsh r1, [r6], #2 ; CHECK-NEXT: ldrsh r1, [r6], #2
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #15 ; CHECK-NEXT: ssat r0, #16, r0, asr #15
; CHECK-NEXT: ssat r0, #16, r0
; CHECK-NEXT: strh r0, [r4], #2 ; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB5_7 ; CHECK-NEXT: le lr, .LBB5_7
; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB6_7: @ %for.body ; CHECK-NEXT: .LBB6_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsh r0, [r12], #2 ; CHECK-NEXT: ldrsh r0, [r12], #2
; CHECK-NEXT: ldrsh r1, [r6], #2 ; CHECK-NEXT: ldrsh r1, [r6], #2
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #15 ; CHECK-NEXT: ssat r0, #16, r0, asr #15
; CHECK-NEXT: ssat r0, #16, r0
; CHECK-NEXT: strh r0, [r4], #2 ; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB6_7 ; CHECK-NEXT: le lr, .LBB6_7
; CHECK-NEXT: .LBB6_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB6_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB7_7: @ %for.body ; CHECK-NEXT: .LBB7_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsh r0, [r12], #2 ; CHECK-NEXT: ldrsh r0, [r12], #2
; CHECK-NEXT: ldrsh r1, [r6], #2 ; CHECK-NEXT: ldrsh r1, [r6], #2
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #15 ; CHECK-NEXT: ssat r0, #16, r0, asr #15
; CHECK-NEXT: ssat r0, #16, r0
; CHECK-NEXT: strh r0, [r4], #2 ; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB7_7 ; CHECK-NEXT: le lr, .LBB7_7
; CHECK-NEXT: .LBB7_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB7_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB13_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB13_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB13_7: @ %for.body ; CHECK-NEXT: .LBB13_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsb r0, [r12], #1 ; CHECK-NEXT: ldrsb r0, [r12], #1
; CHECK-NEXT: ldrsb r1, [r6], #1 ; CHECK-NEXT: ldrsb r1, [r6], #1
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #7 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
; CHECK-NEXT: ssat r0, #8, r0
; CHECK-NEXT: strb r0, [r4], #1 ; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB13_7 ; CHECK-NEXT: le lr, .LBB13_7
; CHECK-NEXT: .LBB13_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB13_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB14_7: @ %for.body ; CHECK-NEXT: .LBB14_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsb r0, [r12], #1 ; CHECK-NEXT: ldrsb r0, [r12], #1
; CHECK-NEXT: ldrsb r1, [r6], #1 ; CHECK-NEXT: ldrsb r1, [r6], #1
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #7 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
; CHECK-NEXT: ssat r0, #8, r0
; CHECK-NEXT: strb r0, [r4], #1 ; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB14_7 ; CHECK-NEXT: le lr, .LBB14_7
; CHECK-NEXT: .LBB14_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB14_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp10 = icmp eq i32 %N, 0 %cmp10 = icmp eq i32 %N, 0
br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB15_7: @ %for.body ; CHECK-NEXT: .LBB15_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsb r0, [r12], #1 ; CHECK-NEXT: ldrsb r0, [r12], #1
; CHECK-NEXT: ldrsb r1, [r6], #1 ; CHECK-NEXT: ldrsb r1, [r6], #1
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #7 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
; CHECK-NEXT: ssat r0, #8, r0
; CHECK-NEXT: strb r0, [r4], #1 ; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB15_7 ; CHECK-NEXT: le lr, .LBB15_7
; CHECK-NEXT: .LBB15_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB15_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp10 = icmp eq i32 %N, 0 %cmp10 = icmp eq i32 %N, 0
br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
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; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB16_7: @ %for.body ; CHECK-NEXT: .LBB16_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsb r0, [r12], #1 ; CHECK-NEXT: ldrsb r0, [r12], #1
; CHECK-NEXT: ldrsb r1, [r6], #1 ; CHECK-NEXT: ldrsb r1, [r6], #1
; CHECK-NEXT: muls r0, r1, r0 ; CHECK-NEXT: muls r0, r1, r0
; CHECK-NEXT: asrs r0, r0, #7 ; CHECK-NEXT: ssat r0, #8, r0, asr #7
; CHECK-NEXT: ssat r0, #8, r0
; CHECK-NEXT: strb r0, [r4], #1 ; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB16_7 ; CHECK-NEXT: le lr, .LBB16_7
; CHECK-NEXT: .LBB16_8: @ %for.cond.cleanup ; CHECK-NEXT: .LBB16_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%cmp10 = icmp eq i32 %N, 0 %cmp10 = icmp eq i32 %N, 0
br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
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