[ARM] Added more patterns to generate SSAT/USAT with shift

[MeeraN]

Summary

Added patterns to generate an SSAT or USAT with shift for
SSAT/USAT instructions that are matched from IR patterns.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrInfo.td

9

Can you rename ARMssatnoshift to just ARMssat (or something similar). The "noshift" doesn't really need to be part of the node name.

[MeeraN]

Renamed ARMssatnoshift and ARMusatnoshift to ARMssat and ARMusat

[dmgreen]

LGTM. Thanks

llvm/lib/Target/ARM/ARMInstrInfo.td

 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the ARM instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // ARM specific DAG Nodes.
 //
 
 // Type profiles.

 def ARMseretflag     : SDNode<"ARMISD::SERET_FLAG", SDTNone,
                               [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def ARMintretflag    : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
                               [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def ARMcmov          : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
                               [SDNPInGlue]>;
 def ARMsubs          : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>;
 
-def ARMssatnoshift   : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
+def ARMssat   : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
 
-def ARMusatnoshift   : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;
+def ARMusat   : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;
 
 def ARMbrcond        : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
                               [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
 
 def ARMbrjt          : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
                               [SDNPHasChain]>;
 def ARMbr2jt         : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
                               [SDNPHasChain]>;
def USAT16 : AI<(outs GPRnopc:$Rd),
   let Inst{19-16} = sat_imm;
   let Inst{3-0} = Rn;
 }
 
 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
                (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
                (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
-def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
+def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
              (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
-def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
+def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
              (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
 def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos),
                (SSAT16 imm1_16:$pos, GPRnopc:$a)>;
 def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos),
                (USAT16 imm0_15:$pos, GPRnopc:$a)>;
 def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
                (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
 def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
                (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
 def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
                (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
 def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
                (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
+def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
+               (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;                            
+def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
+               (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
+def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;  
+def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
 
 
 //===----------------------------------------------------------------------===//
 //  Bitwise Instructions.
 //
 
 defm AND   : AsI1_bin_irs<0b0000, "and",
                           IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;

llvm/lib/Target/ARM/ARMInstrThumb2.td

 def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),
                      "usat16", "\t$Rd, $sat_imm, $Rn">,
                      Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
   let Inst{23-22} = 0b10;
   let sh = 0b100000;
   let Inst{4} = 0;
 }
 
-def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
+def : T2Pat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
              (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
-def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
+def : T2Pat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
              (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),
             (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos),
             (t2USAT imm0_31:$pos, GPR:$a, 0)>;
 def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos),
             (t2SSAT16 imm1_16:$pos, GPR:$a)>;
 def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos),
             (t2USAT16 imm0_15:$pos, GPR:$a)>;
 def : T2Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
             (t2SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
 def : T2Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
             (t2SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
 def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
             (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
 def : T2Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
             (t2USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
+def : T2Pat<(ARMssat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
+            (t2SSAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : T2Pat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
+            (t2SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
+def : T2Pat<(ARMusat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
+            (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : T2Pat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
+            (t2USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
 
 
 //===----------------------------------------------------------------------===//
 //  Shift and rotate Instructions.
 //
 
 defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
 defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr,  srl>;

llvm/test/CodeGen/ARM/ssat-with-shift.ll

 ; CHECK-NEXT:   ssat  r0, #8, r0, asr #7
 ; CHECK-NEXT:   bx  lr
 entry:
   %shr = ashr i32 %num, 7
   %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)
   ret i32 %0
 }
 
+define arm_aapcs_vfpcc i32 @ssat_lsl2(i32 %num){
+; CHECK-LABEL: ssat_lsl2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    ssat r0, #16, r0, lsl #15
+; CHECK-NEXT:    bx lr
+entry:
+  %shl = shl nsw i32 %num, 15
+  %0 = icmp sgt i32 %shl, -32768
+  %1 = select i1 %0, i32 %shl, i32 -32768
+  %2 = icmp slt i32 %1, 32767
+  %3 = select i1 %2, i32 %1, i32 32767
+  ret i32 %3
+}
+
+define arm_aapcs_vfpcc i32 @ssat_asr2(i32 %num){
+; CHECK-LABEL: ssat_asr2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    ssat r0, #16, r0, asr #15
+; CHECK-NEXT:    bx lr
+entry:
+  %shr = ashr i32 %num, 15
+  %0 = icmp sgt i32 %shr, -32768
+  %1 = select i1 %0, i32 %shr, i32 -32768
+  %2 = icmp slt i32 %1, 32767
+  %3 = select i1 %2, i32 %1, i32 32767
+  ret i32 %3
+}
+
 declare i32 @llvm.arm.ssat(i32, i32)

llvm/test/CodeGen/ARM/usat-with-shift.ll

 ; CHECK-NEXT:   usat  r0, #7, r0, asr #2
 ; CHECK-NEXT:   bx  lr
 entry:
   %shr = ashr i32 %num, 2
   %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
   ret i32 %0
 }
 
+define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
+; CHECK-LABEL: usat_lsl2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    usat r0, #15, r0, lsl #15
+; CHECK-NEXT:    bx lr
+entry:
+  %shl = shl nsw i32 %num, 15
+  %0 = icmp sgt i32 %shl, 0
+  %1 = select i1 %0, i32 %shl, i32 0
+  %2 = icmp slt i32 %1, 32767
+  %3 = select i1 %2, i32 %1, i32 32767
+  ret i32 %3
+}
+
+define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
+; CHECK-LABEL: usat_asr2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    usat r0, #15, r0, asr #15
+; CHECK-NEXT:    bx lr
+entry:
+  %shr = ashr i32 %num, 15
+  %0 = icmp sgt i32 %shr, 0
+  %1 = select i1 %0, i32 %shr, i32 0
+  %2 = icmp slt i32 %1, 32767
+  %3 = select i1 %2, i32 %1, i32 32767
+  ret i32 %3
+}
+
 declare i32 @llvm.arm.usat(i32, i32)

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

 ; CHECK-NEXT:  .LBB5_6: @ %for.body.preheader21
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB5_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsh r0, [r12], #2
 ; CHECK-NEXT:    ldrsh r1, [r6], #2
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #15
-; CHECK-NEXT:    ssat r0, #16, r0
+; CHECK-NEXT:    ssat r0, #16, r0, asr #15
 ; CHECK-NEXT:    strh r0, [r4], #2
 ; CHECK-NEXT:    le lr, .LBB5_7
 ; CHECK-NEXT:  .LBB5_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB6_6: @ %for.body.preheader21
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB6_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsh r0, [r12], #2
 ; CHECK-NEXT:    ldrsh r1, [r6], #2
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #15
-; CHECK-NEXT:    ssat r0, #16, r0
+; CHECK-NEXT:    ssat r0, #16, r0, asr #15
 ; CHECK-NEXT:    strh r0, [r4], #2
 ; CHECK-NEXT:    le lr, .LBB6_7
 ; CHECK-NEXT:  .LBB6_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB7_6: @ %for.body.preheader21
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB7_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsh r0, [r12], #2
 ; CHECK-NEXT:    ldrsh r1, [r6], #2
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #15
-; CHECK-NEXT:    ssat r0, #16, r0
+; CHECK-NEXT:    ssat r0, #16, r0, asr #15
 ; CHECK-NEXT:    strh r0, [r4], #2
 ; CHECK-NEXT:    le lr, .LBB7_7
 ; CHECK-NEXT:  .LBB7_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB13_6: @ %for.body.preheader21
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB13_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsb r0, [r12], #1
 ; CHECK-NEXT:    ldrsb r1, [r6], #1
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #7
-; CHECK-NEXT:    ssat r0, #8, r0
+; CHECK-NEXT:    ssat r0, #8, r0, asr #7
 ; CHECK-NEXT:    strb r0, [r4], #1
 ; CHECK-NEXT:    le lr, .LBB13_7
 ; CHECK-NEXT:  .LBB13_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB14_6: @ %for.body.preheader23
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB14_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsb r0, [r12], #1
 ; CHECK-NEXT:    ldrsb r1, [r6], #1
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #7
-; CHECK-NEXT:    ssat r0, #8, r0
+; CHECK-NEXT:    ssat r0, #8, r0, asr #7
 ; CHECK-NEXT:    strb r0, [r4], #1
 ; CHECK-NEXT:    le lr, .LBB14_7
 ; CHECK-NEXT:  .LBB14_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB15_6: @ %for.body.preheader23
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB15_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsb r0, [r12], #1
 ; CHECK-NEXT:    ldrsb r1, [r6], #1
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #7
-; CHECK-NEXT:    ssat r0, #8, r0
+; CHECK-NEXT:    ssat r0, #8, r0, asr #7
 ; CHECK-NEXT:    strb r0, [r4], #1
 ; CHECK-NEXT:    le lr, .LBB15_7
 ; CHECK-NEXT:  .LBB15_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
 

 ; CHECK-NEXT:  .LBB16_6: @ %for.body.preheader23
 ; CHECK-NEXT:    sub.w lr, r3, r5
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB16_7: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsb r0, [r12], #1
 ; CHECK-NEXT:    ldrsb r1, [r6], #1
 ; CHECK-NEXT:    muls r0, r1, r0
-; CHECK-NEXT:    asrs r0, r0, #7
-; CHECK-NEXT:    ssat r0, #8, r0
+; CHECK-NEXT:    ssat r0, #8, r0, asr #7
 ; CHECK-NEXT:    strb r0, [r4], #1
 ; CHECK-NEXT:    le lr, .LBB16_7
 ; CHECK-NEXT:  .LBB16_8: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader