[llvm-exegesis][PowerPC] Add more register classes

[jsji]

Summary

This PR adds more register class support in PowerPC,
mark OperandType for imm and memory operands.

Also added more unit tests for SnippetGenerator.

[courbet]

This looks good for the llvm-exegesis part. I'm not familiar enough with the PowerPC target to review the rest.

llvm/unittests/tools/llvm-exegesis/PowerPC/TestBase.h

12

I think you meant POWERPC :)

[jsji]

llvm/unittests/tools/llvm-exegesis/PowerPC/TestBase.h

12

Good catch! Thanks,yeah, typical copy and paste error.

[jsji]

Fix typo in header.

[nemanjai]

I think the code being added here (and perhaps the existing code as well) requires deep expertise in both PowerPC ISA and Exegesis. But I think with more descriptive comments, we can make it consumable for those that only check one of those boxes. So most of my comments are requests to add more descriptive/explanatory comments.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

39

I assume you have tracked down other definitions for immediate nodes that don't have this set and there are no others?

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

75

If the instruction is a store, won't the value being stored be one of the operands?

79

Because the stack pointer is guaranteed to point to accessible memory? I still don't understand why we wouldn't materialize the offset into a register here.
It seems odd that for D-Forms, we will access memory Reg + Offset and for X-Forms, we will access memory Reg + <Stack>. Seems this is something that should be documented.

94

Two concerns with this:

1. I assume you are using X11 as it is the last caller saved reg in the allocation order and therefor least likely to be used. Can you document this (along with why you think it is safe to use)? Also, can you give it a descriptive name?
2. There does not appear to be any checking that the immediate fits into a 16-bit signed field. Are we guaranteed to get small immediates? Or perhaps we don't really care that the value we get here is the actual value in the register? Please add a comment.

100

This seems highly suspicious and should be documented if it is correct. For VR registers, we populate a single doubleword. But for VSR registers we populate both doublewords? Why? Also, is there a check elsewhere for P9Vector since you're using MTVSRDD which was added in ISA 3.0?

[jsji]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

39

Yes. At least as far as I can tell now.

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

75

No. Value operand is not included.
This is for MemoryOperands only, which is actually only the addressing operand in real llvm MI..

79

I will add comment. No, we don't really care about the address for now.

94

Sure.
Yeah, we don't really care the actual value in register.
This is to form a valid MI, and repeat it for certain times, to measure latency/throughput etc, we don't really care about the values at all.

100

As I mentioned above, we don't really care about the values in reg. We just want to generate a sequence of valid assembly..

And this will generate a code in a snippet , did not check cpu at all for now.

[jsji]

Address comments.

[jsji]

Ping..

[jsji]

Ping.. Any further comments?

[jsji]

Ping.. Any further comments?

[qiucf]

Thanks for the patch! I think code added is quite clear since most of them already exist as framework in implementation of other platforms. We can continue to support more about exegesis on PowerPC in later patches.

Besides, I found llvm-exegesis -mode=latency -opcode-name=XSTDIVDP complains 'illegal instruction' on ppc64le-pwr9, which looks strange. Is that because we did not model CR well in this tool?

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

22

So, we will mark OPERAND_REGISTER in future patches?

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

102

I applied this patch and tested XSDIVDP, still got 2 lines of warning setRegTo is not implemented, results will be unreliable (before this patch, that is six). Is that from RM and can be ignored?

[jsji]

Thanks @qiucf for looking into this.

Besides, I found llvm-exegesis -mode=latency -opcode-name=XSTDIVDP complains 'illegal instruction' on ppc64le-pwr9, which looks strange. Is that because we did not model CR well in this tool?

It depends. We will generate *random* instructions to form the pattern, so you should try to dump the object to see what is causing illegal instruction.

But on the other hand, yes, as I mentioned , this is an incremental patch, it is far from complete.
So some test may still invalid and causing failures.

We will work to fix them in following patches.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

22

We may, but not necessary, it depends on whether we want to update OperandType for all td files or just update when it matters.

This patch only update for imm as it is required and used in llvm-exegesis.

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

102

Yes, you are right. This patch implemented *more* RC, but not a complete one. We will add more RC in later patch.

[steven.zhang]

LGTM, but as mentioned, we need some follow up to support more instructions. Please hold on for several days to see if @nemanjai has more comments.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 //===----------------------------------------------------------------------===//
 // 64-bit operands.
 //
 def s16imm64 : Operand<i64> {
   let PrintMethod = "printS16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS16ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def u16imm64 : Operand<i64> {
   let PrintMethod = "printU16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCU16ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def s17imm64 : Operand<i64> {
   // This operand type is used for addis/lis to allow the assembler parser
   // to accept immediates in the range -65536..65535 for compatibility with
   // the GNU assembler.  The operand is treated as 16-bit otherwise.
   let PrintMethod = "printS16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS17ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def tocentry : Operand<iPTR> {
   let MIOperandInfo = (ops i64imm:$imm);
 }
 def tlsreg : Operand<i64> {
   let EncoderMethod = "getTLSRegEncoding";
   let ParserMatchClass = PPCTLSRegOperand;
 }

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 def PPCU1ImmAsmOperand : AsmOperandClass {
   let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
   let RenderMethod = "addImmOperands";
 }
 def u1imm   : Operand<i32> {
   let PrintMethod = "printU1ImmOperand";
   let ParserMatchClass = PPCU1ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU2ImmAsmOperand : AsmOperandClass {
   let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
   let RenderMethod = "addImmOperands";
 }
 def u2imm   : Operand<i32> {
   let PrintMethod = "printU2ImmOperand";
   let ParserMatchClass = PPCU2ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCATBitsAsHintAsmOperand : AsmOperandClass {
   let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
   let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
 }
 def atimm   : Operand<i32> {
   let PrintMethod = "printATBitsAsHint";
   let ParserMatchClass = PPCATBitsAsHintAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU3ImmAsmOperand : AsmOperandClass {
   let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
   let RenderMethod = "addImmOperands";
 }
 def u3imm   : Operand<i32> {
   let PrintMethod = "printU3ImmOperand";
   let ParserMatchClass = PPCU3ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def PPCU4ImmAsmOperand : AsmOperandClass {
   let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
   let RenderMethod = "addImmOperands";
 }
 def u4imm   : Operand<i32> {
   let PrintMethod = "printU4ImmOperand";
   let ParserMatchClass = PPCU4ImmAsmOperand;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS5ImmAsmOperand : AsmOperandClass {
   let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
   let RenderMethod = "addImmOperands";
 }
 def s5imm   : Operand<i32> {
   let PrintMethod = "printS5ImmOperand";
   let ParserMatchClass = PPCS5ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<5>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU5ImmAsmOperand : AsmOperandClass {
   let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
   let RenderMethod = "addImmOperands";
 }
 def u5imm   : Operand<i32> {
   let PrintMethod = "printU5ImmOperand";
   let ParserMatchClass = PPCU5ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU6ImmAsmOperand : AsmOperandClass {
   let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
   let RenderMethod = "addImmOperands";
 }
 def u6imm   : Operand<i32> {
   let PrintMethod = "printU6ImmOperand";
   let ParserMatchClass = PPCU6ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU7ImmAsmOperand : AsmOperandClass {
   let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
   let RenderMethod = "addImmOperands";
 }
 def u7imm   : Operand<i32> {
   let PrintMethod = "printU7ImmOperand";
   let ParserMatchClass = PPCU7ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<7>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU8ImmAsmOperand : AsmOperandClass {
   let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
   let RenderMethod = "addImmOperands";
 }
 def u8imm   : Operand<i32> {
   let PrintMethod = "printU8ImmOperand";
   let ParserMatchClass = PPCU8ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<8>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU10ImmAsmOperand : AsmOperandClass {
   let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
   let RenderMethod = "addImmOperands";
 }
 def u10imm  : Operand<i32> {
   let PrintMethod = "printU10ImmOperand";
   let ParserMatchClass = PPCU10ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<10>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU12ImmAsmOperand : AsmOperandClass {
   let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
   let RenderMethod = "addImmOperands";
 }
 def u12imm  : Operand<i32> {
   let PrintMethod = "printU12ImmOperand";
   let ParserMatchClass = PPCU12ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<12>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS16ImmAsmOperand : AsmOperandClass {
   let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
   let RenderMethod = "addS16ImmOperands";
 }
 def s16imm  : Operand<i32> {
   let PrintMethod = "printS16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS16ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCU16ImmAsmOperand : AsmOperandClass {
   let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
   let RenderMethod = "addU16ImmOperands";
 }
 def u16imm  : Operand<i32> {
   let PrintMethod = "printU16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCU16ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS17ImmAsmOperand : AsmOperandClass {
   let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
   let RenderMethod = "addS16ImmOperands";
 }
 def s17imm  : Operand<i32> {
   // This operand type is used for addis/lis to allow the assembler parser
   // to accept immediates in the range -65536..65535 for compatibility with
   // the GNU assembler.  The operand is treated as 16-bit otherwise.
   let PrintMethod = "printS16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS17ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS34ImmAsmOperand : AsmOperandClass {
   let Name = "S34Imm";
   let PredicateMethod = "isS34Imm";
   let RenderMethod = "addImmOperands";
 }
 def s34imm : Operand<i64> {
   let PrintMethod = "printS34ImmOperand";
   let EncoderMethod = "getImm34EncodingNoPCRel";
   let ParserMatchClass = PPCS34ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<34>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def s34imm_pcrel : Operand<i64> {
   let PrintMethod = "printS34ImmOperand";
   let EncoderMethod = "getImm34EncodingPCRel";
   let ParserMatchClass = PPCS34ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<34>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCImmZeroAsmOperand : AsmOperandClass {
   let Name = "ImmZero";
   let PredicateMethod = "isImmZero";
   let RenderMethod = "addImmOperands";
 }
 def immZero : Operand<i32> {
   let PrintMethod = "printImmZeroOperand";
   let ParserMatchClass = PPCImmZeroAsmOperand;
   let DecoderMethod = "decodeImmZeroOperand";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 
 def PPCDirectBrAsmOperand : AsmOperandClass {
   let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
   let RenderMethod = "addBranchTargetOperands";
 }
def dispSPE2 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE2Operand;
 }
 
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getMemRIEncoding";
   let DecoderMethod = "decodeMemRIOperands";
+  let OperandType = "OPERAND_MEMORY";
 }
 def memrr : Operand<iPTR> {
   let PrintMethod = "printMemRegReg";
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
+  let OperandType = "OPERAND_MEMORY";
 }
 def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getMemRIXEncoding";
   let DecoderMethod = "decodeMemRIXOperands";
+  let OperandType = "OPERAND_MEMORY";
 }
 def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getMemRIX16Encoding";
   let DecoderMethod = "decodeMemRIX16Operands";
+  let OperandType = "OPERAND_MEMORY";
 }
 def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE8DisEncoding";
   let DecoderMethod = "decodeSPE8Operands";
+  let OperandType = "OPERAND_MEMORY";
 }
 def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE4DisEncoding";
   let DecoderMethod = "decodeSPE4Operands";
+  let OperandType = "OPERAND_MEMORY";
 }
 def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE2DisEncoding";
   let DecoderMethod = "decodeSPE2Operands";
+  let OperandType = "OPERAND_MEMORY";
 }
 
 // A single-register address. This is used with the SjLj
 // pseudo-instructions which translates to LD/LWZ.  These instructions requires
 // G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
+  let OperandType = "OPERAND_MEMORY";
 }
 def PPCTLSRegOperand : AsmOperandClass {
   let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
   let RenderMethod = "addTLSRegOperands";
 }
 def tlsreg32 : Operand<i32> {
   let EncoderMethod = "getTLSRegEncoding";
   let ParserMatchClass = PPCTLSRegOperand;

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 // The PowerPC ExegesisTarget.
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 #include "PPC.h"
 #include "PPCRegisterInfo.h"
 
 namespace llvm {
 namespace exegesis {
 
+// Helper to fill a memory operand with a value.
+static void setMemOp(InstructionTemplate &IT, int OpIdx,
+                     const MCOperand &OpVal) {
+  const auto Op = IT.getInstr().Operands[OpIdx];
+  assert(Op.isExplicit() && "invalid memory pattern");
+  IT.getValueFor(Op) = OpVal;
+}
+
 #include "PPCGenExegesis.inc"
 
 namespace {
 class ExegesisPowerPCTarget : public ExegesisTarget {
 public:
   ExegesisPowerPCTarget() : ExegesisTarget(PPCCpuPfmCounters) {}
 
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override;
   bool matchesArch(Triple::ArchType Arch) const override {
     return Arch == Triple::ppc64le;
   }
+  unsigned getScratchMemoryRegister(const Triple &) const override;
+  void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+                          unsigned Offset) const override;
 };
 } // end anonymous namespace
 
 static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 32:
     return PPC::LI;
   case 64:
     return PPC::LI8;
   }
   llvm_unreachable("Invalid Value Width");
 }
 
 // Generates instruction to load an immediate value into a register.
 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
                             const APInt &Value) {
   if (Value.getBitWidth() > RegBitWidth)
     llvm_unreachable("Value must fit in the Register");
   return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
+unsigned
+ExegesisPowerPCTarget::getScratchMemoryRegister(const Triple &TT) const {
+  // R13 is reserved as Thread Pointer, we won't use threading in benchmark, so
+  // use it as scratch memory register
+  return TT.isArch64Bit() ? PPC::X13 : PPC::R13;
+}
+
+void ExegesisPowerPCTarget::fillMemoryOperands(InstructionTemplate &IT,
+                                               unsigned Reg,
+                                               unsigned Offset) const {
+  int MemOpIdx = 0;
+  if (IT.getInstr().hasTiedRegisters())
+    MemOpIdx = 1;
+  int DispOpIdx = MemOpIdx + 1;
+  const auto DispOp = IT.getInstr().Operands[DispOpIdx];
+  if (DispOp.isReg())
+    // Hardcoded X1 for X-form Memory Operations
+    setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1));
+  else
+    setMemOp(IT, DispOpIdx, MCOperand::createImm(Offset)); // Disp
+  setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg));   // BaseReg
+}
+
 std::vector<MCInst> ExegesisPowerPCTarget::setRegTo(const MCSubtargetInfo &STI,
                                                     unsigned Reg,
                                                     const APInt &Value) const {
   if (PPC::GPRCRegClass.contains(Reg))
     return {loadImmediate(Reg, 32, Value)};
   if (PPC::G8RCRegClass.contains(Reg))
     return {loadImmediate(Reg, 64, Value)};
-  errs() << "setRegTo is not implemented, results will be unreliable\n";
+  if (PPC::F4RCRegClass.contains(Reg))
+    return {loadImmediate(PPC::X11, 64, Value),
+            MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(PPC::X11)};
+  if (PPC::VRRCRegClass.contains(Reg))
+    return {loadImmediate(PPC::X11, 64, Value),
+            MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(PPC::X11)};
+  if (PPC::VSRCRegClass.contains(Reg))
+    return {loadImmediate(PPC::X11, 64, Value), MCInstBuilder(PPC::MTVSRDD)
+                                                    .addReg(Reg)
+                                                    .addReg(PPC::X11)
+                                                    .addReg(PPC::X11)};
+  if (PPC::VFRCRegClass.contains(Reg))
+    return {loadImmediate(PPC::X11, 64, Value),
+            MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(PPC::X11)};
+  // SPE not supported yet
+  if (PPC::SPERCRegClass.contains(Reg)) {
+    errs() << "Unsupported SPE Reg:" << Reg << "\n";
+    return {};
+  }
+  errs() << "setRegTo is not implemented, results will be unreliable:" << Reg
+         << "\n";
   return {};
 }
 
 static ExegesisTarget *getTheExegesisPowerPCTarget() {
   static ExegesisPowerPCTarget Target;
   return &Target;
 }
 
 void InitializePowerPCExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisPowerPCTarget());
 }
 
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt

set(LLVM_LINK_COMPONENTS
   Object
   Support
   Symbolize
   PowerPC
   )
 
 add_llvm_target_unittest(LLVMExegesisPowerPCTests
   AnalysisTest.cpp
+  SnippetGeneratorTest.cpp
   TargetTest.cpp
   )
 target_link_libraries(LLVMExegesisPowerPCTests PRIVATE
   LLVMExegesis
   LLVMExegesisPowerPC)

llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp

+//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../Common/AssemblerUtils.h"
+#include "LlvmState.h"
+#include "MCInstrDescView.h"
+#include "PPCInstrInfo.h"
+#include "ParallelSnippetGenerator.h"
+#include "RegisterAliasing.h"
+#include "SerialSnippetGenerator.h"
+#include "TestBase.h"
+
+#include <unordered_set>
+
+namespace llvm {
+namespace exegesis {
+namespace {
+
+using testing::AnyOf;
+using testing::ElementsAre;
+using testing::HasSubstr;
+using testing::SizeIs;
+
+MATCHER(IsInvalid, "") { return !arg.isValid(); }
+MATCHER(IsReg, "") { return arg.isReg(); }
+
+class PPCSnippetGeneratorTest : public PPCTestBase {};
+
+template <typename SnippetGeneratorT>
+class SnippetGeneratorTest : public PPCSnippetGeneratorTest {
+protected:
+  SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
+
+  std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
+    randomGenerator().seed(0); // Initialize seed.
+    const Instruction &Instr = State.getIC().getInstr(Opcode);
+    auto CodeTemplateOrError = Generator.generateCodeTemplates(
+        &Instr, State.getRATC().emptyRegisters());
+    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
+    return std::move(CodeTemplateOrError.get());
+  }
+
+  SnippetGeneratorT Generator;
+};
+
+using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
+
+using ParallelSnippetGeneratorTest =
+    SnippetGeneratorTest<ParallelSnippetGenerator>;
+
+TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
+  // - ADD8
+  // - Op0 Explicit Def RegClass(G8RC)
+  // - Op1 Explicit Use RegClass(G8RC)
+  // - Op2 Explicit Use RegClass(G8RC)
+  // - Var0 [Op0]
+  // - Var1 [Op1]
+  // - Var2 [Op2]
+  // - hasAliasingRegisters
+  const unsigned Opcode = PPC::ADD8;
+  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
+  ASSERT_THAT(CodeTemplates, SizeIs(1));
+  const auto &CT = CodeTemplates[0];
+  EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionTemplate &IT = CT.Instructions[0];
+  EXPECT_THAT(IT.getOpcode(), Opcode);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_THAT(IT.getVariableValues(),
+              AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
+                    ElementsAre(IsReg(), IsReg(), IsInvalid())))
+      << "Op0 is either set to Op1 or to Op2";
+}
+
+TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
+
+  // - RLDIMI
+  // - Op0 Explicit Def RegClass(G8RC)
+  // - Op1 Explicit Use RegClass(G8RC) TiedToOp0
+  // - Op2 Explicit Use RegClass(G8RC)
+  // - Op3 Explicit Use Immediate
+  // - Op4 Explicit Use Immediate
+  // - Var0 [Op0,Op1]
+  // - Var1 [Op2]
+  // - Var2 [Op3]
+  // - Var3 [Op4]
+  // - hasTiedRegisters (execution is always serial)
+  // - hasAliasingRegisters
+  // - RLDIMI
+  const unsigned Opcode = PPC::RLDIMI;
+  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
+  ASSERT_THAT(CodeTemplates, SizeIs(1));
+  const auto &CT = CodeTemplates[0];
+  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionTemplate &IT = CT.Instructions[0];
+  EXPECT_THAT(IT.getOpcode(), Opcode);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
+  EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set";
+  EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set";
+}
+
+TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
+  // - LDX
+  // - Op0 Explicit Def RegClass(G8RC)
+  // - Op1 Explicit Use Memory RegClass(GPRC)
+  // - Op2 Explicit Use Memory RegClass(VSSRC)
+  // - Var0 [Op0]
+  // - Var1 [Op1]
+  // - Var2 [Op2]
+  // - hasMemoryOperands
+  // - hasAliasingRegisters
+  const unsigned Opcode = PPC::LDX;
+  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
+  ASSERT_THAT(CodeTemplates, SizeIs(1));
+  const auto &CT = CodeTemplates[0];
+  EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables picking "
+                                 "Uses different from defs"));
+  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
+  ASSERT_THAT(CT.Instructions,
+              SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
+  const InstructionTemplate &IT = CT.Instructions[0];
+  EXPECT_THAT(IT.getOpcode(), Opcode);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_EQ(IT.getVariableValues()[1].getReg(), PPC::X1);
+  EXPECT_EQ(IT.getVariableValues()[2].getReg(), PPC::X13);
+}
+
+} // namespace
+} // namespace exegesis
+} // namespace llvm

llvm/unittests/tools/llvm-exegesis/PowerPC/TestBase.h

+//===-- TestBase.h ----------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// Test fixture common to all PowerPC tests.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_POWERPC_TESTBASE_H
+#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_POWERPC_TESTBASE_H
+
+#include "LlvmState.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+
+namespace llvm {
+namespace exegesis {
+
+void InitializePowerPCExegesisTarget();
+
+class PPCTestBase : public ::testing::Test {
+protected:
+  PPCTestBase() : State("powerpc64le-unknown-linux", "ppc64le") {}
+
+  static void SetUpTestCase() {
+    LLVMInitializePowerPCTargetInfo();
+    LLVMInitializePowerPCTargetMC();
+    LLVMInitializePowerPCTarget();
+    InitializePowerPCExegesisTarget();
+  }
+
+  const LLVMState State;
+};
+
+} // namespace exegesis
+} // namespace llvm
+
+#endif