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Differential D87838

[amdgpu] Compilation fix for Release
ClosedPublic

Authored by bgraur on Sep 17 2020, 8:58 AM.

Details

Reviewers
bkramer
Commits
rG7d593d0d6905: [amdgpu] Compilation fix for Release
Summary

Revision https://github.com/llvm/llvm-project/commit/c3492a1aa1b98c8d81b0969d52cea7681f0624c2 added an unused variable when compiling in Release.
This forward-fixes that.

Diff Detail

Event Timeline

bgraur created this revision.Sep 17 2020, 8:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 17 2020, 8:58 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
bgraur requested review of this revision.Sep 17 2020, 8:58 AM
Herald added a subscriber: wdng. · View Herald TranscriptSep 17 2020, 8:58 AM
bgraur added a reviewer: bkramer.Sep 17 2020, 9:01 AM
bgraur added a subscriber: bkramer.
bkramer accepted this revision.Sep 17 2020, 9:04 AM

looks good

This revision is now accepted and ready to land.Sep 17 2020, 9:04 AM
This revision was landed with ongoing or failed builds.Sep 17 2020, 9:05 AM
Closed by commit rG7d593d0d6905: [amdgpu] Compilation fix for Release (authored by bgraur, committed by bkramer). · Explain Why
This revision was automatically updated to reflect the committed changes.
bkramer added a commit: rG7d593d0d6905: [amdgpu] Compilation fix for Release.
bgraur edited the summary of this revision. (Show Details)Sep 17 2020, 9:06 AM
Harbormaster completed remote builds in B72028: Diff 292528.Sep 17 2020, 9:51 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
1 line

Diff 292528

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 11,530 Lines • ▼ Show 20 Lines for (auto BI = MBB.begin(), BE = MBB.end(); BI != BE; /*EMPTY*/) {
LLVM_DEBUG(dbgs() << "Lower COPY: " << MI); LLVM_DEBUG(dbgs() << "Lower COPY: " << MI);
unsigned Opcode = (TRI.getRegSizeInBits(Src.getReg(), MRI) == 64) unsigned Opcode = (TRI.getRegSizeInBits(Src.getReg(), MRI) == 64)
? AMDGPU::V_MOV_B64_PSEUDO ? AMDGPU::V_MOV_B64_PSEUDO
: AMDGPU::V_MOV_B32_e32; : AMDGPU::V_MOV_B32_e32;
auto DstReg = MI.getOperand(0).getReg(); auto DstReg = MI.getOperand(0).getReg();
auto MIB = BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), DstReg) auto MIB = BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), DstReg)
.add(MI.getOperand(1)); .add(MI.getOperand(1));
(void)MIB;
LLVM_DEBUG(dbgs() << " to: " << *MIB.getInstr()); LLVM_DEBUG(dbgs() << " to: " << *MIB.getInstr());
MI.eraseFromParent(); MI.eraseFromParent();
} }
} }
} }
// Figure out which registers should be reserved for stack access. Only after // Figure out which registers should be reserved for stack access. Only after
// the function is legalized do we know all of the non-spill stack objects or if // the function is legalized do we know all of the non-spill stack objects or if
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