[PowerPC][PCRelative] Thread Local Storage Support for Local Dynamic

[NeHuang]

Summary

This patch is the initial support for the Local Dynamic Thread Local Storage model to produce code sequence and relocation correct
to the ABI for the model when using PC relative memory operations.

[NeHuang]

Ping.

[stefanp]

You can probably merge pcrel-tls-local-dynamic-address-load-reloc.s and pcrel-tls-local-dynamic-value-load-reloc.s.
They are short test cases and they are testing almost exactly the same thing.

I think you can address these nits on review. LGTM.

llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll

6

Consider using --no-show-raw-insn for the objdumps.
We are not checking the instruction encoding.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.h

385

nit: s/produces an PADDI8/produces a PADDI8

[NeHuang]

Addressed nits in the implementation and test cases.

llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_TPREL16_HIGHA
 #undef R_PPC64_DTPREL16_HIGH
 #undef R_PPC64_DTPREL16_HIGHA
 #undef R_PPC64_REL24_NOTOC
 #undef R_PPC64_PCREL_OPT
 #undef R_PPC64_PCREL34
 #undef R_PPC64_GOT_PCREL34
 #undef R_PPC64_TPREL34
+#undef R_PPC64_DTPREL34
 #undef R_PPC64_GOT_TLSGD_PCREL34
+#undef R_PPC64_GOT_TLSLD_PCREL34
 #undef R_PPC64_GOT_TPREL_PCREL34
 #undef R_PPC64_IRELATIVE
 #undef R_PPC64_REL16
 #undef R_PPC64_REL16_LO
 #undef R_PPC64_REL16_HI
 #undef R_PPC64_REL16_HA
 
 ELF_RELOC(R_PPC64_NONE,                 0)

 ELF_RELOC(R_PPC64_TPREL16_HIGHA,        113)
 ELF_RELOC(R_PPC64_DTPREL16_HIGH,        114)
 ELF_RELOC(R_PPC64_DTPREL16_HIGHA,       115)
 ELF_RELOC(R_PPC64_REL24_NOTOC,          116)
 ELF_RELOC(R_PPC64_PCREL_OPT,            123)
 ELF_RELOC(R_PPC64_PCREL34,              132)
 ELF_RELOC(R_PPC64_GOT_PCREL34,          133)
 ELF_RELOC(R_PPC64_TPREL34,              146)
+ELF_RELOC(R_PPC64_DTPREL34,             147)
 ELF_RELOC(R_PPC64_GOT_TLSGD_PCREL34,    148)
+ELF_RELOC(R_PPC64_GOT_TLSLD_PCREL34,    149)
 ELF_RELOC(R_PPC64_GOT_TPREL_PCREL34,    150)
 ELF_RELOC(R_PPC64_IRELATIVE,            248)
 ELF_RELOC(R_PPC64_REL16,                249)
 ELF_RELOC(R_PPC64_REL16_LO,             250)
 ELF_RELOC(R_PPC64_REL16_HI,             251)
 ELF_RELOC(R_PPC64_REL16_HA,             252)

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
     VK_PPC_GOT_TLSGD_PCREL, // symbol@got@tlsgd@pcrel
+    VK_PPC_GOT_TLSLD_PCREL, // symbol@got@tlsld@pcrel
     VK_PPC_GOT_TPREL_PCREL, // symbol@got@tprel@pcrel
     VK_PPC_TLS_PCREL,       // symbol@tls@pcrel
     VK_PPC_TLSLD,           // symbol@tlsld
     VK_PPC_LOCAL,           // symbol@local
     VK_PPC_NOTOC,           // symbol@notoc
     VK_PPC_PCREL_OPT,       // .reloc expr, R_PPC64_PCREL_OPT, expr
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
   case VK_PPC_GOT_TLSGD_PCREL:
     return "got@tlsgd@pcrel";
+  case VK_PPC_GOT_TLSLD_PCREL:
+    return "got@tlsld@pcrel";
   case VK_PPC_GOT_TPREL_PCREL:
     return "got@tprel@pcrel";
   case VK_PPC_TLS_PCREL:
     return "tls@pcrel";
   case VK_PPC_TLSLD: return "tlsld";
   case VK_PPC_LOCAL: return "local";
   case VK_PPC_NOTOC: return "notoc";
   case VK_PPC_PCREL_OPT: return "<<invalid>>";
StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_VE_TPOFF_LO32: return "tpoff_lo";
   }
   llvm_unreachable("Invalid variant kind");
 }
 
 MCSymbolRefExpr::VariantKind
 MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
   return StringSwitch<VariantKind>(Name.lower())
     .Case("dtprel", VK_DTPREL)
     .Case("dtpoff", VK_DTPOFF)
     .Case("got", VK_GOT)
     .Case("gotoff", VK_GOTOFF)
     .Case("gotrel", VK_GOTREL)
     .Case("pcrel", VK_PCREL)
     .Case("gotpcrel", VK_GOTPCREL)
     .Case("gottpoff", VK_GOTTPOFF)
     .Case("indntpoff", VK_INDNTPOFF)
return StringSwitch<VariantKind>(Name.lower())
     .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
     .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
     .Case("got@tlsld", VK_PPC_GOT_TLSLD)
     .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
     .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
     .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
     .Case("got@pcrel", VK_PPC_GOT_PCREL)
     .Case("got@tlsgd@pcrel", VK_PPC_GOT_TLSGD_PCREL)
+    .Case("got@tlsld@pcrel", VK_PPC_GOT_TLSLD_PCREL)
     .Case("got@tprel@pcrel", VK_PPC_GOT_TPREL_PCREL)
     .Case("tls@pcrel", VK_PPC_TLS_PCREL)
     .Case("notoc", VK_PPC_NOTOC)
     .Case("gdgot", VK_Hexagon_GD_GOT)
     .Case("gdplt", VK_Hexagon_GD_PLT)
     .Case("iegot", VK_Hexagon_IE_GOT)
     .Case("ie", VK_Hexagon_IE)
     .Case("ldgot", VK_Hexagon_LD_GOT)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

case PPC::fixup_ppc_pcrel34:
         Type = ELF::R_PPC64_PCREL34;
         break;
       case MCSymbolRefExpr::VK_PPC_GOT_PCREL:
         Type = ELF::R_PPC64_GOT_PCREL34;
         break;
       case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL:
         Type = ELF::R_PPC64_GOT_TLSGD_PCREL34;
         break;
+      case MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL:
+        Type = ELF::R_PPC64_GOT_TLSLD_PCREL34;
+        break;
       case MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL:
         Type = ELF::R_PPC64_GOT_TPREL_PCREL34;
         break;
       }
       break;
     case FK_Data_4:
     case FK_PCRel_4:
       Type = ELF::R_PPC_REL32;
case PPC::fixup_ppc_nofixup:
         Type = ELF::R_PPC64_TLS;
         break;
       }
       break;
     case PPC::fixup_ppc_imm34:
       switch (Modifier) {
       default:
         report_fatal_error("Unsupported Modifier for fixup_ppc_imm34.");
+      case MCSymbolRefExpr::VK_DTPREL:
+        Type = ELF::R_PPC64_DTPREL34;
+        break;
       case MCSymbolRefExpr::VK_TPREL:
         Type = ELF::R_PPC64_TPREL34;
         break;
       }
       break;
     case FK_Data_8:
       switch (Modifier) {
       default: llvm_unreachable("Unsupported Modifier");

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
   case MCExpr::SymbolRef: {
     // Relocation alone.
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
     (void)SRE;
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL ||
+            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL ||
             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
-           "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TPREL_PCREL");
+           "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
+           "VK_PPC_GOT_TPREL_PCREL.");
     // Generate the fixup for the relocation.
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
     // Put zero in the location of the immediate. The linker will fill in the
     // correct value based on the relocation.
     return 0;
   }

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
     /// TLS General Dynamic model.
     MO_TLSGD_FLAG = 32,
 
     /// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Initial Exec model.
     MO_TPREL_FLAG = 64,
 
+    /// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to
+    /// TLS Local Dynamic model.
+    MO_TLSLD_FLAG = 128,
+
     /// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tlsgd@pcrel.
     /// Fix up is VK_PPC_GOT_TLSGD_PCREL
     MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
 
+    /// MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set
+    /// they should produce the relocation @got@tlsld@pcrel.
+    /// Fix up is VK_PPC_GOT_TLSLD_PCREL
+    MO_GOT_TLSLD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSLD_FLAG,
+
     /// MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tprel@pcrel.
     /// Fix up is VK_PPC_GOT_TPREL_PCREL
     MO_GOT_TPREL_PCREL_FLAG = MO_GOT_FLAG | MO_TPREL_FLAG | MO_PCREL_FLAG,
 
     /// The next are not flags but distinct values.
     MO_ACCESS_MASK = 0xf00,
 

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
                                 MCSymbolRefExpr::VariantKind VK) {
   StringRef Name = "__tls_get_addr";
   MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(Name);
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
   unsigned Opcode = PPC::BL8_NOP_TLS;
 
   assert(MI->getNumOperands() >= 3 && "Expecting at least 3 operands from MI");
-  if (MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG) {
+  if (MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
+      MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSLD_PCREL_FLAG) {
     Kind = MCSymbolRefExpr::VK_PPC_NOTOC;
     Opcode = PPC::BL8_NOTOC_TLS;
   }
   const Module *M = MF->getFunction().getParent();
 
   assert(MI->getOperand(0).isReg() &&
          ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
           (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
case PPC::ADDISdtprelHA32: {
     EmitToStreamer(
         *OutStreamer,
         MCInstBuilder(IsPPC64 ? PPC::ADDIS8 : PPC::ADDIS)
             .addReg(MI->getOperand(0).getReg())
             .addReg(MI->getOperand(1).getReg())
             .addExpr(SymDtprel));
     return;
   }
+  case PPC::PADDIdtprel: {
+    // Transform: %rd = PADDIdtprel %rs, @sym
+    // Into:      %rd = PADDI8 %rs, sym@dtprel
+    const MachineOperand &MO = MI->getOperand(2);
+    const GlobalValue *GValue = MO.getGlobal();
+    MCSymbol *MOSymbol = getSymbol(GValue);
+    const MCExpr *SymDtprel = MCSymbolRefExpr::create(
+        MOSymbol, MCSymbolRefExpr::VK_DTPREL, OutContext);
+    EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::PADDI8)
+                                     .addReg(MI->getOperand(0).getReg())
+                                     .addReg(MI->getOperand(1).getReg())
+                                     .addExpr(SymDtprel));
+    return;
+  }
+
   case PPC::ADDIdtprelL:
     // Transform: %xd = ADDIdtprelL %xs, @sym
     // Into:      %xd = ADDI8 %xs, sym@dtprel@l
   case PPC::ADDIdtprelL32: {
     // Transform: %rd = ADDIdtprelL32 %rs, @sym
     // Into:      %rd = ADDI %rs, sym@dtprel@l
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// sym\@dtprel\@ha.
     ADDIS_DTPREL_HA,
 
     /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
     /// model, produces an ADDI8 instruction that adds G8RReg to
     /// sym\@got\@dtprel\@l.
     ADDI_DTPREL_L,
 
+    /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
+    /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel.
+    PADDI_DTPREL,
+
     /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
     /// during instruction selection to optimize a BUILD_VECTOR into
     /// operations on splats.  This is necessary to avoid losing these
     /// optimizations due to constant folding.
     VADD_SPLAT,
 
     /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
     /// operand identifies the operating system entry point.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::GET_TLS_ADDR:    return "PPCISD::GET_TLS_ADDR";
   case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
   case PPCISD::ADDIS_TLSLD_HA:  return "PPCISD::ADDIS_TLSLD_HA";
   case PPCISD::ADDI_TLSLD_L:    return "PPCISD::ADDI_TLSLD_L";
   case PPCISD::GET_TLSLD_ADDR:  return "PPCISD::GET_TLSLD_ADDR";
   case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
   case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
   case PPCISD::ADDI_DTPREL_L:   return "PPCISD::ADDI_DTPREL_L";
+  case PPCISD::PADDI_DTPREL:
+    return "PPCISD::PADDI_DTPREL";
   case PPCISD::VADD_SPLAT:      return "PPCISD::VADD_SPLAT";
   case PPCISD::SC:              return "PPCISD::SC";
   case PPCISD::CLRBHRB:         return "PPCISD::CLRBHRB";
   case PPCISD::MFBHRBE:         return "PPCISD::MFBHRBE";
   case PPCISD::RFEBB:           return "PPCISD::RFEBB";
   case PPCISD::XXSWAPD:         return "PPCISD::XXSWAPD";
   case PPCISD::SWAP_NO_CHAIN:   return "PPCISD::SWAP_NO_CHAIN";
   case PPCISD::VABSD:           return "PPCISD::VABSD";
if (is64bit) {
       else
         GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
     }
     return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
                        GOTPtr, TGA, TGA);
   }
 
   if (Model == TLSModel::LocalDynamic) {
+    if (Subtarget.isUsingPCRelativeCalls()) {
+      SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
+                                               PPCII::MO_GOT_TLSLD_PCREL_FLAG);
+      SDValue MatPCRel =
+          DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
+      return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
+    }
+
     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
     SDValue GOTPtr;
     if (is64bit) {
       setUsesTOCBasePtr(DAG);
       SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
       GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
                            GOTReg, TGA);
     } else {

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
                             (PPCaddisDtprelHA i64:$reg,
                                               tglobaltlsaddr:$disp))]>,
                    isPPC64;
 def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
                          "#ADDIdtprelL",
                          [(set i64:$rD,
                            (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
                   isPPC64;
+def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
+                          "#PADDIdtprel",
+                          [(set i64:$rD,
+                            (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>,
+                  isPPC64;
 
 let PPC970_Unit = 2 in {
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 // Truncating stores.                       
 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
                    "stb $rS, $src", IIC_LdStStore,
                    [(truncstorei8 i64:$rS, iaddr:$src)]>;
 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace PPCII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
       {MO_GOT_FLAG, "ppc-got"},
       {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
       {MO_TLSGD_FLAG, "ppc-tlsgd"},
+      {MO_TLSLD_FLAG, "ppc-tlsld"},
       {MO_TPREL_FLAG, "ppc-tprel"},
       {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
+      {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
       {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas
 // the FP ones have the advantage of lower latency and higher throughput. So
 // what we are after is using the faster instructions in low register pressure

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
                                SDTypeProfile<1, 3, [
                                  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
                                  SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
 def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
+def PPCpaddiDtprel   : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>;
 
 def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
 def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>;
 def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>;
 def PPCxxpermdi  : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;
 def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
 

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
     RefKind = MCSymbolRefExpr::VK_PCREL;
   else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_GOT_FLAG))
     RefKind = MCSymbolRefExpr::VK_PPC_GOT_PCREL;
   else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG))
     RefKind = MCSymbolRefExpr::VK_TPREL;
   else if (MO.getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
     RefKind = MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL;
+  else if (MO.getTargetFlags() == PPCII::MO_GOT_TLSLD_PCREL_FLAG)
+    RefKind = MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL;
   else if (MO.getTargetFlags() == PPCII::MO_GOT_TPREL_PCREL_FLAG)
     RefKind = MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL;
 
   const MachineInstr *MI = MO.getParent();
   const MachineFunction *MF = MI->getMF();
   const Module *M = MF->getFunction().getParent();
   const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
   const TargetMachine &TM = Printer.TM;

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

struct PPCTLSDynamicCall : public MachineFunctionPass {
     const PPCInstrInfo *TII;
     LiveIntervals *LIS;
 
 protected:
     bool processBlock(MachineBasicBlock &MBB) {
       bool Changed = false;
       bool NeedFence = true;
       bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
-      bool IsTLSGDPCREL = false;
+      bool IsPCREL = false;
 
       for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
            I != IE;) {
         MachineInstr &MI = *I;
-        IsTLSGDPCREL = isTLSGDPCREL(MI);
+        IsPCREL = isPCREL(MI);
 
         if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
             MI.getOpcode() != PPC::ADDItlsldLADDR &&
             MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
-            MI.getOpcode() != PPC::ADDItlsldLADDR32 && !IsTLSGDPCREL) {
+            MI.getOpcode() != PPC::ADDItlsldLADDR32 && !IsPCREL) {
           // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
           // as scheduling fences, we skip creating fences if we already
           // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
           // which causes verification error with -verify-machineinstrs.
           if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
             NeedFence = false;
           else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
             NeedFence = true;
 
           ++I;
           continue;
         }
 
         LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n    " << MI);
 
         Register OutReg = MI.getOperand(0).getReg();
         Register InReg = PPC::NoRegister;
         Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
         SmallVector<Register, 3> OrigRegs = {OutReg, GPR3};
-        if (!IsTLSGDPCREL) {
+        if (!IsPCREL) {
           InReg = MI.getOperand(1).getReg();
           OrigRegs.push_back(InReg);
         }
         DebugLoc DL = MI.getDebugLoc();
 
         unsigned Opc1, Opc2;
         switch (MI.getOpcode()) {
         default:
bool processBlock(MachineBasicBlock &MBB) {
           Opc1 = PPC::ADDItlsgdL32;
           Opc2 = PPC::GETtlsADDR32;
           break;
         case PPC::ADDItlsldLADDR32:
           Opc1 = PPC::ADDItlsldL32;
           Opc2 = PPC::GETtlsldADDR32;
           break;
         case PPC::PADDI8pc:
-          assert(IsTLSGDPCREL && "Expecting General Dynamic PCRel");
+          assert(IsPCREL && "Expecting General/Local Dynamic PCRel");
           Opc1 = PPC::PADDI8pc;
-          Opc2 = PPC::GETtlsADDR;
+          Opc2 = MI.getOperand(2).getTargetFlags() ==
+                         PPCII::MO_GOT_TLSGD_PCREL_FLAG
+                     ? PPC::GETtlsADDR
+                     : PPC::GETtlsldADDR;
         }
 
         // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
         // as scheduling fence to avoid it is scheduled before
         // mflr in the prologue and the address in LR is clobbered (PR25839).
         // We don't really need to save data to the stack - the clobbered
         // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
         // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
                                                               .addImm(0);
 
         MachineInstr *Addi;
-        if (IsTLSGDPCREL) {
+        if (IsPCREL) {
           Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
         } else {
           // Expand into two ops built prior to the existing instruction.
           assert(InReg != PPC::NoRegister && "Operand must be a register");
           Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
         }
 
         Addi->addOperand(MI.getOperand(2));
 
         // The ADDItls* instruction is the first instruction in the
         // repair range.
         MachineBasicBlock::iterator First = I;
         --First;
 
         MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
                               .addReg(GPR3));
-        if (IsTLSGDPCREL)
+        if (IsPCREL)
           Call->addOperand(MI.getOperand(2));
         else
           Call->addOperand(MI.getOperand(3));
 
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
 
         BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
bool processBlock(MachineBasicBlock &MBB) {
         LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
         Changed = true;
       }
 
       return Changed;
     }
 
 public:
-  bool isTLSGDPCREL(const MachineInstr &MI) {
+  bool isPCREL(const MachineInstr &MI) {
     return (MI.getOpcode() == PPC::PADDI8pc) &&
            (MI.getOperand(2).getTargetFlags() ==
-            PPCII::MO_GOT_TLSGD_PCREL_FLAG);
+                PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
+            MI.getOperand(2).getTargetFlags() ==
+                PPCII::MO_GOT_TLSLD_PCREL_FLAG);
   }
+
     bool runOnMachineFunction(MachineFunction &MF) override {
       TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
       LIS = &getAnalysis<LiveIntervals>();
 
       bool Changed = false;
 
       for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
         MachineBasicBlock &B = *I++;

llvm/test/CodeGen/PowerPC/pcrel-tls-local-dynamic.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 \
+; RUN:   -ppc-asm-full-reg-names --relocation-model=pic -enable-ppc-pcrel-tls < %s | FileCheck %s --check-prefix=CHECK-S
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 \
+; RUN:   -ppc-asm-full-reg-names --relocation-model=pic -enable-ppc-pcrel-tls --filetype=obj < %s | \
+; RUN:   llvm-objdump --mcpu=pwr10 --no-show-raw-insn -dr - | FileCheck %s --check-prefix=CHECK-O
+
+; These test cases are to ensure that when using pc relative memory operations
+; ABI correct code and relocations are produced for Local Dynamic TLS Model.
+
+@x = hidden thread_local global i32 0, align 4
+
+define nonnull i32* @LocalDynamicAddressLoad() {
+  ; CHECK-S-LABEL: LocalDynamicAddressLoad:
+  ; CHECK-S:         paddi r3, 0, x@got@tlsld@pcrel, 1
+  ; CHECK-S-NEXT:    bl __tls_get_addr@notoc(x@tlsld)
+  ; CHECK-S-NEXT:    paddi r3, r3, x@DTPREL, 0
+  ; CHECK-S-NEXT:    addi r1, r1, 32
+  ; CHECK-S-NEXT:    ld r0, 16(r1)
+  ; CHECK-S-NEXT:    mtlr r0
+  ; CHECK-S-NEXT:    blr
+  ; CHECK-O-LABEL: <LocalDynamicAddressLoad>:
+  ; CHECK-O:         c: paddi 3, 0, 0, 1
+  ; CHECK-O-NEXT:    000000000000000c: R_PPC64_GOT_TLSLD_PCREL34 x
+  ; CHECK-O-NEXT:    14: bl 0x14
+  ; CHECK-O-NEXT:    0000000000000014: R_PPC64_TLSLD x
+  ; CHECK-O-NEXT:    0000000000000014: R_PPC64_REL24_NOTOC __tls_get_addr
+  ; CHECK-O-NEXT:    18: paddi 3, 3, 0, 0
+  ; CHECK-O-NEXT:    0000000000000018: R_PPC64_DTPREL34 x
+  entry:
+    ret i32* @x
+}
+
+define i32 @LocalDynamicValueLoad() {
+  ; CHECK-S-LABEL: LocalDynamicValueLoad:
+  ; CHECK-S:         paddi r3, 0, x@got@tlsld@pcrel, 1
+  ; CHECK-S-NEXT:    bl __tls_get_addr@notoc(x@tlsld)
+  ; CHECK-S-NEXT:    paddi r3, r3, x@DTPREL, 0
+  ; CHECK-S-NEXT:    lwz r3, 0(r3)
+  ; CHECK-S-NEXT:    addi r1, r1, 32
+  ; CHECK-S-NEXT:    ld r0, 16(r1)
+  ; CHECK-S-NEXT:    mtlr r0
+  ; CHECK-S-NEXT:    blr
+  ; CHECK-O-LABEL: <LocalDynamicValueLoad>:
+  ; CHECK-O:         4c: paddi 3, 0, 0, 1
+  ; CHECK-O-NEXT:    000000000000004c: R_PPC64_GOT_TLSLD_PCREL34 x
+  ; CHECK-O-NEXT:    54: bl 0x54
+  ; CHECK-O-NEXT:    0000000000000054: R_PPC64_TLSLD x
+  ; CHECK-O-NEXT:    0000000000000054: R_PPC64_REL24_NOTOC __tls_get_addr
+  ; CHECK-O-NEXT:    58: paddi 3, 3, 0, 0
+  ; CHECK-O-NEXT:    0000000000000058: R_PPC64_DTPREL34 x
+  ; CHECK-O-NEXT:    60: lwz 3, 0(3)
+  entry:
+    %0 = load i32, i32* @x, align 4
+    ret i32 %0
+}

llvm/test/MC/PowerPC/pcrel-tls-local-dynamic-reloc.s

+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s 2>&1 | \
+# RUN: FileCheck %s -check-prefix=MC
+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=READOBJ
+
+# This test checks that on Power PC we can correctly convert @got@tlsld@pcrel
+# x@tlsld, __tls_get_addr@notoc and x@DTPREL into R_PPC64_GOT_TLSLD_PCREL34,
+# R_PPC64_TLSLD, R_PPC64_REL24_NOTOC and R_PPC64_DTPREL34 for local dynamic
+# relocations with address/value loaded
+
+# MC-NOT:  error: invalid variant
+
+# READOBJ:       0x0 R_PPC64_GOT_TLSLD_PCREL34 x 0x0
+# READOBJ-NEXT:  0x8 R_PPC64_TLSLD x 0x0
+# READOBJ-NEXT:  0x8 R_PPC64_REL24_NOTOC __tls_get_addr 0x0
+# READOBJ-NEXT:  0xC R_PPC64_DTPREL34 x 0x0
+# READOBJ-NEXT:  0x18 R_PPC64_GOT_TLSLD_PCREL34 x 0x0
+# READOBJ-NEXT:  0x20 R_PPC64_TLSLD x 0x0
+# READOBJ-NEXT:  0x20 R_PPC64_REL24_NOTOC __tls_get_addr 0x0
+# READOBJ-NEXT:  0x24 R_PPC64_DTPREL34 x 0x0
+
+LocalDynamicAddrLoad:
+  paddi 3, 0, x@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsld)
+  paddi 3, 3, x@DTPREL, 0
+  blr
+
+LocalDynamicValueLoad:
+  paddi 3, 0, x@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsld)
+  paddi 3, 3, x@DTPREL, 0
+  lwz 3, 0(3)
+  blr