[AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads

[evgeny777]

Summary

WriteAdr describes scheduling for first operand of load:

$x0, $x1, $x2 = LDPXpost $x0, 2          # x0 is first

[dmgreen]

STRWpost should be $x0 = STRWpost $xzr, $x0. The concept of scheduling a store can be a little strange, but the address update should come as the first operand.

I agree loads look backwards.

[evgeny777]

@dmgreen Thx, I've updated the diff.

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 let hasSideEffects = 0 in {
 let mayStore = 0, mayLoad = 1 in
 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
              string asm>
     : BaseLoadStorePreIdx<sz, V, opc,
                      (outs GPR64sp:$wback, regtype:$Rt),
                      (ins GPR64sp:$Rn, simm9:$offset), asm,
                      "$Rn = $wback,@earlyclobber $wback", []>,
-      Sched<[WriteLD, WriteAdr]>;
+      Sched<[WriteAdr, WriteLD]>;
 
 let mayStore = 1, mayLoad = 0 in
 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
                   string asm, SDPatternOperator storeop, ValueType Ty>
     : BaseLoadStorePreIdx<sz, V, opc,
                       (outs GPR64sp:$wback),
                       (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
                       asm, "$Rn = $wback,@earlyclobber $wback",

 let hasSideEffects = 0 in {
 let mayStore = 0, mayLoad = 1 in
 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
              string asm>
     : BaseLoadStorePostIdx<sz, V, opc,
                       (outs GPR64sp:$wback, regtype:$Rt),
                       (ins GPR64sp:$Rn, simm9:$offset),
                       asm, "$Rn = $wback,@earlyclobber $wback", []>,
-      Sched<[WriteLD, WriteAdr]>;
+      Sched<[WriteAdr, WriteLD]>;
 
 let mayStore = 1, mayLoad = 0 in
 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
                    string asm, SDPatternOperator storeop, ValueType Ty>
     : BaseLoadStorePostIdx<sz, V, opc,
                       (outs GPR64sp:$wback),
                       (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
                        asm, "$Rn = $wback,@earlyclobber $wback",

 
 let hasSideEffects = 0 in {
 let mayStore = 0, mayLoad = 1 in
 class LoadPairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
                      Operand indextype, string asm>
     : BaseLoadStorePairPreIdx<opc, V, 1,
                               (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
                               (ins GPR64sp:$Rn, indextype:$offset), asm>,
-      Sched<[WriteLD, WriteLDHi, WriteAdr]>;
+      Sched<[WriteAdr, WriteLD, WriteLDHi]>;
 
 let mayStore = 1, mayLoad = 0 in
 class StorePairPreIdx<bits<2> opc, bit V, RegisterOperand regtype,
                       Operand indextype, string asm>
     : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
                              (ins regtype:$Rt, regtype:$Rt2,
                                   GPR64sp:$Rn, indextype:$offset),
                              asm>,

 
 let hasSideEffects = 0 in {
 let mayStore = 0, mayLoad = 1 in
 class LoadPairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,
                       Operand idxtype, string asm>
     : BaseLoadStorePairPostIdx<opc, V, 1,
                               (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
                               (ins GPR64sp:$Rn, idxtype:$offset), asm>,
-      Sched<[WriteLD, WriteLDHi, WriteAdr]>;
+      Sched<[WriteAdr, WriteLD, WriteLDHi]>;
 
 let mayStore = 1, mayLoad = 0 in
 class StorePairPostIdx<bits<2> opc, bit V, RegisterOperand regtype,
                        Operand idxtype, string asm>
     : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
                              (ins regtype:$Rt, regtype:$Rt2,
                                   GPR64sp:$Rn, idxtype:$offset),
                              asm>,

llvm/test/tools/llvm-mca/AArch64/Exynos/load.s

 ldnp  w0, w1, [sp, #8]
 ldp x0, x1, [sp], #16
 ldpsw  x0, x1, [sp, #8]!
 
 1:
 
 # ALL:      Iterations:        100
 # ALL-NEXT: Instructions:      1200
-# ALL-NEXT: Total Cycles:      1904
+# ALL-NEXT: Total Cycles:      1304
 
 # M3-NEXT:  Total uOps:        1600
 # M4-NEXT:  Total uOps:        1400
 # M5-NEXT:  Total uOps:        1400
 
 # ALL:      Dispatch Width:    6
 
-# M3-NEXT:  uOps Per Cycle:    0.84
-# M4-NEXT:  uOps Per Cycle:    0.74
-# M5-NEXT:  uOps Per Cycle:    0.74
+# M3-NEXT:  uOps Per Cycle:    1.23
+# M4-NEXT:  uOps Per Cycle:    1.07
+# M5-NEXT:  uOps Per Cycle:    1.07
 
-# ALL-NEXT: IPC:               0.63
+# ALL-NEXT: IPC:               0.92
 # ALL-NEXT: Block RThroughput: 6.0
 
 # ALL:      Instruction Info:
 # ALL-NEXT: [1]: #uOps
 # ALL-NEXT: [2]: Latency
 # ALL-NEXT: [3]: RThroughput
 # ALL-NEXT: [4]: MayLoad
 # ALL-NEXT: [5]: MayStore