[ELF][PowerPC] Define NOP as 0x60000000 to tidy up code. NFC

[nemanjai]

I am very much in favour of such readability improvements. LGTM.

lld/ELF/Arch/PPC64.cpp

enum DFormOpcd {
   STW = 36,
   STWU = 37,
   STFSU = 53,
   STFDU = 55,
   STD = 62,
   ADDI = 14
 };
 
+constexpr uint32_t NOP = 0x60000000;
+
 enum class PPCLegacyInsn : uint32_t {
   NOINSN = 0,
   // Loads.
   LBZ = 0x88000000,
   LHZ = 0xa0000000,
   LWZ = 0x80000000,
   LHA = 0xa8000000,
   LWA = 0xe8000002,
case R_PPC64_PCREL_OPT: {
     int64_t totalDisp = getTotalDisp(insn, accessInsn);
     if (!isInt<34>(totalDisp))
       break; // Displacement doesn't fit.
     // Convert the PADDI to the prefixed version of accessInsn and convert
     // accessInsn to a nop.
     writePrefixedInstruction(loc, pcRelInsn |
                                       ((totalDisp & 0x3ffff0000) << 16) |
                                       (totalDisp & 0xffff));
-    write32(loc + rel.addend, 0x60000000); // nop accessInsn.
+    write32(loc + rel.addend, NOP); // nop accessInsn.
     break;
   }
   default:
     llvm_unreachable("unexpected relocation type");
   }
 }
 
 void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
   // Relaxing to local exec entails converting:
   // addis r3, r2, x@got@tlsgd@ha    into      nop
   // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
   // bl __tls_get_addr(x@tlsgd)      into      nop
   // nop                             into      addi r3, r3, x@tprel@l
 
   switch (rel.type) {
   case R_PPC64_GOT_TLSGD16_HA:
-    writeFromHalf16(loc, 0x60000000); // nop
+    writeFromHalf16(loc, NOP);
     break;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13
     relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
     break;
   case R_PPC64_TLSGD:
-    write32(loc, 0x60000000);     // nop
+    write32(loc, NOP);
     write32(loc + 4, 0x38630000); // addi r3, r3
     // Since we are relocating a half16 type relocation and Loc + 4 points to
     // the start of an instruction we need to advance the buffer by an extra
     // 2 bytes on BE.
     relocateNoSym(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0),
                   R_PPC64_TPREL16_LO, val);
     break;
   default:
void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
   // Relaxing to local exec entails converting:
   // addis r3, r2, x@got@tlsld@ha   into      nop
   // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
   // bl __tls_get_addr(x@tlsgd)     into      nop
   // nop                            into      addi r3, r3, 4096
 
   switch (rel.type) {
   case R_PPC64_GOT_TLSLD16_HA:
-    writeFromHalf16(loc, 0x60000000); // nop
+    writeFromHalf16(loc, NOP);
     break;
   case R_PPC64_GOT_TLSLD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0
     break;
   case R_PPC64_TLSLD:
-    write32(loc, 0x60000000);     // nop
+    write32(loc, NOP);
     write32(loc + 4, 0x38631000); // addi r3, r3, 4096
     break;
   case R_PPC64_DTPREL16:
   case R_PPC64_DTPREL16_HA:
   case R_PPC64_DTPREL16_HI:
   case R_PPC64_DTPREL16_DS:
   case R_PPC64_DTPREL16_LO:
   case R_PPC64_DTPREL16_LO_DS:
void PPC64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
   // The add instruction in the initial exec sequence has multiple variations
   // that need to be handled. If we are building an address it will use an add
   // instruction, if we are accessing memory it will use any of the X-form
   // indexed load or store instructions.
 
   unsigned offset = (config->ekind == ELF64BEKind) ? 2 : 0;
   switch (rel.type) {
   case R_PPC64_GOT_TPREL16_HA:
-    write32(loc - offset, 0x60000000); // nop
+    write32(loc - offset, NOP);
     break;
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS: {
     uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10
     write32(loc - offset, 0x3C0D0000 | regNo);          // addis RegNo, r13
     relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
     break;
   }
case R_PPC64_TPREL16_DS: {
     uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 0xf : 0x3;
     checkAlignment(loc, lo(val), mask + 1, rel);
     write16(loc, (read16(loc) & mask) | lo(val));
   } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
     if (config->tocOptimize && shouldTocOptimize && ha(val) == 0)
-      writeFromHalf16(loc, 0x60000000);
+      writeFromHalf16(loc, NOP);
     else
       write16(loc, ha(val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
   case R_PPC64_TPREL16_HI:
     write16(loc, hi(val));
     break;
case R_PPC64_GOT_TLSGD16_LO: {
     // Relax from addi  r3, rA, sym@got@tlsgd@l to
     //            ld r3, sym@got@tprel@l(rA)
     uint32_t ra = (readFromHalf16(loc) & (0x1f << 16));
     writeFromHalf16(loc, 0xe8600000 | ra);
     relocateNoSym(loc, R_PPC64_GOT_TPREL16_LO_DS, val);
     return;
   }
   case R_PPC64_TLSGD:
-    write32(loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
+    write32(loc, NOP);            // bl __tls_get_addr(sym@tlsgd) --> nop
     write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
     return;
   default:
     llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
   }
 }
 
 // The prologue for a split-stack function is expected to look roughly
if (getPrimaryOpCode(firstInstr) == 15) {
     return false;
   }
 
   // Second instruction is either an addi or a nop. If the first instruction was
   // an addi then LoImm is set and the second instruction must be a nop.
   uint32_t secondInstr = read32(loc + 8);
   if (!loImm && getPrimaryOpCode(secondInstr) == 14) {
     loImm = secondInstr & 0xFFFF;
-  } else if (secondInstr != 0x60000000) {
+  } else if (secondInstr != NOP) {
     return false;
   }
 
   // The register operands of the first instruction should be the stack-pointer
   // (r1) as the input (RA) and r12 as the output (RT). If the second
   // instruction is not a nop, then it should use r12 as both input and output.
   auto checkRegOperands = [](uint32_t instr, uint8_t expectedRT,
                              uint8_t expectedRA) {
     return ((instr & 0x3E00000) >> 21 == expectedRT) &&
            ((instr & 0x1F0000) >> 16 == expectedRA);
   };
   if (!checkRegOperands(firstInstr, 12, 1))
     return false;
-  if (secondInstr != 0x60000000 && !checkRegOperands(secondInstr, 12, 12))
+  if (secondInstr != NOP && !checkRegOperands(secondInstr, 12, 12))
     return false;
 
   int32_t stackFrameSize = (hiImm * 65536) + loImm;
   // Check that the adjusted size doesn't overflow what we can represent with 2
   // instructions.
   if (stackFrameSize < config->splitStackAdjustSize + INT32_MIN) {
     error(getErrorLocation(loc) + "split-stack prologue adjustment overflows");
     return false;
   }
 
   int32_t adjustedStackFrameSize =
       stackFrameSize - config->splitStackAdjustSize;
 
   loImm = adjustedStackFrameSize & 0xFFFF;
   hiImm = (adjustedStackFrameSize + 0x8000) >> 16;
   if (hiImm) {
     write32(loc + 4, 0x3D810000 | (uint16_t)hiImm);
     // If the low immediate is zero the second instruction will be a nop.
-    secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : 0x60000000;
+    secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : NOP;
     write32(loc + 8, secondInstr);
   } else {
     // addi r12, r1, imm
     write32(loc + 4, (0x39810000) | (uint16_t)loImm);
-    write32(loc + 8, 0x60000000);
+    write32(loc + 8, NOP);
   }
 
   return true;
 }
 
 TargetInfo *elf::getPPC64TargetInfo() {
   static PPC64 target;
   return &target;
 }