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Differential D87287

[ARM] Fixup single source mla reductions.
ClosedPublic

Authored by dmgreen on Sep 8 2020, 6:58 AM.

Details

Reviewers
simon_tatham
SjoerdMeijer
samparker
efriedma
samtebbs
Summary

This fixes a complication on top of D87276. If we are sext-ing around a mul with the two operands that are the same, instcombine will helpfully convert one of the sext to a zext. Reverse that so that we again generate a reduction.

Diff Detail

Event Timeline

dmgreen created this revision.Sep 8 2020, 6:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 8 2020, 6:58 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Sep 8 2020, 6:58 AM
samparker added a comment.Sep 8 2020, 11:54 PM

So this can't be fixed by changing the IsVMLAV logic to accept mul with differing extending inputs then?

dmgreen added a comment.Sep 10 2020, 12:07 AM

It could probably be done either way, but this seemed simpler when I wrote it. I was trying to keep the functions cleaner. Otherwise they will have to start looking backwards from the mul (which has two operands the same) up to the extend to check it's type.

samparker accepted this revision.Sep 10 2020, 12:26 AM

Okay, fair enough.

This revision is now accepted and ready to land.Sep 10 2020, 12:26 AM
dmgreen mentioned this in rG6cfd38d03d5f: [ARM] Fixup single source mla reductions..Sep 12 2020, 6:31 AM
dmgreen closed this revision.Sep 12 2020, 6:49 AM

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
20 lines
test/
CodeGen/
Thumb2/
294 lines
598 lines

Diff 290464

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 14,884 Lines • ▼ Show 20 Linesstatic SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
if (IsPredVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B, Mask)) if (IsPredVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B, Mask))
return Create64bitNode(ARMISD::VMLALVpu, {A, B, Mask}); return Create64bitNode(ARMISD::VMLALVpu, {A, B, Mask});
if (IsPredVMLAV(MVT::i16, ISD::SIGN_EXTEND, {MVT::v16i8}, A, B, Mask)) if (IsPredVMLAV(MVT::i16, ISD::SIGN_EXTEND, {MVT::v16i8}, A, B, Mask))
return DAG.getNode(ISD::TRUNCATE, dl, ResVT, return DAG.getNode(ISD::TRUNCATE, dl, ResVT,
DAG.getNode(ARMISD::VMLAVps, dl, MVT::i32, A, B, Mask)); DAG.getNode(ARMISD::VMLAVps, dl, MVT::i32, A, B, Mask));
if (IsPredVMLAV(MVT::i16, ISD::ZERO_EXTEND, {MVT::v16i8}, A, B, Mask)) if (IsPredVMLAV(MVT::i16, ISD::ZERO_EXTEND, {MVT::v16i8}, A, B, Mask))
return DAG.getNode(ISD::TRUNCATE, dl, ResVT, return DAG.getNode(ISD::TRUNCATE, dl, ResVT,
DAG.getNode(ARMISD::VMLAVpu, dl, MVT::i32, A, B, Mask)); DAG.getNode(ARMISD::VMLAVpu, dl, MVT::i32, A, B, Mask));
// Some complications. We can get a case where the two inputs of the mul are
// the same, then the output sext will have been helpfully converted to a
// zext. Turn it back.
SDValue Op = N0;
if (Op->getOpcode() == ISD::VSELECT)
Op = Op->getOperand(1);
if (Op->getOpcode() == ISD::ZERO_EXTEND &&
Op->getOperand(0)->getOpcode() == ISD::MUL) {
SDValue Mul = Op->getOperand(0);
if (Mul->getOperand(0) == Mul->getOperand(1) &&
Mul->getOperand(0)->getOpcode() == ISD::SIGN_EXTEND) {
SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, N0->getValueType(0), Mul);
if (Op != N0)
Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0),
N0->getOperand(0), Ext, N0->getOperand(2));
return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);
}
}
return SDValue(); return SDValue();
} }
static SDValue PerformVMOVNCombine(SDNode *N, static SDValue PerformVMOVNCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) { TargetLowering::DAGCombinerInfo &DCI) {
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1); SDValue Op1 = N->getOperand(1);
unsigned IsTop = N->getConstantOperandVal(2); unsigned IsTop = N->getConstantOperandVal(2);
▲ Show 20 Lines • Show All 4,156 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Linesentry:
%ma = sext <8 x i32> %m to <8 x i64> %ma = sext <8 x i32> %m to <8 x i64>
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y) { define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext: ; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmlalv.s16 r0, r1, q0, q0
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmullb.s16 q2, q1, q1
; CHECK-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-NEXT: vmov.f32 s12, s8
; CHECK-NEXT: vmov.f32 s14, s9
; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov r1, s13
; CHECK-NEXT: vmov.f32 s12, s10
; CHECK-NEXT: vmov.f32 s14, s11
; CHECK-NEXT: vand q2, q3, q1
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: vmov r1, s11
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmullb.s16 q0, q2, q2
; CHECK-NEXT: vmov.f32 s8, s0
; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vand q2, q2, q1
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: vmov r1, s11
; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vand q0, q2, q1
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%m = mul <8 x i32> %xx, %xx %m = mul <8 x i32> %xx, %xx
%ma = zext <8 x i32> %m to <8 x i64> %ma = zext <8 x i32> %m to <8 x i64>
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
ret i64 %z ret i64 %z
} }
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Linesentry:
%ma = sext <16 x i16> %m to <16 x i32> %ma = sext <16 x i16> %m to <16 x i32>
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext: ; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmlav.s8 r0, q0, q0
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmullb.s8 q1, q1, q1
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.u16 q2, q2
; CHECK-NEXT: vmullb.s8 q0, q3, q3
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmovlb.u16 q3, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmovlb.u16 q1, q3
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmovlb.u16 q0, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%m = mul <16 x i16> %xx, %xx %m = mul <16 x i16> %xx, %xx
%ma = zext <16 x i16> %m to <16 x i32> %ma = zext <16 x i16> %m to <16 x i32>
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
ret i32 %z ret i32 %z
} }
▲ Show 20 Lines • Show All 777 Lines • ▼ Show 20 Linesentry:
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, i64 %a) { define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, i64 %a) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext: ; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: vmlalva.s16 r0, r1, q0, q0
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: bx lr
; CHECK-NEXT: vmov.u16 r2, q0[0]
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[1]
; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vmullb.s16 q1, q1, q1
; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: vmov.32 q3[3], r3
; CHECK-NEXT: vmov lr, s14
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r12, s13
; CHECK-NEXT: adds.w lr, lr, r3
; CHECK-NEXT: adc.w r12, r12, r2, asr #31
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: vmov.32 q1[3], r3
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: adds.w r4, r4, lr
; CHECK-NEXT: adc.w lr, r12, r3
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: adds.w r12, r4, r3
; CHECK-NEXT: adc.w lr, lr, r2, asr #31
; CHECK-NEXT: vmov.u16 r2, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vmullb.s16 q0, q1, q1
; CHECK-NEXT: vmov.f32 s4, s0
; CHECK-NEXT: vmov.f32 s6, s1
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: asrs r4, r2, #31
; CHECK-NEXT: vmov.32 q2[3], r4
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmov r4, s9
; CHECK-NEXT: adds.w r12, r12, r3
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: adc.w r4, r4, lr
; CHECK-NEXT: adds.w r3, r3, r12
; CHECK-NEXT: adc.w r2, r4, r2, asr #31
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: adc.w r2, r2, r4, asr #31
; CHECK-NEXT: vmov r4, s6
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: adc.w r2, r2, r4, asr #31
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: pop {r4, pc}
entry: entry:
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%m = mul <8 x i32> %xx, %xx %m = mul <8 x i32> %xx, %xx
%ma = sext <8 x i32> %m to <8 x i64> %ma = sext <8 x i32> %m to <8 x i64>
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Linesentry:
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, i32 %a) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext: ; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r1, q0[8] ; CHECK-NEXT: vmlava.s8 r0, q0, q0
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[9]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[10]
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[11]
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[12]
; CHECK-NEXT: vmov.16 q1[4], r1
; CHECK-NEXT: vmov.u8 r1, q0[13]
; CHECK-NEXT: vmov.16 q1[5], r1
; CHECK-NEXT: vmov.u8 r1, q0[14]
; CHECK-NEXT: vmov.16 q1[6], r1
; CHECK-NEXT: vmov.u8 r1, q0[15]
; CHECK-NEXT: vmov.16 q1[7], r1
; CHECK-NEXT: vmullb.s8 q1, q1, q1
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[6]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[7]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r1
; CHECK-NEXT: vmov.u8 r1, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r1
; CHECK-NEXT: vmov.u8 r1, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r1
; CHECK-NEXT: vmov.u8 r1, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r1
; CHECK-NEXT: vmovlb.u16 q2, q2
; CHECK-NEXT: vmullb.s8 q0, q3, q3
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.u16 r1, q1[0]
; CHECK-NEXT: vmovlb.u16 q3, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[2]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[3]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmovlb.u16 q1, q3
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[2]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[3]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmovlb.u16 q0, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%m = mul <16 x i16> %xx, %xx %m = mul <16 x i16> %xx, %xx
%ma = zext <16 x i16> %m to <16 x i32> %ma = zext <16 x i16> %m to <16 x i32>
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
▲ Show 20 Lines • Show All 602 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Linesentry:
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer %s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext: ; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: vpt.i16 eq, q2, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vmlalvt.s16 r0, r1, q0, q0
; CHECK-NEXT: vmov.i8 q1, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q2, zr
; CHECK-NEXT: vpsel q2, q3, q1
; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.32 q4[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[2]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[3]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmullb.s16 q3, q1, q1
; CHECK-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: vmov.f32 s22, s13
; CHECK-NEXT: vand q5, q5, q1
; CHECK-NEXT: vand q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: vmov r1, s16
; CHECK-NEXT: vmov r12, s19
; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vand q3, q5, q1
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsb.w r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q4[0], r3
; CHECK-NEXT: rsb.w r0, r0, #0
; CHECK-NEXT: vmov.32 q4[1], r3
; CHECK-NEXT: adc.w r2, r2, r12
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vand q3, q3, q4
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: vmov r3, s15
; CHECK-NEXT: adcs r2, r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: adds.w r12, r1, r0
; CHECK-NEXT: adc.w r1, r2, r3
; CHECK-NEXT: vmov.u16 r2, q2[4]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: vcmp.i32 ne, q3, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q2[2], r3
; CHECK-NEXT: vmov.32 q2[3], r3
; CHECK-NEXT: vmov.u16 r3, q0[4]
; CHECK-NEXT: vmov.32 q3[0], r3
; CHECK-NEXT: vmov.u16 r3, q0[5]
; CHECK-NEXT: vmov.32 q3[1], r3
; CHECK-NEXT: vmov.u16 r3, q0[6]
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vmov.u16 r3, q0[7]
; CHECK-NEXT: vmov.32 q3[3], r3
; CHECK-NEXT: vmullb.s16 q0, q3, q3
; CHECK-NEXT: vmov.f32 s12, s0
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vand q0, q3, q1
; CHECK-NEXT: adds.w r12, r12, r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: adds.w r0, r0, r12
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%m = mul <8 x i32> %xx, %xx %m = mul <8 x i32> %xx, %xx
%ma = zext <8 x i32> %m to <8 x i64> %ma = zext <8 x i32> %m to <8 x i64>
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer %s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Linesentry:
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext: ; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q2, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vmlavt.s8 r0, q0, q0
; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcmp.i8 eq, q2, zr
; CHECK-NEXT: vmov.i8 q2, #0xff
; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vpsel q1, q2, q0
; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vmov.u8 r0, q1[0]
; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[1]
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vcmp.i16 ne, q2, zr
; CHECK-NEXT: vmov.i32 q6, #0x0
; CHECK-NEXT: vpsel q5, q3, q0
; CHECK-NEXT: vmov q7, q6
; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov.i32 q2, #0xffff
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[6]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q4[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q4[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q4[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q4[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q4[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q4[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q4[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q4[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmullb.s8 q3, q3, q3
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q7, q0, q2
; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vcmp.i16 ne, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q4[8]
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q4[9]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q4[10]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q4[11]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q4[12]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q4[13]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q4[14]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q4[15]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmullb.s8 q1, q1, q1
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[0]
; CHECK-NEXT: vmovlb.u16 q4, q4
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q7, q7, q4
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[1]
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vcmp.i32 ne, q4, zr
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q6, q4, q2
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vpt.i32 ne, q2, zr
; CHECK-NEXT: vaddt.i32 q6, q6, q0
; CHECK-NEXT: vadd.i32 q0, q6, q7
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%m = mul <16 x i16> %xx, %xx %m = mul <16 x i16> %xx, %xx
%ma = zext <16 x i16> %m to <16 x i32> %ma = zext <16 x i16> %m to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
▲ Show 20 Lines • Show All 1,331 Lines • ▼ Show 20 Linesentry:
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) { define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext: ; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: vpt.i16 eq, q2, zr
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: vmlalvat.s16 r0, r1, q0, q0
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: bx lr
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.i8 q1, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q2, zr
; CHECK-NEXT: vpsel q2, q3, q1
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[1]
; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q4[0], r3
; CHECK-NEXT: vmov.32 q4[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q4[2], r3
; CHECK-NEXT: vmov.32 q4[3], r3
; CHECK-NEXT: vmov.u16 r3, q0[0]
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.u16 r3, q0[1]
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: vmov.u16 r3, q0[2]
; CHECK-NEXT: vmov.32 q1[2], r3
; CHECK-NEXT: vmov.u16 r3, q0[3]
; CHECK-NEXT: vmov.32 q1[3], r3
; CHECK-NEXT: vmullb.s16 q3, q1, q1
; CHECK-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: vmov.f32 s22, s13
; CHECK-NEXT: vand q5, q5, q1
; CHECK-NEXT: vand q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: vmov r12, s19
; CHECK-NEXT: vmov lr, s17
; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vand q3, q5, q1
; CHECK-NEXT: adds r5, r4, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsb.w r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q4[0], r3
; CHECK-NEXT: rsb.w r2, r2, #0
; CHECK-NEXT: vmov.32 q4[1], r3
; CHECK-NEXT: adc.w r4, lr, r12
; CHECK-NEXT: vmov.32 q4[2], r2
; CHECK-NEXT: vmov.32 q4[3], r2
; CHECK-NEXT: vand q3, q3, q4
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: adds r3, r3, r5
; CHECK-NEXT: vmov r5, s15
; CHECK-NEXT: adcs r2, r4
; CHECK-NEXT: vmov r4, s14
; CHECK-NEXT: adds.w r12, r3, r4
; CHECK-NEXT: adc.w r3, r2, r5
; CHECK-NEXT: vmov.u16 r2, q2[4]
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.32 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.32 q3[3], r2
; CHECK-NEXT: vcmp.i32 ne, q3, zr
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r5, r2, #1
; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: vmov.32 q2[0], r5
; CHECK-NEXT: vmov.32 q2[1], r5
; CHECK-NEXT: ubfx r5, r2, #4, #1
; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: vmov.32 q2[2], r5
; CHECK-NEXT: vmov.32 q2[3], r5
; CHECK-NEXT: vmov.u16 r5, q0[4]
; CHECK-NEXT: vmov.32 q3[0], r5
; CHECK-NEXT: vmov.u16 r5, q0[5]
; CHECK-NEXT: vmov.32 q3[1], r5
; CHECK-NEXT: vmov.u16 r5, q0[6]
; CHECK-NEXT: vmov.32 q3[2], r5
; CHECK-NEXT: vmov.u16 r5, q0[7]
; CHECK-NEXT: vmov.32 q3[3], r5
; CHECK-NEXT: vmullb.s16 q0, q3, q3
; CHECK-NEXT: vmov.f32 s12, s0
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov r4, s8
; CHECK-NEXT: vmov r5, s9
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vand q0, q3, q1
; CHECK-NEXT: adds.w r4, r4, r12
; CHECK-NEXT: adc.w r12, r3, r5
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vmov r5, s11
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: ubfx r4, r2, #8, #1
; CHECK-NEXT: rsb.w r4, r4, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q2[0], r4
; CHECK-NEXT: rsb.w r2, r2, #0
; CHECK-NEXT: vmov.32 q2[1], r4
; CHECK-NEXT: adc.w r5, r5, r12
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: adcs r2, r5
; CHECK-NEXT: vmov r5, s3
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: adcs r2, r5
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%m = mul <8 x i32> %xx, %xx %m = mul <8 x i32> %xx, %xx
%ma = zext <8 x i32> %m to <8 x i64> %ma = zext <8 x i32> %m to <8 x i64>
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer %s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Linesentry:
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext: ; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q2, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vmlavat.s8 r0, q0, q0
; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcmp.i8 eq, q2, zr
; CHECK-NEXT: vmov.i8 q2, #0xff
; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vpsel q1, q2, q0
; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vmov.u8 r1, q1[0]
; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[0], r1
; CHECK-NEXT: vmov.u8 r1, q1[1]
; CHECK-NEXT: vmov.16 q2[1], r1
; CHECK-NEXT: vmov.u8 r1, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov.u8 r1, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r1
; CHECK-NEXT: vmov.u8 r1, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r1
; CHECK-NEXT: vmov.u8 r1, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r1
; CHECK-NEXT: vmov.u8 r1, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r1
; CHECK-NEXT: vmov.u8 r1, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r1
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vcmp.i16 ne, q2, zr
; CHECK-NEXT: vmov.i32 q6, #0x0
; CHECK-NEXT: vpsel q5, q3, q0
; CHECK-NEXT: vmov q7, q6
; CHECK-NEXT: vmov.u16 r1, q5[4]
; CHECK-NEXT: vmov.i32 q2, #0xffff
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q5[5]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q5[6]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q5[7]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q4[0]
; CHECK-NEXT: vmov.16 q3[0], r1
; CHECK-NEXT: vmov.u8 r1, q4[1]
; CHECK-NEXT: vmov.16 q3[1], r1
; CHECK-NEXT: vmov.u8 r1, q4[2]
; CHECK-NEXT: vmov.16 q3[2], r1
; CHECK-NEXT: vmov.u8 r1, q4[3]
; CHECK-NEXT: vmov.16 q3[3], r1
; CHECK-NEXT: vmov.u8 r1, q4[4]
; CHECK-NEXT: vmov.16 q3[4], r1
; CHECK-NEXT: vmov.u8 r1, q4[5]
; CHECK-NEXT: vmov.16 q3[5], r1
; CHECK-NEXT: vmov.u8 r1, q4[6]
; CHECK-NEXT: vmov.16 q3[6], r1
; CHECK-NEXT: vmov.u8 r1, q4[7]
; CHECK-NEXT: vmov.16 q3[7], r1
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmullb.s8 q3, q3, q3
; CHECK-NEXT: vmov.u16 r1, q3[4]
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q3[5]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q3[6]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q3[7]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q1[8]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q7, q0, q2
; CHECK-NEXT: vmov.16 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q1[9]
; CHECK-NEXT: vmov.16 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q1[10]
; CHECK-NEXT: vmov.16 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q1[11]
; CHECK-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q1[12]
; CHECK-NEXT: vmov.16 q0[4], r1
; CHECK-NEXT: vmov.u8 r1, q1[13]
; CHECK-NEXT: vmov.16 q0[5], r1
; CHECK-NEXT: vmov.u8 r1, q1[14]
; CHECK-NEXT: vmov.16 q0[6], r1
; CHECK-NEXT: vmov.u8 r1, q1[15]
; CHECK-NEXT: vmov.16 q0[7], r1
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vcmp.i16 ne, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q4[8]
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmov.u8 r1, q4[9]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov.u8 r1, q4[10]
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov.u8 r1, q4[11]
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q4[12]
; CHECK-NEXT: vmov.16 q1[4], r1
; CHECK-NEXT: vmov.u8 r1, q4[13]
; CHECK-NEXT: vmov.16 q1[5], r1
; CHECK-NEXT: vmov.u8 r1, q4[14]
; CHECK-NEXT: vmov.16 q1[6], r1
; CHECK-NEXT: vmov.u8 r1, q4[15]
; CHECK-NEXT: vmov.16 q1[7], r1
; CHECK-NEXT: vmullb.s8 q1, q1, q1
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov.32 q4[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[6]
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[7]
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.u16 r1, q5[0]
; CHECK-NEXT: vmovlb.u16 q4, q4
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q7, q7, q4
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.u16 r1, q5[1]
; CHECK-NEXT: vmov.32 q4[1], r1
; CHECK-NEXT: vmov.u16 r1, q5[2]
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.u16 r1, q5[3]
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.u16 r1, q3[0]
; CHECK-NEXT: vcmp.i32 ne, q4, zr
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.u16 r1, q3[1]
; CHECK-NEXT: vmov.32 q4[1], r1
; CHECK-NEXT: vmov.u16 r1, q3[2]
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.u16 r1, q3[3]
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q6, q4, q2
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u16 r1, q1[0]
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[2]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[3]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vpt.i32 ne, q2, zr
; CHECK-NEXT: vaddt.i32 q6, q6, q0
; CHECK-NEXT: vadd.i32 q0, q6, q7
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%m = mul <16 x i16> %xx, %xx %m = mul <16 x i16> %xx, %xx
%ma = zext <16 x i16> %m to <16 x i32> %ma = zext <16 x i16> %m to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
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