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Differential D86731

GlobalISel: Implement known bits for min/max
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Authored by arsenm on Aug 27 2020, 11:52 AM.

Details

Reviewers
paquette
aemerson
aditya_nandakumar
volkan
foad
kerbowa

Diff Detail

Event Timeline

arsenm created this revision.Aug 27 2020, 11:52 AM
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Herald added subscribers: hiraditya, rovka, nhaehnle, jvesely. · View Herald Transcript
arsenm requested review of this revision.Aug 27 2020, 11:52 AM
Herald added a subscriber: wdng. · View Herald TranscriptAug 27 2020, 11:52 AM
arsenm added a parent revision: D86729: GlobalISel: Add and_trivial_mask to all_combines.Aug 27 2020, 11:52 AM
paquette accepted this revision.Aug 27 2020, 1:11 PM

LGTM

This revision is now accepted and ready to land.Aug 27 2020, 1:11 PM
arsenm closed this revision.Aug 27 2020, 1:56 PM

abc99ab5725636c17fa9c9ced0269f92bf5398cb

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
4 lines
lib/
CodeGen/
GlobalISel/
38 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
160 lines

Diff 288410

llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h

Show All 28 Linesclass GISelKnownBits : public GISelChangeObserver {
MachineFunction &MF; MachineFunction &MF;
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
const TargetLowering &TL; const TargetLowering &TL;
const DataLayout &DL; const DataLayout &DL;
unsigned MaxDepth; unsigned MaxDepth;
/// Cache maintained during a computeKnownBits request. /// Cache maintained during a computeKnownBits request.
SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache; SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
const APInt &DemandedElts,
unsigned Depth = 0);
public: public:
GISelKnownBits(MachineFunction &MF, unsigned MaxDepth = 6); GISelKnownBits(MachineFunction &MF, unsigned MaxDepth = 6);
virtual ~GISelKnownBits() = default; virtual ~GISelKnownBits() = default;
void setMF(MachineFunction &MF); void setMF(MachineFunction &MF);
const MachineFunction &getMachineFunction() const { const MachineFunction &getMachineFunction() const {
return MF; return MF;
} }
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines dbgs() << "[" << Depth << "] Compute known bits: " << MI << "[" << Depth
<< "] Computed for: " << MI << "[" << Depth << "] Known: 0x" << "] Computed for: " << MI << "[" << Depth << "] Known: 0x"
<< (Known.Zero | Known.One).toString(16, false) << "\n" << (Known.Zero | Known.One).toString(16, false) << "\n"
<< "[" << Depth << "] Zero: 0x" << Known.Zero.toString(16, false) << "[" << Depth << "] Zero: 0x" << Known.Zero.toString(16, false)
<< "\n" << "\n"
<< "[" << Depth << "] One: 0x" << Known.One.toString(16, false) << "[" << Depth << "] One: 0x" << Known.One.toString(16, false)
<< "\n"; << "\n";
} }
/// Compute known bits for the intersection of \p Src0 and \p Src1
void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,
KnownBits &Known,
const APInt &DemandedElts,
unsigned Depth) {
// Test src1 first, since we canonicalize simpler expressions to the RHS.
computeKnownBitsImpl(Src1, Known, DemandedElts, Depth);
// If we don't know any bits, early out.
if (Known.isUnknown())
return;
KnownBits Known2;
computeKnownBitsImpl(Src0, Known2, DemandedElts, Depth);
// Only known if known in both the LHS and RHS.
Known &= Known2;
}
void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known, void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
const APInt &DemandedElts, const APInt &DemandedElts,
unsigned Depth) { unsigned Depth) {
MachineInstr &MI = *MRI.getVRegDef(R); MachineInstr &MI = *MRI.getVRegDef(R);
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
LLT DstTy = MRI.getType(R); LLT DstTy = MRI.getType(R);
// Handle the case where this is called on a register that does not have a // Handle the case where this is called on a register that does not have a
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines unsigned LeadZ =
BitWidth; BitWidth;
Known.resetAll(); Known.resetAll();
Known.Zero.setLowBits(std::min(TrailZ, BitWidth)); Known.Zero.setLowBits(std::min(TrailZ, BitWidth));
Known.Zero.setHighBits(std::min(LeadZ, BitWidth)); Known.Zero.setHighBits(std::min(LeadZ, BitWidth));
break; break;
} }
case TargetOpcode::G_SELECT: { case TargetOpcode::G_SELECT: {
computeKnownBitsImpl(MI.getOperand(3).getReg(), Known, DemandedElts, computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),
Depth + 1); Known, DemandedElts, Depth + 1);
// If we don't know any bits, early out.
if (Known.isUnknown())
break; break;
computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, }
Depth + 1); case TargetOpcode::G_SMIN:
// Only known if known in both the LHS and RHS. case TargetOpcode::G_SMAX:
Known &= Known2; case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX: {
computeKnownBitsMin(MI.getOperand(1).getReg(), MI.getOperand(2).getReg(),
Known, DemandedElts, Depth + 1);
break; break;
} }
case TargetOpcode::G_FCMP: case TargetOpcode::G_FCMP:
case TargetOpcode::G_ICMP: { case TargetOpcode::G_ICMP: {
if (TL.getBooleanContents(DstTy.isVector(), if (TL.getBooleanContents(DstTy.isVector(),
Opcode == TargetOpcode::G_FCMP) == Opcode == TargetOpcode::G_FCMP) ==
TargetLowering::ZeroOrOneBooleanContent && TargetLowering::ZeroOrOneBooleanContent &&
BitWidth > 1) BitWidth > 1)
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir

Show All 14 Lines bb.0:
; CHECK: $vgpr0 = COPY %load(s32) ; CHECK: $vgpr0 = COPY %load(s32)
%ptr:_(p1) = COPY $vgpr0_vgpr1 %ptr:_(p1) = COPY $vgpr0_vgpr1
%load:_(s32) = G_ZEXTLOAD %ptr :: (load 1, addrspace 1, align 1) %load:_(s32) = G_ZEXTLOAD %ptr :: (load 1, addrspace 1, align 1)
%mask:_(s32) = G_CONSTANT i32 255 %mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %load, %mask %and:_(s32) = G_AND %load, %mask
$vgpr0 = COPY %and $vgpr0 = COPY %and
... ...
---
name: remove_and_255_smin_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load 1, addrspace 1)
; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
; CHECK: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK: $vgpr0 = COPY %smin(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load 1, addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load 1, addrspace 1, align 1)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_smax_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smax_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load 1, addrspace 1)
; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
; CHECK: %smax:_(s32) = G_SMAX %load0, %load1
; CHECK: $vgpr0 = COPY %smax(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load 1, addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load 1, addrspace 1, align 1)
%smax:_(s32) = G_SMAX %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smax, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_umin_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_umin_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load 1, addrspace 1)
; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
; CHECK: %umin:_(s32) = G_UMIN %load0, %load1
; CHECK: $vgpr0 = COPY %umin(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load 1, addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load 1, addrspace 1, align 1)
%umin:_(s32) = G_UMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %umin, %mask
$vgpr0 = COPY %and
...
---
name: remove_and_255_umax_zextload
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_umax_zextload
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load 1, addrspace 1)
; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
; CHECK: %umax:_(s32) = G_UMAX %load0, %load1
; CHECK: $vgpr0 = COPY %umax(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load 1, addrspace 1, align 1)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load 1, addrspace 1, align 1)
%umax:_(s32) = G_UMAX %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %umax, %mask
$vgpr0 = COPY %and
...
# Don't have enough known bits for lhs
---
name: remove_and_255_smin_fail_lhs
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_fail_lhs
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_LOAD %ptr0(p1) :: (load 4, addrspace 1)
; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
; CHECK: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK: $vgpr0 = COPY %smin(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_LOAD %ptr0 :: (load 4, addrspace 1, align 4)
%load1:_(s32) = G_ZEXTLOAD %ptr1 :: (load 1, addrspace 1, align 1)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...
# Don't have enough known bits for rhs
---
name: remove_and_255_smin_fail_rhs
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: remove_and_255_smin_fail_rhs
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK: %ptr0:_(p1) = COPY $vgpr0_vgpr1
; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
; CHECK: %load0:_(s32) = G_ZEXTLOAD %ptr0(p1) :: (load 1, addrspace 1)
; CHECK: %load1:_(s32) = G_LOAD %ptr1(p1) :: (load 4, addrspace 1)
; CHECK: %smin:_(s32) = G_SMIN %load0, %load1
; CHECK: %mask:_(s32) = G_CONSTANT i32 255
; CHECK: %and:_(s32) = G_AND %smin, %mask
; CHECK: $vgpr0 = COPY %and(s32)
%ptr0:_(p1) = COPY $vgpr0_vgpr1
%ptr1:_(p1) = COPY $vgpr2_vgpr3
%load0:_(s32) = G_ZEXTLOAD %ptr0 :: (load 1, addrspace 1, align 1)
%load1:_(s32) = G_LOAD %ptr1 :: (load 4, addrspace 1, align 4)
%smin:_(s32) = G_SMIN %load0, %load1
%mask:_(s32) = G_CONSTANT i32 255
%and:_(s32) = G_AND %smin, %mask
$vgpr0 = COPY %and
...