[PowerPC] Fix store-fptoi combine of f128 on Power8

[qiucf]

Summary

llc would crash for the below when -mcpu=pwr8:

define void @qpConv2uw_02(i32* nocapture %res) {
entry:
  %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 2), align 16
  %conv = fptoui fp128 %0 to i32
  store i32 %conv, i32* %res, align 4
  ret void
}

We should not generate FP_TO_(S|U)INT_IN_VSR for f128 types at this time. This patch will fix that.

[qiucf]

Ping..

[qiucf]

Ping.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

13979

Can we check this with isTypeLegal() instead of enum all the conditions ?

[qiucf]

Use isTypeLegal

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14098

I think, we can remove these two lines comment now as it is not needed any more.

[qiucf]

Remove comments

[steven.zhang]

LGTM now.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case ISD::LOAD: {
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
     MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
     Chain = Intrin->getChain();
     // Similarly to the store case below, Intrin->getBasePtr() doesn't get
     // us what we want. Get operand 2 instead.
     Base = Intrin->getOperand(2);
     MMO = Intrin->getMemOperand();
     break;
   }
   }
 
   MVT VecTy = N->getValueType(0).getSimpleVT();
 
   // Do not expand to PPCISD::LXVD2X + PPCISD::XXSWAPD when the load is
   // aligned and the type is a vector with elements up to 4 bytes
SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
 
   assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT)
          && "Not a FP_TO_INT Instruction!");
 
   SDValue Val = N->getOperand(1).getOperand(0);
   EVT Op1VT = N->getOperand(1).getValueType();
   EVT ResVT = Val.getValueType();
 
-  // Floating point types smaller than 32 bits are not legal on Power.
-  if (ResVT.getScalarSizeInBits() < 32)
+  if (!isTypeLegal(ResVT))
     return SDValue();
 
   // Only perform combine for conversion to i64/i32 or power9 i16/i8.
   bool ValidTypeForStoreFltAsInt =
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
   if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)

llvm/test/CodeGen/PowerPC/store_fptoi.ll

 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-PWR8 %s
 
 ; ==========================================
 ; Tests for store of fp_to_sint converstions
 ; ==========================================
 
 ; Function Attrs: norecurse nounwind
+define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i64
+  store i64 %conv, i64* %b, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2sdw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsd [[CONV]], 0(4)
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2sdw
+; CHECK-PWR8: bl __fixkfdi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw(fp128* nocapture readonly %a, i32* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i32
+  store i32 %conv, i32* %b, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2sw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2sw
+; CHECK-PWR8: bl __fixkfsi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2udw(fp128* nocapture readonly %a, i64* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i64
+  store i64 %conv, i64* %b, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2udw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsd [[CONV]], 0(4)
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2udw
+; CHECK-PWR8: bl __fixunskfdi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw(fp128* nocapture readonly %a, i32* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i32
+  store i32 %conv, i32* %b, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2uw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2uw
+; CHECK-PWR8: bl __fixunskfsi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
 define void @dpConv2sdw(double* nocapture readonly %a, i64* nocapture %b) {
 entry:
   %0 = load double, double* %a, align 8
   %conv = fptosi double %0 to i64
   store i64 %conv, i64* %b, align 8
   ret void
 
 ; CHECK-LABEL: dpConv2sdw