[PowerPC] Handle STRICT_FSETCC(S) in more cases

[qiucf]

Summary

On -O0, i1 strict_fsetcc will be promoted to i32. We can't handle that in TD patterns. This patch fills logic in PPCISelDAGToDAG to handle more cases.

[uweigand]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4176

This is wrong for strict mode. You'll need to create a strict version of SELECT_CC here, and this needs to handle the (incoming and outgoing) chain.

4199

This doesn't make sense - the RLWINM instruction does not actually have two outputs. Again, the outgoing chain needs to be processed by the strict SELECT_CC above. The RLWINM (as a pure integer operation) only creates the integer output. It can be merged back with the chain from above using e.g. MERGE_VALUES here.

4210

Same comment as above.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4176

I think here the method name is a little bit confusing.. It doesn't create SELECT_CC, instead, it selects the fcmp* opcode by operand type and predicate, and return a machine node of that.

But yes, the chain needs to be handled here since it's the core FP operation we want.

[qiucf]

Fix chain of fcmp instruction

[uweigand]

This LGTM now, thanks!

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
     bool tryTLSXFormLoad(LoadSDNode *N);
     // tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
     // an X-Form store instruction with the offset being a relocation coming from
     // the PPCISD::ADD_TLS.
     bool tryTLSXFormStore(StoreSDNode *N);
     /// SelectCC - Select a comparison of the specified values with the
     /// specified condition code, returning the CR# of the expression.
     SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
-                     const SDLoc &dl);
+                     const SDLoc &dl, SDValue Chain = SDValue());
 
     /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
     /// immediate field.  Note that the operand at this point is already the
     /// result of a prior SelectAddressRegImm call.
     bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
       if (N.getOpcode() == ISD::TargetConstant ||
           N.getOpcode() == ISD::TargetGlobalAddress) {
         Out = N;
bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
   }
 
   return false;
 }
 
 /// SelectCC - Select a comparison of the specified values with the specified
 /// condition code, returning the CR# of the expression.
 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
-                                  const SDLoc &dl) {
+                                  const SDLoc &dl, SDValue Chain) {
   // Always select the LHS.
   unsigned Opc;
 
   if (LHS.getValueType() == MVT::i32) {
     unsigned Imm;
     if (CC == ISD::SETEQ || CC == ISD::SETNE) {
       if (isInt32Immediate(RHS, Imm)) {
         // SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (Subtarget->hasSPE()) {
       }
     } else
       Opc = Subtarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
   } else {
     assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
     assert(Subtarget->hasVSX() && "__float128 requires VSX");
     Opc = PPC::XSCMPUQP;
   }
+  if (Chain)
+    return SDValue(
+        CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::Other, LHS, RHS, Chain),
+        0);
+  else
     return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
 }
 
 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC, const EVT &VT,
                                            const PPCSubtarget *Subtarget) {
   // For SPE instructions, the result is in GT bit of the CR
   bool UseSPE = Subtarget->hasSPE() && VT.isFloatingPoint();
 
   switch (CC) {
if (VecVT.isFloatingPoint()) {
     }
     llvm_unreachable("Invalid integer vector compare condition");
   }
 }
 
 bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
   SDLoc dl(N);
   unsigned Imm;
-  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  bool IsStrict = N->isStrictFPOpcode();
+  ISD::CondCode CC =
+      cast<CondCodeSDNode>(N->getOperand(IsStrict ? 3 : 2))->get();
   EVT PtrVT =
       CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
   bool isPPC64 = (PtrVT == MVT::i64);
+  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
+
+  SDValue LHS = N->getOperand(IsStrict ? 1 : 0);
+  SDValue RHS = N->getOperand(IsStrict ? 2 : 1);
 
-  if (!Subtarget->useCRBits() && isInt32Immediate(N->getOperand(1), Imm)) {
+  if (!IsStrict && !Subtarget->useCRBits() && isInt32Immediate(RHS, Imm)) {
     // We can codegen setcc op, imm very efficiently compared to a brcond.
     // Check for those cases here.
     // setcc op, 0
     if (Imm == 0) {
-      SDValue Op = N->getOperand(0);
+      SDValue Op = LHS;
       switch (CC) {
       default: break;
       case ISD::SETEQ: {
         Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
         SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
                           getI32Imm(31, dl) };
         CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
         return true;
if (Imm == 0) {
         T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
         SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
                           getI32Imm(31, dl) };
         CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
         return true;
       }
       }
     } else if (Imm == ~0U) {        // setcc op, -1
-      SDValue Op = N->getOperand(0);
+      SDValue Op = LHS;
       switch (CC) {
       default: break;
       case ISD::SETEQ:
         if (isPPC64) break;
         Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
                                             Op, getI32Imm(1, dl)), 0);
         CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
                              SDValue(CurDAG->getMachineNode(PPC::LI, dl,
if (Imm == 0) {
         Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
         CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
         return true;
       }
       }
     }
   }
 
-  SDValue LHS = N->getOperand(0);
-  SDValue RHS = N->getOperand(1);
-
   // Altivec Vector compare instructions do not set any CR register by default and
   // vector compare operations return the same type as the operands.
-  if (LHS.getValueType().isVector()) {
+  if (!IsStrict && LHS.getValueType().isVector()) {
     if (Subtarget->hasSPE())
       return false;
 
     EVT VecVT = LHS.getValueType();
     bool Swap, Negate;
     unsigned int VCmpInst =
         getVCmpInst(VecVT.getSimpleVT(), CC, Subtarget->hasVSX(), Swap, Negate);
     if (Swap)
       std::swap(LHS, RHS);
 
     EVT ResVT = VecVT.changeVectorElementTypeToInteger();
     if (Negate) {
       SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
       CurDAG->SelectNodeTo(N, Subtarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
                            ResVT, VCmp, VCmp);
       return true;
     }
 
     CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
     return true;
   }
 
   if (Subtarget->useCRBits())
     return false;
 
   bool Inv;
   unsigned Idx = getCRIdxForSetCC(CC, Inv);
-  SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
+  SDValue CCReg = SelectCC(LHS, RHS, CC, dl, Chain);
+  if (IsStrict)
+    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), CCReg.getValue(1));
   SDValue IntCR;
 
   // SPE e*cmp* instructions only set the 'gt' bit, so hard-code that
   // The correct compare instruction is already set by SelectCC()
   if (Subtarget->hasSPE() && LHS.getValueType().isFloatingPoint()) {
     Idx = 1;
   }
 
   // Force the ccreg into CR7.
   SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
 
   SDValue InFlag(nullptr, 0);  // Null incoming flag value.
   CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
                                InFlag).getValue(1);
 
   IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
                                          CCReg), 0);
 
   SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
                       getI32Imm(31, dl), getI32Imm(31, dl) };
   if (!Inv) {
     CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
     return true;
   }
 
   // Get the specified bit.
   SDValue Tmp =
     SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
   CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
   return true;
 }
 
 /// Does this node represent a load/store node whose address can be represented
 /// with a register plus an immediate that's a multiple of \p Val:
void PPCDAGToDAGISel::Select(SDNode *N) {
   case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
       ReplaceNode(N, selectI64Imm(CurDAG, N));
       return;
     }
     break;
 
   case ISD::SETCC:
+  case ISD::STRICT_FSETCC:
+  case ISD::STRICT_FSETCCS:
     if (trySETCC(N))
       return;
     break;
   // These nodes will be transformed into GETtlsADDR32 node, which
   // later becomes BL_TLS __tls_get_addr(sym at tlsgd)@PLT
   case PPCISD::ADDI_TLSLD_L_ADDR:
   case PPCISD::ADDI_TLSGD_L_ADDR: {
     const Module *Mod = MF->getFunction().getParent();

llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr9 -O0 | FileCheck %s
+
+define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
+; CHECK-LABEL: une_ppcf128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpudp cr7, f1, f3
+; CHECK-NEXT:    mfocrf r3, 1
+; CHECK-NEXT:    rlwinm r3, r3, 31, 31, 31
+; CHECK-NEXT:    xscmpudp cr7, f2, f4
+; CHECK-NEXT:    mfocrf r4, 1
+; CHECK-NEXT:    rlwinm r4, r4, 31, 31, 31
+; CHECK-NEXT:    xori r4, r4, 1
+; CHECK-NEXT:    and r3, r3, r4
+; CHECK-NEXT:    xscmpudp cr7, f1, f3
+; CHECK-NEXT:    mfocrf r4, 1
+; CHECK-NEXT:    rlwinm r4, r4, 31, 31, 31
+; CHECK-NEXT:    xori r4, r4, 1
+; CHECK-NEXT:    xscmpudp cr7, f1, f3
+; CHECK-NEXT:    mfocrf r5, 1
+; CHECK-NEXT:    rlwinm r5, r5, 31, 31, 31
+; CHECK-NEXT:    xori r5, r5, 1
+; CHECK-NEXT:    and r4, r4, r5
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    # kill: def $r4 killed $r3
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
+  %1 = zext i1 %0 to i32
+  ret i32 %1
+}
+
+; This is a different branch from une
+define i32 @ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
+; CHECK-LABEL: ogt_ppcf128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpudp cr7, f1, f3
+; CHECK-NEXT:    mfocrf r3, 1
+; CHECK-NEXT:    rlwinm r3, r3, 31, 31, 31
+; CHECK-NEXT:    xscmpudp cr7, f2, f4
+; CHECK-NEXT:    mfocrf r4, 1
+; CHECK-NEXT:    rlwinm r4, r4, 30, 31, 31
+; CHECK-NEXT:    and r3, r3, r4
+; CHECK-NEXT:    xscmpudp cr7, f1, f3
+; CHECK-NEXT:    xscmpudp cr0, f1, f3
+; CHECK-NEXT:    mfocrf r4, 1
+; CHECK-NEXT:    rotlwi r4, r4, 28
+; CHECK-NEXT:    stw r4, -4(r1)
+; CHECK-NEXT:    mcrf cr7, cr0
+; CHECK-NEXT:    mfocrf r4, 1
+; CHECK-NEXT:    rlwinm r4, r4, 30, 31, 31
+; CHECK-NEXT:    lwz r5, -4(r1)
+; CHECK-NEXT:    rotlwi r5, r5, 4
+; CHECK-NEXT:    mtocrf 1, r5
+; CHECK-NEXT:    mfocrf r5, 1
+; CHECK-NEXT:    rlwinm r5, r5, 31, 31, 31
+; CHECK-NEXT:    xori r5, r5, 1
+; CHECK-NEXT:    and r4, r5, r4
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    # kill: def $r4 killed $r3
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
+  %1 = zext i1 %0 to i32
+  ret i32 %1
+}
+
+define i1 @test_f128(fp128 %a, fp128 %b) #0 {
+; CHECK-LABEL: test_f128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpuqp cr7, v2, v3
+; CHECK-NEXT:    mfocrf r3, 1
+; CHECK-NEXT:    rlwinm r3, r3, 31, 31, 31
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    # implicit-def: $x4
+; CHECK-NEXT:    mr r4, r3
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
+  ret i1 %0
+}
+
+define i1 @testbr_f64(double %a, double %b) #0 {
+; CHECK-LABEL: testbr_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscmpudp cr7, f1, f2
+; CHECK-NEXT:    mfocrf r3, 1
+; CHECK-NEXT:    rlwinm r3, r3, 31, 31, 31
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    bne cr0, .LBB3_2
+; CHECK-NEXT:    b .LBB3_1
+; CHECK-NEXT:  .LBB3_1: # %tr
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB3_2: # %fl
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") #0
+  br i1 %0, label %tr, label %fl
+tr:
+  ret i1 true
+fl:
+  ret i1 false
+}
+
+define i1 @testbr_f32(float %a, float %b) #0 {
+; CHECK-LABEL: testbr_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fcmpu cr7, f1, f2
+; CHECK-NEXT:    mfocrf r3, 1
+; CHECK-NEXT:    rlwinm r3, r3, 31, 31, 31
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    bne cr0, .LBB4_2
+; CHECK-NEXT:    b .LBB4_1
+; CHECK-NEXT:  .LBB4_1: # %tr
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB4_2: # %fl
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") #0
+  br i1 %0, label %tr, label %fl
+tr:
+  ret i1 true
+fl:
+  ret i1 false
+}
+
+declare i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128, ppc_fp128, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmp.f128(fp128, fp128, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
+
+attributes #0 = { strictfp }