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Differential D86523

[1/5] [llvm-readobj] Fix arm64 unwind opcode disassembly printing
ClosedPublic

Authored by mstorsjo on Aug 25 2020, 4:27 AM.

Details

Reviewers
efriedma
ssijaric
TomTan
jhenderson
Commits
rGdb259fe38b89: [llvm-readobj] Fix arm64 unwind opcode disassembly printing
Summary

Add a missing minus, fix vertical alignment of instructions for one opcode.

Diff Detail

Event Timeline

mstorsjo created this revision.Aug 25 2020, 4:27 AM
Herald added a reviewer: jhenderson. · View Herald TranscriptAug 25 2020, 4:27 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: danielkiss, rupprecht, kristof.beyls. · View Herald Transcript
mstorsjo requested review of this revision.Aug 25 2020, 4:27 AM
Herald added a subscriber: MaskRay. · View Herald TranscriptAug 25 2020, 4:27 AM
mstorsjo added a child revision: D86524: [2/5] [MC] [Win64EH] Update the AArch64/seh.s test slightly. NFC..Aug 25 2020, 4:30 AM
mstorsjo retitled this revision from [llvm-readobj] Fix arm64 unwind opcode disassembly printing to [1/5] [llvm-readobj] Fix arm64 unwind opcode disassembly printing.Aug 25 2020, 4:35 AM
Harbormaster completed remote builds in B69429: Diff 287624.Aug 25 2020, 4:58 AM
efriedma accepted this revision.Aug 25 2020, 1:27 PM

LGTM

This revision is now accepted and ready to land.Aug 25 2020, 1:27 PM
Closed by commit rGdb259fe38b89: [llvm-readobj] Fix arm64 unwind opcode disassembly printing (authored by mstorsjo). · Explain WhyAug 25 2020, 11:38 PM
This revision was automatically updated to reflect the committed changes.
mstorsjo added a commit: rGdb259fe38b89: [llvm-readobj] Fix arm64 unwind opcode disassembly printing.
mstorsjo mentioned this in D87363: [llvm-readobj] [ARMWinEH] Print set_fp/add_fp differently in epilogues.Sep 9 2020, 10:33 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
2 lines
tools/
llvm-readobj/
COFF/
24 lines
tools/
llvm-readobj/
4 lines

Diff 287624

llvm/test/CodeGen/AArch64/wineh5.mir

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# CHECK-NEXT: EpiloguePacked: No # CHECK-NEXT: EpiloguePacked: No
# CHECK-NEXT: EpilogueScopes: 1 # CHECK-NEXT: EpilogueScopes: 1
# CHECK-NEXT: ByteCodeLength: 20 # CHECK-NEXT: ByteCodeLength: 20
# CHECK-NEXT: Prologue [ # CHECK-NEXT: Prologue [
# CHECK-NEXT: 0xe002dac9 ; sub sp, #2993296 # CHECK-NEXT: 0xe002dac9 ; sub sp, #2993296
# CHECK-NEXT: 0xe3 ; nop # CHECK-NEXT: 0xe3 ; nop
# CHECK-NEXT: 0xe3 ; nop # CHECK-NEXT: 0xe3 ; nop
# CHECK-NEXT: 0x42 ; stp x29, x30, [sp, #16] # CHECK-NEXT: 0x42 ; stp x29, x30, [sp, #16]
# CHECK-NEXT: 0xd53f ; str x28, [sp, #256]! # CHECK-NEXT: 0xd53f ; str x28, [sp, #-256]!
# CHECK-NEXT: 0xe4 ; end # CHECK-NEXT: 0xe4 ; end
# CHECK-NEXT: ] # CHECK-NEXT: ]
# CHECK-NEXT: EpilogueScopes [ # CHECK-NEXT: EpilogueScopes [
# CHECK-NEXT: EpilogueScope { # CHECK-NEXT: EpilogueScope {
# CHECK-NEXT: StartOffset: 34 # CHECK-NEXT: StartOffset: 34
# CHECK-NEXT: EpilogueStartIndex: 10 # CHECK-NEXT: EpilogueStartIndex: 10
# CHECK-NEXT: Opcodes [ # CHECK-NEXT: Opcodes [
# CHECK-NEXT: 0xe002da00 ; add sp, #2990080 # CHECK-NEXT: 0xe002da00 ; add sp, #2990080
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llvm/test/tools/llvm-readobj/COFF/arm64-unwind-opcodes.s

  • This file was added.
// REQUIRES: aarch64-registered-target
// RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o - \
// RUN: | llvm-readobj --unwind - | FileCheck %s
// CHECK: Prologue [
// CHECK-NEXT: 0xdc01 ; str d8, [sp, #8]
// CHECK-NEXT: 0xd400 ; str x19, [sp, #-8]!
// CHECK-NEXT: 0xe4 ; end
// CHECK-NEXT: ]
.section .pdata,"dr"
.long func@IMGREL
.long "$unwind$func"@IMGREL
.text
.globl func
func:
str x19, [sp, #-8]!
str d8, [sp, #8]
ret
.section .xdata,"dr"
"$unwind$func":
.long 0x10000002, 0x00d401dc, 0xe3e3e3e4

llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp

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bool Decoder::opcode_save_reg_x(const uint8_t *OC, unsigned &Offset, bool Decoder::opcode_save_reg_x(const uint8_t *OC, unsigned &Offset,
unsigned Length, bool Prologue) { unsigned Length, bool Prologue) {
uint32_t Reg = (OC[Offset] & 0x01) << 8; uint32_t Reg = (OC[Offset] & 0x01) << 8;
Reg |= (OC[Offset + 1] & 0xE0); Reg |= (OC[Offset + 1] & 0xE0);
Reg >>= 5; Reg >>= 5;
Reg += 19; Reg += 19;
uint32_t Off = ((OC[Offset + 1] & 0x1F) + 1) << 3; uint32_t Off = ((OC[Offset + 1] & 0x1F) + 1) << 3;
if (Prologue) if (Prologue)
SW.startLine() << format("0x%02x%02x ; str x%u, [sp, #%u]!\n", SW.startLine() << format("0x%02x%02x ; str x%u, [sp, #-%u]!\n",
OC[Offset], OC[Offset + 1], Reg, Off); OC[Offset], OC[Offset + 1], Reg, Off);
else else
SW.startLine() << format("0x%02x%02x ; ldr x%u, [sp], #%u\n", SW.startLine() << format("0x%02x%02x ; ldr x%u, [sp], #%u\n",
OC[Offset], OC[Offset + 1], Reg, Off); OC[Offset], OC[Offset + 1], Reg, Off);
Offset += 2; Offset += 2;
return false; return false;
} }
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bool Decoder::opcode_save_freg(const uint8_t *OC, unsigned &Offset, bool Decoder::opcode_save_freg(const uint8_t *OC, unsigned &Offset,
unsigned Length, bool Prologue) { unsigned Length, bool Prologue) {
uint32_t Reg = (OC[Offset] & 0x01) << 8; uint32_t Reg = (OC[Offset] & 0x01) << 8;
Reg |= (OC[Offset + 1] & 0xC0); Reg |= (OC[Offset + 1] & 0xC0);
Reg >>= 6; Reg >>= 6;
Reg += 8; Reg += 8;
uint32_t Off = (OC[Offset + 1] & 0x3F) << 3; uint32_t Off = (OC[Offset + 1] & 0x3F) << 3;
SW.startLine() << format("0x%02x%02x ; %s d%u, [sp, #%u]\n", SW.startLine() << format("0x%02x%02x ; %s d%u, [sp, #%u]\n",
OC[Offset], OC[Offset + 1], OC[Offset], OC[Offset + 1],
static_cast<const char *>(Prologue ? "str" : "ldr"), static_cast<const char *>(Prologue ? "str" : "ldr"),
Reg, Off); Reg, Off);
Offset += 2; Offset += 2;
return false; return false;
} }
bool Decoder::opcode_save_freg_x(const uint8_t *OC, unsigned &Offset, bool Decoder::opcode_save_freg_x(const uint8_t *OC, unsigned &Offset,
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