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Differential D85845

AMDGPU/GlobalISel: Fix using readfirstlane with ballot intrinsics
ClosedPublic

Authored by arsenm on Aug 12 2020, 9:38 AM.

Details

Reviewers
Petar.Avramovic
mbrkusanin
foad
nhaehnle
kerbowa
sebastian-ne
Summary

This should use the default mapping and insert a copy to the vcc bank,
and not try to insert a readfirstlane.

Diff Detail

Event Timeline

arsenm created this revision.Aug 12 2020, 9:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 12 2020, 9:38 AM
Herald added subscribers: hiraditya, t-tye, tpr and 5 others. · View Herald Transcript
arsenm requested review of this revision.Aug 12 2020, 9:38 AM
Herald added a subscriber: wdng. · View Herald TranscriptAug 12 2020, 9:38 AM
arsenm added a child revision: D85846: AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands..Aug 12 2020, 9:50 AM
foad added a reviewer: sebastian-ne.Aug 17 2020, 5:17 AM
sebastian-ne accepted this revision.Aug 17 2020, 6:24 AM

This looks better than what was there before, thanks.

This revision is now accepted and ready to land.Aug 17 2020, 6:24 AM
arsenm closed this revision.Aug 17 2020, 6:54 AM

af162ac785dd6aa371afc0f111544c82d72c5242

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
64 lines

Diff 285119

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 2,981 Lines • ▼ Show 20 Lines case Intrinsic::amdgcn_writelane: {
assert(OpdMapper.getVRegs(2).empty()); assert(OpdMapper.getVRegs(2).empty());
assert(OpdMapper.getVRegs(3).empty()); assert(OpdMapper.getVRegs(3).empty());
substituteSimpleCopyRegs(OpdMapper, 4); // VGPR input val substituteSimpleCopyRegs(OpdMapper, 4); // VGPR input val
constrainOpWithReadfirstlane(MI, MRI, 2); // Source value constrainOpWithReadfirstlane(MI, MRI, 2); // Source value
constrainOpWithReadfirstlane(MI, MRI, 3); // Index constrainOpWithReadfirstlane(MI, MRI, 3); // Index
return; return;
} }
case Intrinsic::amdgcn_ballot:
case Intrinsic::amdgcn_interp_p1: case Intrinsic::amdgcn_interp_p1:
case Intrinsic::amdgcn_interp_p2: case Intrinsic::amdgcn_interp_p2:
case Intrinsic::amdgcn_interp_mov: case Intrinsic::amdgcn_interp_mov:
case Intrinsic::amdgcn_interp_p1_f16: case Intrinsic::amdgcn_interp_p1_f16:
case Intrinsic::amdgcn_interp_p2_f16: { case Intrinsic::amdgcn_interp_p2_f16: {
applyDefaultMapping(OpdMapper); applyDefaultMapping(OpdMapper);
// Readlane for m0 value, which is always the last operand. // Readlane for m0 value, which is always the last operand.
Show All 11 Lines case Intrinsic::amdgcn_permlanex16: {
return; return;
} }
case Intrinsic::amdgcn_sbfe: case Intrinsic::amdgcn_sbfe:
applyMappingBFEIntrinsic(OpdMapper, true); applyMappingBFEIntrinsic(OpdMapper, true);
return; return;
case Intrinsic::amdgcn_ubfe: case Intrinsic::amdgcn_ubfe:
applyMappingBFEIntrinsic(OpdMapper, false); applyMappingBFEIntrinsic(OpdMapper, false);
return; return;
case Intrinsic::amdgcn_ballot:
// Use default handling and insert copy to vcc source.
break;
} }
break; break;
} }
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD: case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD:
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: { case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: {
const AMDGPU::RsrcIntrinsic *RSrcIntrin const AMDGPU::RsrcIntrinsic *RSrcIntrin
= AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID()); = AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID());
assert(RSrcIntrin && RSrcIntrin->IsImage); assert(RSrcIntrin && RSrcIntrin->IsImage);
▲ Show 20 Lines • Show All 1,439 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: ballot_sgpr_src
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ballot_sgpr_src
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1)
; CHECK: S_ENDPGM 0, implicit [[INT]](s64)
%0:_(s32) = COPY $sgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), %1
S_ENDPGM 0, implicit %2
...
---
name: ballot_vgpr_src
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ballot_vgpr_src
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1)
; CHECK: S_ENDPGM 0, implicit [[INT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), %1
S_ENDPGM 0, implicit %2
...
---
name: ballot_vcc_src
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: ballot_vcc_src
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1)
; CHECK: S_ENDPGM 0, implicit [[INT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(eq), %0, %1
%3:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), %2
S_ENDPGM 0, implicit %3
...