[PowerPC] Add compatibility check for PPC PLT stubs

[NeHuang]

Summary

Compatibility checking for PPC64PltCallStub and PPC64PCRelPLTStub are needed to avoid incompatible thunk/stub re-using.

[NeHuang]

Fixed nits in the test case to

• Add start address.
• Fix indentations.

[stefanp]

I think this looks good! Thank you for fixing this issue.

[sfertile]

LGTM.

lld/ELF/Thunks.cpp

872

Would it be better to explicitly check for R_PPC64_REL24 and R_PPC64_REL14?

[NeHuang]

Addressed the comment to check R_PPC64_REL24 and R_PPC64_REL14 for PPC64PltCallStub compatibility check.

[NeHuang]

lld/ELF/Thunks.cpp

872

Good catch! Updated.

lld/ELF/Thunks.cpp

 //    register.
 // 3) Transferring control to the target function through an indirect branch.
 class PPC64PltCallStub final : public Thunk {
 public:
   PPC64PltCallStub(Symbol &dest) : Thunk(dest, 0) {}
   uint32_t size() override { return 20; }
   void writeTo(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
+  bool isCompatibleWith(const InputSection &isec,
+                        const Relocation &rel) const override;
 };
 
 // PPC64 R2 Save Stub
 // When the caller requires a valid R2 TOC pointer but the callee does not
 // require a TOC pointer and the callee cannot guarantee that it doesn't
 // clobber R2 then we need to save R2. This stub:
 // 1) Saves the TOC pointer to the stack.
 // 2) Tail calls the callee.

 //    register with pc-relative instructions.
 // 2) Transferring control to the target function through an indirect branch.
 class PPC64PCRelPLTStub final : public Thunk {
 public:
   PPC64PCRelPLTStub(Symbol &dest) : Thunk(dest, 0) {}
   uint32_t size() override { return 16; }
   void writeTo(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
+  bool isCompatibleWith(const InputSection &isec,
+                        const Relocation &rel) const override;
 };
 
 // A bl instruction uses a signed 24 bit offset, with an implicit 4 byte
 // alignment. This gives a possible 26 bits of 'reach'. If the call offset is
 // larger then that we need to emit a long-branch thunk. The target address
 // of the callee is stored in a table to be accessed TOC-relative. Since the
 // call must be local (a non-local call will have a PltCallStub instead) the
 // table stores the address of the callee's local entry point. For

 
 void PPC64PltCallStub::addSymbols(ThunkSection &isec) {
   Defined *s = addSymbol(saver.save("__plt_" + destination.getName()), STT_FUNC,
                          0, isec);
   s->needsTocRestore = true;
   s->file = destination.file;
 }
 
+bool PPC64PltCallStub::isCompatibleWith(const InputSection &isec,
+                                        const Relocation &rel) const {
+  return rel.type == R_PPC64_REL24 || rel.type == R_PPC64_REL14;
+}
+
 void PPC64R2SaveStub::writeTo(uint8_t *buf) {
   int64_t offset = destination.getVA() - (getThunkTargetSym()->getVA() + 4);
   // The branch offset needs to fit in 26 bits.
   if (!isInt<26>(offset))
     fatal("R2 save stub branch offset is too large: " + Twine(offset));
   write32(buf + 0, 0xf8410018);                         // std  r2,24(r1)
   write32(buf + 4, 0x48000000 | (offset & 0x03fffffc)); // b    <offset>
 }
void PPC64PCRelPLTStub::writeTo(uint8_t *buf) {
   write32(buf + 12, BCTR);                // bctr
 }
 
 void PPC64PCRelPLTStub::addSymbols(ThunkSection &isec) {
   addSymbol(saver.save("__plt_pcrel_" + destination.getName()), STT_FUNC, 0,
             isec);
 }
 
+bool PPC64PCRelPLTStub::isCompatibleWith(const InputSection &isec,
+                                         const Relocation &rel) const {
+  return rel.type == R_PPC64_REL24_NOTOC;
+}
+
 void PPC64LongBranchThunk::writeTo(uint8_t *buf) {
   int64_t offset = in.ppc64LongBranchTarget->getEntryVA(&destination, addend) -
                    getPPC64TocBase();
   writePPC64LoadAndBranch(buf, offset);
 }
 
 void PPC64LongBranchThunk::addSymbols(ThunkSection &isec) {
   addSymbol(saver.save("__long_branch_" + destination.getName()), STT_FUNC, 0,

lld/test/ELF/ppc64-plt-stub-compatible.s

+# REQUIRES: ppc
+# RUN: echo 'SECTIONS { \
+# RUN:   .text_start 0x10010300 : { *(.text_start) } \
+# RUN:   }' > %t.script
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T1=1 -o %t1.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T2=1 -o %t2.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T3=1 -o %t3.o
+# RUN: ld.lld --shared %t1.o -o %t1.so
+# RUN: ld.lld -T %t.script %t1.so %t2.o -o %t2
+# RUN: ld.lld -T %t.script %t1.so %t3.o -o %t3
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t2 | FileCheck %s --check-prefix=T2
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t3 | FileCheck %s --check-prefix=T3
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T1=1 -o %t1.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T2=1 -o %t2.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T3=1 -o %t3.o
+# RUN: ld.lld --shared %t1.o -o %t1.so
+# RUN: ld.lld -T %t.script %t1.so %t2.o -o %t2
+# RUN: ld.lld -T %t.script %t1.so %t3.o -o %t3
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t2 | FileCheck %s --check-prefix=T2
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t3 | FileCheck %s --check-prefix=T3
+
+.ifdef T1
+.globl callee
+callee:
+  blr
+.endif
+
+# T2-LABEL: <p9codegen>:
+# T2-NEXT:    10010300: addis 2, 12, 1
+# T2-NEXT:    10010304: addi 2, 2, -32392
+# T2-NEXT:    10010308: addis 4, 2, -1
+# T2-NEXT:    1001030c: lwa 3, 32436(4)
+# T2-NEXT:    10010310: bl 0x10010330
+# T2-NEXT:    10010314: ld 2, 24(1)
+# T2-NEXT:    10010318: blr
+
+# T2-LABEL: <p10codegen>:
+# T2-NEXT:    1001031c: plwa 3, 16(0), 1
+# T2-NEXT:    10010324: bl 0x10010344
+# T2-NEXT:    10010328: blr
+
+# T2-LABEL: <__plt_callee>:
+# T2-NEXT:    10010330: std 2, 24(1)
+# T2-NEXT:    10010334: addis 12, 2, 0
+# T2-NEXT:    10010338: ld 12, -32744(12)
+# T2-NEXT:    1001033c: mtctr 12
+# T2-NEXT:    10010340: bctr
+
+# T2-LABEL: <__plt_pcrel_callee>:
+# T2-NEXT:    10010344: pld 12, 332(0), 1
+# T2-NEXT:    1001034c: mtctr 12
+# T2-NEXT:    10010350: bctr
+.ifdef T2
+.section .text_start, "ax", %progbits
+p9codegen:
+.Lfunc_gep0:
+  addis 2, 12, .TOC.-.Lfunc_gep0@ha
+  addi 2, 2, .TOC.-.Lfunc_gep0@l
+.Lfunc_lep0:
+  .localentry p9codegen, .Lfunc_lep0-.Lfunc_gep0
+  addis 4, 2, Global@toc@ha
+  lwa 3, Global@toc@l(4)
+  bl callee
+  nop
+  blr
+p10codegen:
+  .localentry main, 1
+  plwa 3, Global@PCREL(0), 1
+  bl callee@notoc
+  blr
+.globl Global
+Global:
+  .long 10
+  .size Global, 4
+.endif
+
+# T3-LABEL: <p10codegen>:
+# T3-NEXT:    10010300: plwa 3, 44(0), 1
+# T3-NEXT:    10010308: bl 0x10010330
+# T3-NEXT:    1001030c: blr
+
+# T3-LABEL: <p9codegen>:
+# T3-NEXT:    10010310: addis 2, 12, 1
+# T3-NEXT:    10010314: addi 2, 2, -32408
+# T3-NEXT:    10010318: addis 4, 2, -1
+# T3-NEXT:    1001031c: lwa 3, 32436(4)
+# T3-NEXT:    10010320: bl 0x10010340
+# T3-NEXT:    10010324: ld 2, 24(1)
+# T3-NEXT:    10010328: blr
+
+# T3-LABEL: <__plt_pcrel_callee>:
+# T3-NEXT:    10010330: pld 12, 352(0), 1
+# T3-NEXT:    10010338: mtctr 12
+# T3-NEXT:    1001033c: bctr
+
+# T3-LABEL: <__plt_callee>:
+# T3-NEXT:    10010340: std 2, 24(1)
+# T3-NEXT:    10010344: addis 12, 2, 0
+# T3-NEXT:    10010348: ld 12, -32744(12)
+# T3-NEXT:    1001034c: mtctr 12
+# T3-NEXT:    10010350: bctr
+.ifdef T3
+.section .text_start, "ax", %progbits
+p10codegen:
+  .localentry   main, 1
+  plwa 3, Global@PCREL(0), 1
+  bl callee@notoc
+  blr
+p9codegen:
+.Lfunc_gep0:
+  addis 2, 12, .TOC.-.Lfunc_gep0@ha
+  addi 2, 2, .TOC.-.Lfunc_gep0@l
+.Lfunc_lep0:
+  .localentry   p9codegen, .Lfunc_lep0-.Lfunc_gep0
+  addis 4, 2, Global@toc@ha
+  lwa 3, Global@toc@l(4)
+  bl callee
+  nop
+  blr
+.globl Global
+Global:
+  .long 10
+  .size Global, 4
+.endif