[GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel.

[cameron.mcinally]

Summary

This patch stops unconditionally transforming FSUB(-0, X) into an FNEG(X) while building the MIR.

This corresponds with the old ISel change in D84056.

[arsenm]

I think this leaves behind a redundant test_fneg/test_fneg_fmf case elsewhere

[cameron.mcinally]

In D85139#2193065, @arsenm wrote:

I think this leaves behind a redundant test_fneg/test_fneg_fmf case elsewhere

You're probably right. Just took a look and I don't see anything obvious though. Did you have a particular set of tests in mind?

I do see some tests that transform an illegal G_FNEG into an G_FSUB. I don't fully understand the motivation yet, but that's probably worth attention.

[arsenm]

In D85139#2193672, @cameron.mcinally wrote:

In D85139#2193065, @arsenm wrote:

I think this leaves behind a redundant test_fneg/test_fneg_fmf case elsewhere

You're probably right. Just took a look and I don't see anything obvious though. Did you have a particular set of tests in mind?

I do see some tests that transform an illegal G_FNEG into an G_FSUB. I don't fully understand the motivation yet, but that's probably worth attention.

No, I mean you changed these cases using fsub in the irtranslator test, when there were already tests for fneg here already. LegalizerHelper still does have an incorrect expansion of fneg into fsub, but that's another story

[cameron.mcinally]

Ah, ok. Tests removed with:

commit 724b035fe4df89e807f85ee202da8b0bc227895b (HEAD -> master, origin/master, origin/HEAD)
Author: Cameron McInally <[e-mail]>
Date: Tue Aug 4 11:32:15 2020 -0500

[GlobalISel] Remove redundant FNEG tests.

These tests were made redundant by D85139.

llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

private:
   bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
 
   /// Translate return (ret) instruction.
   /// The target needs to implement CallLowering::lowerReturn for
   /// this to succeed.
   /// \pre \p U is a return instruction.
   bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
 
-  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
-
   bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
 
   bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
   }
   bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
   }
private:
   }
   bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
   }
 
   bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
   }
+  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
+    return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
+  }
   bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
   }
   bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
   }
   bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

if (isa<Instruction>(U)) {
     const Instruction &I = cast<Instruction>(U);
     Flags = MachineInstr::copyFlagsFromInstruction(I);
   }
 
   MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
   return true;
 }
 
-bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
-  // -0.0 - X --> G_FNEG
-  if (isa<Constant>(U.getOperand(0)) &&
-      U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
-    Register Op1 = getOrCreateVReg(*U.getOperand(1));
-    Register Res = getOrCreateVReg(U);
-    uint16_t Flags = 0;
-    if (isa<Instruction>(U)) {
-      const Instruction &I = cast<Instruction>(U);
-      Flags = MachineInstr::copyFlagsFromInstruction(I);
-    }
-    // Negate the last operand of the FSUB
-    MIRBuilder.buildFNeg(Res, Op1, Flags);
-    return true;
-  }
-  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
-}
-
 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
   Register Op0 = getOrCreateVReg(*U.getOperand(0));
   Register Res = getOrCreateVReg(U);
   uint16_t Flags = 0;
   if (isa<Instruction>(U)) {
     const Instruction &I = cast<Instruction>(U);
     Flags = MachineInstr::copyFlagsFromInstruction(I);
   }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr)
   ret void
 }
 
 define float @test_fneg_f32(float %x) {
 ; CHECK-LABEL: name: test_fneg_f32
 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
 ; CHECK: $s0 = COPY [[RES]](s32)
-  %neg = fsub float -0.000000e+00, %x
+  %neg = fneg float %x
   ret float %neg
 }
 
 define float @test_fneg_f32_fmf(float %x) {
 ; CHECK-LABEL: name: test_fneg_f32
 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
 ; CHECK: $s0 = COPY [[RES]](s32)
-  %neg = fsub fast float -0.000000e+00, %x
+  %neg = fneg fast float %x
   ret float %neg
 }
 
 define double @test_fneg_f64(double %x) {
 ; CHECK-LABEL: name: test_fneg_f64
 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
 ; CHECK: $d0 = COPY [[RES]](s64)
-  %neg = fsub double -0.000000e+00, %x
+  %neg = fneg double %x
   ret double %neg
 }
 
 define double @test_fneg_f64_fmf(double %x) {
 ; CHECK-LABEL: name: test_fneg_f64
 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
 ; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
 ; CHECK: $d0 = COPY [[RES]](s64)
-  %neg = fsub fast double -0.000000e+00, %x
+  %neg = fneg fast double %x
   ret double %neg
 }
 
 define void @test_trivial_inlineasm() {
 ; CHECK-LABEL: name: test_trivial_inlineasm
 ; CHECK: INLINEASM &wibble, 1
 ; CHECK: INLINEASM &wibble, 0
   call void asm sideeffect "wibble", ""()