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[WebAssembly] Remove intrinsics for SIMD widening ops

Authored by tlively on Jul 24 2020, 1:54 PM.



Instead, pattern match extends of extract_subvectors to generate
widening operations. Since extract_subvector is not a legal node, this
is implemented via a custom combine that recognizes extract_subvector
nodes before they are legalized. The combine produces custom ISD nodes
that are later pattern matched directly, just like the intrinsic was.

Also removes the clang builtins for these operations since the
instructions can now be generated from portable code sequences.

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tlively created this revision.Jul 24 2020, 1:54 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJul 24 2020, 1:54 PM
srj added a subscriber: srj.Jul 24 2020, 2:24 PM
aheejin accepted this revision.Jul 24 2020, 7:05 PM
aheejin added inline comments.

It'd be clearer to say starting indices of these don't start with 0 or [lanecount - 1] so they can't be widened using widen_low or widen_high instructions.

Question: Can we also widen these using shifts?

This revision is now accepted and ready to land.Jul 24 2020, 7:05 PM
tlively added inline comments.Jul 28 2020, 6:18 PM

Sure, since I didn't end up testing more patterns, I can make the comment more specific.

Regarding shifts, I don't think it's possible to do widening with shifts because widening has to fundamentally change the number of lanes, which shifts can't do.

This revision was landed with ongoing or failed builds.Jul 28 2020, 6:26 PM
This revision was automatically updated to reflect the committed changes.
aheejin added inline comments.Jul 28 2020, 6:55 PM

What I meant was, in case of i16x8->i32x4, the current code can widen i16x8 input vector with elements in the indices 0 to 4. If those elements are instead in 1 to 5, can we first shift that to 0~4 and widen it?

tlively added inline comments.Jul 28 2020, 7:59 PM

Oh gotcha. No, unfortunately I don't think that would work. The SIMD shift instructions shift bytes within lanes but they can't shift data into a different lane. Even if we used shifts on larger lanes to try to overcome that limitation, a 64x2 shift would still not be able to shift data from the high half of the vector to the low half or vice versa, which we would need to do to implement your suggestion.

aheejin added inline comments.Jul 28 2020, 8:16 PM

Ah right... I was confused about SIMD shifts. Thanks.