[ARM] Constant fold VCTP intrinsics

[dmgreen]

Summary

We can sometimes get into the situation where the operand to a vctp intrinsic becomes constant, such as after a loop is fully unrolled. This adds the constant folding needed for them, allowing them to simplify away and hopefully simplifying remaining instructions.

[nikic]

Why is this in InstCombine rather than ConstantFolding?

[dmgreen]

Ah. Sure, I think I can move it there. For some reason I was under the impression that constant folding did not handle target intrinsics, but I see there are some x86 and amd intrinsics in there already.

[dmgreen]

Moved to constant folding.

[SjoerdMeijer]

With this now in ConstantFolding, this looks good to me. Please wait a day in case there are more comments.

[efriedma]

We might want to look at migrating the target-specific code into the target, similar to what we're doing for target-specific intrinsics in instcombine.

llvm/lib/Analysis/ConstantFolding.cpp

2765 ↗

(On Diff #279109)

Are these just ConstantInt::getTrue() and ConstantInt::getFalse()?

[dmgreen]

In D84110#2162902, @efriedma wrote:

We might want to look at migrating the target-specific code into the target, similar to what we're doing for target-specific intrinsics in instcombine.

Yep. Sounds sensible to me. (That's one of the reason's I didn't think ConstantFolding handled target intrinsics). The instcombine side should probably go in first though.

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

assert(II->getArgOperand(CarryOp)->getType()->getScalarSizeInBits() == 32 &&
            "Bad type for intrinsic!");
 
     KnownBits CarryKnown(32);
     if (SimplifyDemandedBits(II, CarryOp, APInt::getOneBitSet(32, 29),
                              CarryKnown))
       return II;
     break;
   }
+  case Intrinsic::arm_mve_vctp8:
+  case Intrinsic::arm_mve_vctp16:
+  case Intrinsic::arm_mve_vctp32:
+  case Intrinsic::arm_mve_vctp64: {
+    Value *DataArg = II->getArgOperand(0);
+    if (auto *C = dyn_cast<ConstantInt>(DataArg)) {
+      unsigned Lanes = cast<FixedVectorType>(II->getType())->getNumElements();
+      uint64_t Limit = C->getZExtValue();
+      // vctp64 are currently modelled as returning a v4i1, not a v2i1. Make
+      // sure we get the limit right in that case and set all relevant lanes.
+      if (II->getIntrinsicID() == Intrinsic::arm_mve_vctp64)
+        Limit *= 2;
+
+      SmallVector<Constant*, 16> NCs;
+      for(unsigned i = 0; i < Lanes; i++) {
+        if (i < Limit)
+          NCs.push_back(ConstantInt::get(Builder.getInt1Ty(), 1));
+        else
+          NCs.push_back(ConstantInt::get(Builder.getInt1Ty(), 0));
+      }
+      return replaceInstUsesWith(*II, ConstantVector::get(NCs));
+    }
+    break;
+  }
   case Intrinsic::amdgcn_rcp: {
     Value *Src = II->getArgOperand(0);
 
     // TODO: Move to ConstantFolding/InstSimplify?
     if (isa<UndefValue>(Src)) {
       Type *Ty = II->getType();
       auto *QNaN = ConstantFP::get(Ty, APFloat::getQNaN(Ty->getFltSemantics()));
       return replaceInstUsesWith(CI, QNaN);

llvm/test/Transforms/InstCombine/ARM/mve-vctp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -instcombine -S -o - %s | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 
 define <16 x i1> @vctp8_0() {
 ; CHECK-LABEL: @vctp8_0(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 0)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> zeroinitializer
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 0)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_1() {
 ; CHECK-LABEL: @vctp8_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 1)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 1)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_8() {
 ; CHECK-LABEL: @vctp8_8(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 8)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 8)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_15() {
 ; CHECK-LABEL: @vctp8_15(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 15)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 15)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_16() {
 ; CHECK-LABEL: @vctp8_16(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 16)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 16)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_100() {
 ; CHECK-LABEL: @vctp8_100(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 100)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 100)
   ret <16 x i1> %int
 }
 
 define <16 x i1> @vctp8_m1() {
 ; CHECK-LABEL: @vctp8_m1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 -1)
-; CHECK-NEXT:    ret <16 x i1> [[INT]]
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 -1)
   ret <16 x i1> %int
 }
 
 
 
 define <8 x i1> @vctp16_0() {
 ; CHECK-LABEL: @vctp16_0(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 0)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> zeroinitializer
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 0)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_1() {
 ; CHECK-LABEL: @vctp16_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 1)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 1)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_4() {
 ; CHECK-LABEL: @vctp16_4(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 4)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 4)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_7() {
 ; CHECK-LABEL: @vctp16_7(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 7)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 7)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_8() {
 ; CHECK-LABEL: @vctp16_8(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 8)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 8)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_100() {
 ; CHECK-LABEL: @vctp16_100(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 100)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 100)
   ret <8 x i1> %int
 }
 
 define <8 x i1> @vctp16_m1() {
 ; CHECK-LABEL: @vctp16_m1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 -1)
-; CHECK-NEXT:    ret <8 x i1> [[INT]]
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 -1)
   ret <8 x i1> %int
 }
 
 
 
 define <4 x i1> @vctp32_0() {
 ; CHECK-LABEL: @vctp32_0(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 0)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 0)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp32_1() {
 ; CHECK-LABEL: @vctp32_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 1)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 1)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp32_3() {
 ; CHECK-LABEL: @vctp32_3(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 3)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 false>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 3)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp32_4() {
 ; CHECK-LABEL: @vctp32_4(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 4)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 4)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp32_100() {
 ; CHECK-LABEL: @vctp32_100(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 100)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 100)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp32_m1() {
 ; CHECK-LABEL: @vctp32_m1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 -1)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 -1)
   ret <4 x i1> %int
 }
 
 
 
 define <4 x i1> @vctp64_0() {
 ; CHECK-LABEL: @vctp64_0(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp64(i32 0)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 0)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp64_1() {
 ; CHECK-LABEL: @vctp64_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp64(i32 1)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 false, i1 false>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 1)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp64_2() {
 ; CHECK-LABEL: @vctp64_2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp64(i32 2)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 2)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp64_100() {
 ; CHECK-LABEL: @vctp64_100(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp64(i32 100)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 100)
   ret <4 x i1> %int
 }
 
 define <4 x i1> @vctp64_m1() {
 ; CHECK-LABEL: @vctp64_m1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.arm.mve.vctp64(i32 -1)
-; CHECK-NEXT:    ret <4 x i1> [[INT]]
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
 ;
 entry:
   %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 -1)
   ret <4 x i1> %int
 }
 
 
 
 declare <4 x i1> @llvm.arm.mve.vctp64(i32)
 declare <4 x i1> @llvm.arm.mve.vctp32(i32)
 declare <8 x i1> @llvm.arm.mve.vctp16(i32)
 declare <16 x i1> @llvm.arm.mve.vctp8(i32)