[ARM] Constant fold VCTP intrinsics

[dmgreen]

Summary

We can sometimes get into the situation where the operand to a vctp intrinsic becomes constant, such as after a loop is fully unrolled. This adds the constant folding needed for them, allowing them to simplify away and hopefully simplifying remaining instructions.

[nikic]

Why is this in InstCombine rather than ConstantFolding?

[dmgreen]

Ah. Sure, I think I can move it there. For some reason I was under the impression that constant folding did not handle target intrinsics, but I see there are some x86 and amd intrinsics in there already.

[dmgreen]

Moved to constant folding.

[SjoerdMeijer]

With this now in ConstantFolding, this looks good to me. Please wait a day in case there are more comments.

[efriedma]

We might want to look at migrating the target-specific code into the target, similar to what we're doing for target-specific intrinsics in instcombine.

llvm/lib/Analysis/ConstantFolding.cpp

2784

Are these just ConstantInt::getTrue() and ConstantInt::getFalse()?

[dmgreen]

In D84110#2162902, @efriedma wrote:

We might want to look at migrating the target-specific code into the target, similar to what we're doing for target-specific intrinsics in instcombine.

Yep. Sounds sensible to me. (That's one of the reason's I didn't think ConstantFolding handled target intrinsics). The instcombine side should probably go in first though.

llvm/lib/Analysis/ConstantFolding.cpp

 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/IR/InstrTypes.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/IR/IntrinsicsX86.h"
 #include "llvm/IR/Operator.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/Value.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
   case Intrinsic::experimental_vector_reduce_mul:
   case Intrinsic::experimental_vector_reduce_and:
   case Intrinsic::experimental_vector_reduce_or:
   case Intrinsic::experimental_vector_reduce_xor:
   case Intrinsic::experimental_vector_reduce_smin:
   case Intrinsic::experimental_vector_reduce_smax:
   case Intrinsic::experimental_vector_reduce_umin:
   case Intrinsic::experimental_vector_reduce_umax:
+  // Target intrinsics
+  case Intrinsic::arm_mve_vctp8:
+  case Intrinsic::arm_mve_vctp16:
+  case Intrinsic::arm_mve_vctp32:
+  case Intrinsic::arm_mve_vctp64:
     return true;
 
   // Floating point operations cannot be folded in strictfp functions in
   // general case. They can be folded if FP environment is known to compiler.
   case Intrinsic::minnum:
   case Intrinsic::maxnum:
   case Intrinsic::minimum:
   case Intrinsic::maximum:
if (isa<ScalableVectorType>(VTy))
     return nullptr;
 
   auto *FVTy = cast<FixedVectorType>(VTy);
 
   SmallVector<Constant *, 4> Result(FVTy->getNumElements());
   SmallVector<Constant *, 4> Lane(Operands.size());
   Type *Ty = FVTy->getElementType();
 
-  if (IntrinsicID == Intrinsic::masked_load) {
+  switch (IntrinsicID) {
+  case Intrinsic::masked_load: {
     auto *SrcPtr = Operands[0];
     auto *Mask = Operands[2];
     auto *Passthru = Operands[3];
 
     Constant *VecData = ConstantFoldLoadFromConstPtr(SrcPtr, FVTy, DL);
 
     SmallVector<Constant *, 32> NewElements;
     for (unsigned I = 0, E = FVTy->getNumElements(); I != E; ++I) {
for (unsigned I = 0, E = FVTy->getNumElements(); I != E; ++I) {
       } else {
         return nullptr;
       }
     }
     if (NewElements.size() != FVTy->getNumElements())
       return nullptr;
     return ConstantVector::get(NewElements);
   }
+  case Intrinsic::arm_mve_vctp8:
+  case Intrinsic::arm_mve_vctp16:
+  case Intrinsic::arm_mve_vctp32:
+  case Intrinsic::arm_mve_vctp64: {
+    if (auto *Op = dyn_cast<ConstantInt>(Operands[0])) {
+      unsigned Lanes = FVTy->getNumElements();
+      uint64_t Limit = Op->getZExtValue();
+      // vctp64 are currently modelled as returning a v4i1, not a v2i1. Make
+      // sure we get the limit right in that case and set all relevant lanes.
+      if (IntrinsicID == Intrinsic::arm_mve_vctp64)
+        Limit *= 2;
+
+      SmallVector<Constant *, 16> NCs;
+      for (unsigned i = 0; i < Lanes; i++) {
+        if (i < Limit)
+          NCs.push_back(ConstantInt::getTrue(Ty));
+        else
+          NCs.push_back(ConstantInt::getFalse(Ty));
+      }
+      return ConstantVector::get(NCs);
+    }
+    break;
+  }
+  default:
+    break;
+  }
 
   for (unsigned I = 0, E = FVTy->getNumElements(); I != E; ++I) {
     // Gather a column of constants.
     for (unsigned J = 0, JE = Operands.size(); J != JE; ++J) {
       // Some intrinsics use a scalar type for certain arguments.
       if (hasVectorInstrinsicScalarOpd(IntrinsicID, J)) {
         Lane[J] = Operands[J];
         continue;

llvm/test/Analysis/ConstantFolding/ARM/lit.local.cfg

+if not 'ARM' in config.root.targets:
+    config.unsupported = True

llvm/test/Analysis/ConstantFolding/ARM/mve-vctp.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instsimplify -S -o - %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+
+define <16 x i1> @vctp8_0() {
+; CHECK-LABEL: @vctp8_0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> zeroinitializer
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 0)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_1() {
+; CHECK-LABEL: @vctp8_1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 1)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_8() {
+; CHECK-LABEL: @vctp8_8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 8)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_15() {
+; CHECK-LABEL: @vctp8_15(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 15)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_16() {
+; CHECK-LABEL: @vctp8_16(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 16)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_100() {
+; CHECK-LABEL: @vctp8_100(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 100)
+  ret <16 x i1> %int
+}
+
+define <16 x i1> @vctp8_m1() {
+; CHECK-LABEL: @vctp8_m1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <16 x i1> @llvm.arm.mve.vctp8(i32 -1)
+  ret <16 x i1> %int
+}
+
+
+
+define <8 x i1> @vctp16_0() {
+; CHECK-LABEL: @vctp16_0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> zeroinitializer
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 0)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_1() {
+; CHECK-LABEL: @vctp16_1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 1)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_4() {
+; CHECK-LABEL: @vctp16_4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 4)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_7() {
+; CHECK-LABEL: @vctp16_7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 7)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_8() {
+; CHECK-LABEL: @vctp16_8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 8)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_100() {
+; CHECK-LABEL: @vctp16_100(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 100)
+  ret <8 x i1> %int
+}
+
+define <8 x i1> @vctp16_m1() {
+; CHECK-LABEL: @vctp16_m1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <8 x i1> @llvm.arm.mve.vctp16(i32 -1)
+  ret <8 x i1> %int
+}
+
+
+
+define <4 x i1> @vctp32_0() {
+; CHECK-LABEL: @vctp32_0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 0)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp32_1() {
+; CHECK-LABEL: @vctp32_1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 1)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp32_3() {
+; CHECK-LABEL: @vctp32_3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 false>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 3)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp32_4() {
+; CHECK-LABEL: @vctp32_4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 4)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp32_100() {
+; CHECK-LABEL: @vctp32_100(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 100)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp32_m1() {
+; CHECK-LABEL: @vctp32_m1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp32(i32 -1)
+  ret <4 x i1> %int
+}
+
+
+
+define <4 x i1> @vctp64_0() {
+; CHECK-LABEL: @vctp64_0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> zeroinitializer
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 0)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp64_1() {
+; CHECK-LABEL: @vctp64_1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 false, i1 false>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 1)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp64_2() {
+; CHECK-LABEL: @vctp64_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 2)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp64_100() {
+; CHECK-LABEL: @vctp64_100(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 100)
+  ret <4 x i1> %int
+}
+
+define <4 x i1> @vctp64_m1() {
+; CHECK-LABEL: @vctp64_m1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %int = call <4 x i1> @llvm.arm.mve.vctp64(i32 -1)
+  ret <4 x i1> %int
+}
+
+
+
+declare <4 x i1> @llvm.arm.mve.vctp64(i32)
+declare <4 x i1> @llvm.arm.mve.vctp32(i32)
+declare <8 x i1> @llvm.arm.mve.vctp16(i32)
+declare <16 x i1> @llvm.arm.mve.vctp8(i32)