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Differential D84101

[ARM] Add predicated add reduction patterns
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Authored by dmgreen on Jul 18 2020, 7:53 AM.

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Reviewers
SjoerdMeijer
samparker
efriedma
simon_tatham
ostannard
Commits
rG8fa824d7a36d: [ARM] Add predicated add reduction patterns
Summary

Given a vecreduce.add(select(p, x, 0)), we can convert that to a predicated vaddv, as the negative value for the select is the identity value, a zero. That is what this patch does for the vaddv, vaddva, vaddlv and vaddlva instruction, copying the existing patterns to also handle predication through a select.

Diff Detail

Event Timeline

dmgreen created this revision.Jul 18 2020, 7:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2020, 7:53 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen mentioned this in D84102: [ARM] Add predicated mla reduction patterns.Jul 18 2020, 7:58 AM
dmgreen added a child revision: D84102: [ARM] Add predicated mla reduction patterns.
dmgreen added a parent revision: D84091: [ARM] Extra MVE select(binop) patterns.
simon_tatham accepted this revision.Jul 20 2020, 5:29 AM
This revision is now accepted and ready to land.Jul 20 2020, 5:29 AM
Closed by commit rG8fa824d7a36d: [ARM] Add predicated add reduction patterns (authored by dmgreen). · Explain WhyJul 22 2020, 9:30 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
12 lines
26 lines
24 lines
test/
CodeGen/
Thumb2/
1062 lines
170 lines

Diff 279003

llvm/lib/Target/ARM/ARMISelLowering.h

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines enum NodeType : unsigned {
// Vector multiply long: // Vector multiply long:
VMULLs, // ...signed VMULLs, // ...signed
VMULLu, // ...unsigned VMULLu, // ...unsigned
// MVE reductions // MVE reductions
VADDVs, // sign- or zero-extend the elements of a vector to i32, VADDVs, // sign- or zero-extend the elements of a vector to i32,
VADDVu, // add them all together, and return an i32 of their sum VADDVu, // add them all together, and return an i32 of their sum
VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
VADDVpu,
VADDLVs, // sign- or zero-extend elements to i64 and sum, returning VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
VADDLVu, // the low and high 32-bit halves of the sum VADDLVu, // the low and high 32-bit halves of the sum
VADDLVAs, // same as VADDLV[su] but also add an input accumulator VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
VADDLVAu, // provided as low and high halves VADDLVAu, // provided as low and high halves
VADDLVps, // same as VADDLVs but with a v4i1 predicate mask VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
VADDLVpu, // same as VADDLVu but with a v4i1 predicate mask VADDLVpu,
VADDLVAps, // same as VADDLVps but with a v4i1 predicate mask VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
VADDLVApu, // same as VADDLVpu but with a v4i1 predicate mask VADDLVApu,
VMLAVs, VMLAVs,
VMLAVu, VMLAVu,
VMLALVs, VMLALVs,
VMLALVu, VMLALVu,
VMLALVAs, VMLALVAs,
VMLALVAu, VMLALVAu,
SMULWB, // Signed multiply word by half word, bottom SMULWB, // Signed multiply word by half word, bottom
▲ Show 20 Lines • Show All 691 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,712 Lines • ▼ Show 20 Linesconst char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::VQMOVNs: return "ARMISD::VQMOVNs"; case ARMISD::VQMOVNs: return "ARMISD::VQMOVNs";
case ARMISD::VQMOVNu: return "ARMISD::VQMOVNu"; case ARMISD::VQMOVNu: return "ARMISD::VQMOVNu";
case ARMISD::VCVTN: return "ARMISD::VCVTN"; case ARMISD::VCVTN: return "ARMISD::VCVTN";
case ARMISD::VCVTL: return "ARMISD::VCVTL"; case ARMISD::VCVTL: return "ARMISD::VCVTL";
case ARMISD::VMULLs: return "ARMISD::VMULLs"; case ARMISD::VMULLs: return "ARMISD::VMULLs";
case ARMISD::VMULLu: return "ARMISD::VMULLu"; case ARMISD::VMULLu: return "ARMISD::VMULLu";
case ARMISD::VADDVs: return "ARMISD::VADDVs"; case ARMISD::VADDVs: return "ARMISD::VADDVs";
case ARMISD::VADDVu: return "ARMISD::VADDVu"; case ARMISD::VADDVu: return "ARMISD::VADDVu";
case ARMISD::VADDVps: return "ARMISD::VADDVps";
case ARMISD::VADDVpu: return "ARMISD::VADDVpu";
case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
case ARMISD::VADDLVu: return "ARMISD::VADDLVu"; case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs"; case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu"; case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu";
case ARMISD::VADDLVps: return "ARMISD::VADDLVps"; case ARMISD::VADDLVps: return "ARMISD::VADDLVps";
case ARMISD::VADDLVpu: return "ARMISD::VADDLVpu"; case ARMISD::VADDLVpu: return "ARMISD::VADDLVpu";
case ARMISD::VADDLVAps: return "ARMISD::VADDLVAps"; case ARMISD::VADDLVAps: return "ARMISD::VADDLVAps";
case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu"; case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu";
▲ Show 20 Lines • Show All 12,995 Lines • ▼ Show 20 Linesstatic SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
auto IsVADDV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef<MVT> ExtTypes) { auto IsVADDV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef<MVT> ExtTypes) {
if (ResVT != RetTy || N0->getOpcode() != ExtendCode) if (ResVT != RetTy || N0->getOpcode() != ExtendCode)
return SDValue(); return SDValue();
SDValue A = N0->getOperand(0); SDValue A = N0->getOperand(0);
if (llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; })) if (llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; }))
return A; return A;
return SDValue(); return SDValue();
}; };
auto IsPredVADDV = [&](MVT RetTy, unsigned ExtendCode,
ArrayRef<MVT> ExtTypes, SDValue &Mask) {
if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||
!ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode()))
return SDValue();
Mask = N0->getOperand(0);
SDValue Ext = N0->getOperand(1);
if (Ext->getOpcode() != ExtendCode)
return SDValue();
SDValue A = Ext->getOperand(0);
if (llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; }))
return A;
return SDValue();
};
auto IsVMLAV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef<MVT> ExtTypes, auto IsVMLAV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef<MVT> ExtTypes,
SDValue &A, SDValue &B) { SDValue &A, SDValue &B) {
if (ResVT != RetTy || N0->getOpcode() != ISD::MUL) if (ResVT != RetTy || N0->getOpcode() != ISD::MUL)
return false; return false;
SDValue ExtA = N0->getOperand(0); SDValue ExtA = N0->getOperand(0);
SDValue ExtB = N0->getOperand(1); SDValue ExtB = N0->getOperand(1);
if (ExtA->getOpcode() != ExtendCode && ExtB->getOpcode() != ExtendCode) if (ExtA->getOpcode() != ExtendCode && ExtB->getOpcode() != ExtendCode)
return false; return false;
Show All 14 Lines if (SDValue A = IsVADDV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}))
return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A);
if (SDValue A = IsVADDV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8})) if (SDValue A = IsVADDV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}))
return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A); return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A);
if (SDValue A = IsVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32})) if (SDValue A = IsVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32}))
return Create64bitNode(ARMISD::VADDLVs, {A}); return Create64bitNode(ARMISD::VADDLVs, {A});
if (SDValue A = IsVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32})) if (SDValue A = IsVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}))
return Create64bitNode(ARMISD::VADDLVu, {A}); return Create64bitNode(ARMISD::VADDLVu, {A});
SDValue Mask;
if (SDValue A = IsPredVADDV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask))
return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);
if (SDValue A = IsPredVADDV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask))
return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);
if (SDValue A = IsPredVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32}, Mask))
return Create64bitNode(ARMISD::VADDLVps, {A, Mask});
if (SDValue A = IsPredVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}, Mask))
return Create64bitNode(ARMISD::VADDLVpu, {A, Mask});
SDValue A, B; SDValue A, B;
if (IsVMLAV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B)) if (IsVMLAV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B))
return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B); return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);
if (IsVMLAV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B)) if (IsVMLAV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B))
return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B); return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B);
if (IsVMLAV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B)) if (IsVMLAV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B))
return Create64bitNode(ARMISD::VMLALVs, {A, B}); return Create64bitNode(ARMISD::VMLALVs, {A, B});
if (IsVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B)) if (IsVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B))
▲ Show 20 Lines • Show All 4,164 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 704 Lines • ▼ Show 20 Linesclass MVE_VADDV<string iname, string suffix, dag iops, string cstr,
let Inst{8-6} = 0b100; let Inst{8-6} = 0b100;
let Inst{5} = A; let Inst{5} = A;
let Inst{3-1} = Qm{2-0}; let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0; let Inst{0} = 0b0;
let horizontalReduction = 1; let horizontalReduction = 1;
let validForTailPredication = 1; let validForTailPredication = 1;
} }
def SDTVecReduceP : SDTypeProfile<1, 2, [ // VADDLVp
SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>
]>;
def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>; def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
def ARMVADDVu : SDNode<"ARMISD::VADDVu", SDTVecReduce>; def ARMVADDVu : SDNode<"ARMISD::VADDVu", SDTVecReduce>;
def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
def ARMVADDVpu : SDNode<"ARMISD::VADDVpu", SDTVecReduceP>;
multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> { multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> {
def acc : MVE_VADDV<"vaddva", VTI.Suffix, def acc : MVE_VADDV<"vaddva", VTI.Suffix,
(ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src", (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
0b1, VTI.Unsigned, VTI.Size>; 0b1, VTI.Unsigned, VTI.Size>;
def no_acc : MVE_VADDV<"vaddv", VTI.Suffix, def no_acc : MVE_VADDV<"vaddv", VTI.Suffix,
(ins MQPR:$Qm), "", (ins MQPR:$Qm), "",
0b0, VTI.Unsigned, VTI.Size>; 0b0, VTI.Unsigned, VTI.Size>;
defvar InstA = !cast<Instruction>(NAME # "acc"); defvar InstA = !cast<Instruction>(NAME # "acc");
defvar InstN = !cast<Instruction>(NAME # "no_acc"); defvar InstN = !cast<Instruction>(NAME # "no_acc");
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
if VTI.Unsigned then { if VTI.Unsigned then {
def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))), def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$vec),
(VTI.Vec MVEimmAllZerosV))))),
(i32 (InstN $vec, ARMVCCThen, $pred))>;
def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>;
def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$vec),
(VTI.Vec MVEimmAllZerosV))))),
(i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
} else { } else {
def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>;
def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
} }
def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec), def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>; (i32 (InstN $vec, ARMVCCThen, $pred))>;
def : Pat<(i32 (add (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec), def : Pat<(i32 (add (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
▲ Show 20 Lines • Show All 6,453 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) { define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i32: ; CHECK-LABEL: add_v4i32_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %b) { define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i64_zext: ; CHECK-LABEL: add_v4i32_v4i64_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.f32 s12, s0 ; CHECK-NEXT: vaddlvt.u32 r0, r1, q0
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q3, q3, q2
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vand q0, q1, q2
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsb.w r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: rsb.w r0, r0, #0
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: adc.w r2, r2, r12
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: adcs r2, r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: adds r0, r0, r1
; CHECK-NEXT: adc.w r1, r2, r3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%xx = zext <4 x i32> %x to <4 x i64> %xx = zext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %b) { define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i64_sext: ; CHECK-LABEL: add_v4i32_v4i64_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s12, s0 ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vaddlvt.s32 r0, r1, q0
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: asrs r0, r0, #31
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: and r1, r0, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: ubfx r1, r0, #4, #1
; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: adds r1, r1, r2
; CHECK-NEXT: adc.w r2, r3, r12
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q0[3], r3
; CHECK-NEXT: ubfx r3, r0, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r0, r0, #12, #1
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: adcs r2, r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: adds r0, r0, r1
; CHECK-NEXT: adc.w r1, r2, r3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%xx = sext <4 x i32> %x to <4 x i64> %xx = sext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
ret i64 %z ret i64 %z
} }
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Linesentry:
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_zext: ; CHECK-LABEL: add_v8i16_v8i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q4, #0xffff
; CHECK-NEXT: vpsel q1, q3, q2
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q2, q3, q4
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmovlb.u16 q0, q1
; CHECK-NEXT: vpt.i32 ne, q3, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vaddv.u32 r0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = zext <8 x i16> %x to <8 x i32> %xx = zext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_sext: ; CHECK-LABEL: add_v8i16_v8i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i8 q3, #0xff ; CHECK-NEXT: vaddvt.s16 r0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vpsel q1, q3, q2
; CHECK-NEXT: vmov.i32 q3, #0x0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vpsel q2, q2, q3
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmovlb.s16 q0, q1
; CHECK-NEXT: vpt.i32 ne, q3, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vaddv.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_zext: ; CHECK-LABEL: add_v4i16_v4i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmov.i32 q2, #0xffff ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q2
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = zext <4 x i16> %x to <4 x i32> %xx = zext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_sext: ; CHECK-LABEL: add_v4i16_v4i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = sext <4 x i16> %x to <4 x i32> %xx = sext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b) { define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i16: ; CHECK-LABEL: add_v8i16_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
} }
▲ Show 20 Lines • Show All 345 Lines • ▼ Show 20 Linesentry:
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer %s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i32_zext: ; CHECK-LABEL: add_v16i8_v16i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q5, #0xff
; CHECK-NEXT: vpsel q7, q5, q0
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.u8 r0, q7[0]
; CHECK-NEXT: vmov.i32 q6, #0xff
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q7[1]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q7[2]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q7[3]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q7[4]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q7[5]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q7[6]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q7[7]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: vpsel q4, q5, q0
; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q2[4]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q2[5]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q2[6]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q2[7]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q7[8]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q3, q0, q6
; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q7[9]
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q7[10]
; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q7[11]
; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q7[12]
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u8 r0, q7[13]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u8 r0, q7[14]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u8 r0, q7[15]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vcmp.i16 ne, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vpsel q5, q5, q0
; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[6]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q2[12]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q2[14]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q2[15]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vand q0, q0, q6
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q3, q3, q0
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q2[0]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q2[3]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[0]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q6
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q5[1]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vmov.u8 r0, q2[8]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q2[9]
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q2[11]
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: vand q0, q0, q6
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q1, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q3
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = zext <16 x i8> %x to <16 x i32> %xx = zext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i32_sext: ; CHECK-LABEL: add_v16i8_v16i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vaddvt.s8 r0, q0
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q3, #0x0
; CHECK-NEXT: vmov.i8 q5, #0xff
; CHECK-NEXT: vmov.i32 q4, #0x0
; CHECK-NEXT: vpsel q6, q5, q3
; CHECK-NEXT: vmov.u8 r0, q6[0]
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q6[1]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q6[2]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q6[3]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q6[4]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q6[5]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q6[6]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q6[7]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vpsel q2, q5, q3
; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q6[8]
; CHECK-NEXT: vmov.16 q7[0], r0
; CHECK-NEXT: vmov.u8 r0, q6[9]
; CHECK-NEXT: vmov.16 q7[1], r0
; CHECK-NEXT: vmov.u8 r0, q6[10]
; CHECK-NEXT: vmov.16 q7[2], r0
; CHECK-NEXT: vmov.u8 r0, q6[11]
; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov.u8 r0, q6[12]
; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.u8 r0, q6[13]
; CHECK-NEXT: vmov.16 q7[5], r0
; CHECK-NEXT: vmov.u8 r0, q6[14]
; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmov.16 q7[6], r0
; CHECK-NEXT: vmov.u8 r0, q6[15]
; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmov.16 q7[7], r0
; CHECK-NEXT: vpsel q1, q1, q4
; CHECK-NEXT: vcmp.i16 ne, q7, zr
; CHECK-NEXT: vpsel q3, q5, q3
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vcmp.i32 ne, q5, zr
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmovlb.s8 q5, q5
; CHECK-NEXT: vmovlb.s16 q5, q5
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q1, q1, q5
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vcmp.i32 ne, q5, zr
; CHECK-NEXT: vmovlb.s8 q2, q2
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vpsel q2, q2, q4
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmovlb.s8 q0, q3
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpt.i32 ne, q4, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vadd.i32 q0, q2, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i32> %xx = sext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_zext: ; CHECK-LABEL: add_v4i8_v4i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q2
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = zext <4 x i8> %x to <4 x i32> %xx = zext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_sext: ; CHECK-LABEL: add_v4i8_v4i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = sext <4 x i8> %x to <4 x i32> %xx = sext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Linesentry:
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer %s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %b) { define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_zext: ; CHECK-LABEL: add_v8i8_v8i16_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = zext <8 x i8> %x to <8 x i16> %xx = zext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %b) { define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_sext: ; CHECK-LABEL: add_v8i8_v8i16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = sext <8 x i8> %x to <8 x i16> %xx = sext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) { define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i8: ; CHECK-LABEL: add_v16i8_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i8 eq, q1, zr ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s) %z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
ret i8 %z ret i8 %z
} }
▲ Show 20 Lines • Show All 690 Lines • ▼ Show 20 Linesentry:
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %b, i32 %a) {
; CHECK-LABEL: add_v4i32_v4i32_acc: ; CHECK-LABEL: add_v4i32_v4i32_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, <4 x i32> %b, i64 %a) { define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, <4 x i32> %b, i64 %a) {
; CHECK-LABEL: add_v4i32_v4i64_acc_zext: ; CHECK-LABEL: add_v4i32_v4i64_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: vaddlvat.u32 r0, r1, q0
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: bx lr
; CHECK-NEXT: vmov.f32 s12, s0
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vand q3, q3, q2
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[2], r3
; CHECK-NEXT: vmov.32 q1[3], r3
; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: vmov lr, s5
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vand q0, q1, q2
; CHECK-NEXT: adds r5, r4, r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsb.w r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: rsb.w r2, r2, #0
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: adc.w r4, lr, r12
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r3, r3, r5
; CHECK-NEXT: vmov r5, s3
; CHECK-NEXT: adcs r2, r4
; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: adcs r2, r5
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%xx = zext <4 x i32> %x to <4 x i64> %xx = zext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, <4 x i32> %b, i64 %a) { define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, <4 x i32> %b, i64 %a) {
; CHECK-LABEL: add_v4i32_v4i64_acc_sext: ; CHECK-LABEL: add_v4i32_v4i64_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: vaddlvat.s32 r0, r1, q0
; CHECK-NEXT: vmov.f32 s12, s0 ; CHECK-NEXT: bx lr
; CHECK-NEXT: vcmp.i32 eq, q1, zr
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: vmov.32 q2[2], r2
; CHECK-NEXT: asrs r2, r2, #31
; CHECK-NEXT: vmov.32 q2[3], r2
; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: vmov.32 q1[2], r3
; CHECK-NEXT: vmov.32 q1[3], r3
; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: vmov r5, s5
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: adds.w lr, r4, r3
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: adc.w r12, r12, r5
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: vmov.32 q0[3], r3
; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov.32 q1[1], r3
; CHECK-NEXT: vmov.32 q1[2], r2
; CHECK-NEXT: vmov.32 q1[3], r2
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: vmov r5, s3
; CHECK-NEXT: adds.w r3, r3, lr
; CHECK-NEXT: adc.w r2, r2, r12
; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: adcs r2, r5
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%xx = sext <4 x i32> %x to <4 x i64> %xx = sext <4 x i32> %x to <4 x i64>
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer %s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linesentry:
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, <8 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, <8 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v8i16_v8i32_acc_zext: ; CHECK-LABEL: add_v8i16_v8i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q4, #0xffff
; CHECK-NEXT: vpsel q1, q3, q2
; CHECK-NEXT: vmov.u16 r1, q1[0]
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[2]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[3]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[2]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[3]
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q2, q3, q4
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[6]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[7]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmovlb.u16 q0, q1
; CHECK-NEXT: vpt.i32 ne, q3, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vaddva.u32 r0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = zext <8 x i16> %x to <8 x i32> %xx = zext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, <8 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, <8 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v8i16_v8i32_acc_sext: ; CHECK-LABEL: add_v8i16_v8i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i8 q3, #0xff ; CHECK-NEXT: vaddvat.s16 r0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr
; CHECK-NEXT: vpsel q1, q3, q2
; CHECK-NEXT: vmov.i32 q3, #0x0
; CHECK-NEXT: vmov.u16 r1, q1[0]
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[2]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[3]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vcmp.i32 ne, q2, zr
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vpsel q2, q2, q3
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u16 r1, q1[6]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u16 r1, q1[7]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmovlb.s16 q0, q1
; CHECK-NEXT: vpt.i32 ne, q3, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vaddva.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32> %xx = sext <8 x i16> %x to <8 x i32>
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer %s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v4i16_v4i32_acc_zext: ; CHECK-LABEL: add_v4i16_v4i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmov.i32 q2, #0xffff ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q2
; CHECK-NEXT: vaddva.u32 r0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = zext <4 x i16> %x to <4 x i32> %xx = zext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v4i16_v4i32_acc_sext: ; CHECK-LABEL: add_v4i16_v4i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = sext <4 x i16> %x to <4 x i32> %xx = sext <4 x i16> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %b, i16 %a) { define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %b, i16 %a) {
; CHECK-LABEL: add_v8i16_v8i16_acc: ; CHECK-LABEL: add_v8i16_v8i16_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Linesentry:
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
%r = add i64 %z, %a %r = add i64 %z, %a
ret i64 %r ret i64 %r
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, <16 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, <16 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i32_acc_zext: ; CHECK-LABEL: add_v16i8_v16i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vaddvat.u8 r0, q0
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q5, #0xff
; CHECK-NEXT: vpsel q7, q5, q0
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.u8 r1, q7[0]
; CHECK-NEXT: vmov.i32 q6, #0xff
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmov.u8 r1, q7[1]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov.u8 r1, q7[2]
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov.u8 r1, q7[3]
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q7[4]
; CHECK-NEXT: vmov.16 q1[4], r1
; CHECK-NEXT: vmov.u8 r1, q7[5]
; CHECK-NEXT: vmov.16 q1[5], r1
; CHECK-NEXT: vmov.u8 r1, q7[6]
; CHECK-NEXT: vmov.16 q1[6], r1
; CHECK-NEXT: vmov.u8 r1, q7[7]
; CHECK-NEXT: vmov.16 q1[7], r1
; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: vpsel q4, q5, q0
; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vmov.u16 r1, q4[4]
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q4[5]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q4[6]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q4[7]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q2[4]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q2[5]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q2[6]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q2[7]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q7[8]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q3, q0, q6
; CHECK-NEXT: vmov.16 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q7[9]
; CHECK-NEXT: vmov.16 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q7[10]
; CHECK-NEXT: vmov.16 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q7[11]
; CHECK-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q7[12]
; CHECK-NEXT: vmov.16 q0[4], r1
; CHECK-NEXT: vmov.u8 r1, q7[13]
; CHECK-NEXT: vmov.16 q0[5], r1
; CHECK-NEXT: vmov.u8 r1, q7[14]
; CHECK-NEXT: vmov.16 q0[6], r1
; CHECK-NEXT: vmov.u8 r1, q7[15]
; CHECK-NEXT: vmov.16 q0[7], r1
; CHECK-NEXT: vcmp.i16 ne, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vpsel q5, q5, q0
; CHECK-NEXT: vmov.u16 r1, q5[4]
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q5[5]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q5[6]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q5[7]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q2[12]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q2[13]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q2[14]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q2[15]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u16 r1, q4[0]
; CHECK-NEXT: vand q0, q0, q6
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q3, q3, q0
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q4[1]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q4[2]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q4[3]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q2[0]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q2[1]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q2[2]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q2[3]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u16 r1, q5[0]
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q6
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u16 r1, q5[1]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u16 r1, q5[2]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u16 r1, q5[3]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vmov.u8 r1, q2[8]
; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.u8 r1, q2[9]
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.u8 r1, q2[10]
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vmov.u8 r1, q2[11]
; CHECK-NEXT: vmov.32 q0[3], r1
; CHECK-NEXT: vand q0, q0, q6
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q1, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q3
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = zext <16 x i8> %x to <16 x i32> %xx = zext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, <16 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, <16 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i32_acc_sext: ; CHECK-LABEL: add_v16i8_v16i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vaddvat.s8 r0, q0
; CHECK-NEXT: vcmp.i8 eq, q1, zr
; CHECK-NEXT: vmov.i8 q3, #0x0
; CHECK-NEXT: vmov.i8 q5, #0xff
; CHECK-NEXT: vmov.i32 q4, #0x0
; CHECK-NEXT: vpsel q6, q5, q3
; CHECK-NEXT: vmov.u8 r1, q6[0]
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmov.u8 r1, q6[1]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov.u8 r1, q6[2]
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov.u8 r1, q6[3]
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q6[4]
; CHECK-NEXT: vmov.16 q1[4], r1
; CHECK-NEXT: vmov.u8 r1, q6[5]
; CHECK-NEXT: vmov.16 q1[5], r1
; CHECK-NEXT: vmov.u8 r1, q6[6]
; CHECK-NEXT: vmov.16 q1[6], r1
; CHECK-NEXT: vmov.u8 r1, q6[7]
; CHECK-NEXT: vmov.16 q1[7], r1
; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vpsel q2, q5, q3
; CHECK-NEXT: vmov.u16 r1, q2[4]
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u16 r1, q2[5]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u16 r1, q2[6]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u16 r1, q2[7]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[4]
; CHECK-NEXT: vcmp.i32 ne, q1, zr
; CHECK-NEXT: vmov.32 q1[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[5]
; CHECK-NEXT: vmov.32 q1[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[6]
; CHECK-NEXT: vmov.32 q1[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[7]
; CHECK-NEXT: vmov.32 q1[3], r1
; CHECK-NEXT: vmov.u8 r1, q6[8]
; CHECK-NEXT: vmov.16 q7[0], r1
; CHECK-NEXT: vmov.u8 r1, q6[9]
; CHECK-NEXT: vmov.16 q7[1], r1
; CHECK-NEXT: vmov.u8 r1, q6[10]
; CHECK-NEXT: vmov.16 q7[2], r1
; CHECK-NEXT: vmov.u8 r1, q6[11]
; CHECK-NEXT: vmov.16 q7[3], r1
; CHECK-NEXT: vmov.u8 r1, q6[12]
; CHECK-NEXT: vmov.16 q7[4], r1
; CHECK-NEXT: vmov.u8 r1, q6[13]
; CHECK-NEXT: vmov.16 q7[5], r1
; CHECK-NEXT: vmov.u8 r1, q6[14]
; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmov.16 q7[6], r1
; CHECK-NEXT: vmov.u8 r1, q6[15]
; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmov.16 q7[7], r1
; CHECK-NEXT: vpsel q1, q1, q4
; CHECK-NEXT: vcmp.i16 ne, q7, zr
; CHECK-NEXT: vpsel q3, q5, q3
; CHECK-NEXT: vmov.u16 r1, q3[4]
; CHECK-NEXT: vmov.32 q5[0], r1
; CHECK-NEXT: vmov.u16 r1, q3[5]
; CHECK-NEXT: vmov.32 q5[1], r1
; CHECK-NEXT: vmov.u16 r1, q3[6]
; CHECK-NEXT: vmov.32 q5[2], r1
; CHECK-NEXT: vmov.u16 r1, q3[7]
; CHECK-NEXT: vmov.32 q5[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[12]
; CHECK-NEXT: vcmp.i32 ne, q5, zr
; CHECK-NEXT: vmov.32 q5[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[13]
; CHECK-NEXT: vmov.32 q5[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[14]
; CHECK-NEXT: vmov.32 q5[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[15]
; CHECK-NEXT: vmov.32 q5[3], r1
; CHECK-NEXT: vmov.u16 r1, q2[0]
; CHECK-NEXT: vmovlb.s8 q5, q5
; CHECK-NEXT: vmovlb.s16 q5, q5
; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i32 q1, q1, q5
; CHECK-NEXT: vmov.32 q5[0], r1
; CHECK-NEXT: vmov.u16 r1, q2[1]
; CHECK-NEXT: vmov.32 q5[1], r1
; CHECK-NEXT: vmov.u16 r1, q2[2]
; CHECK-NEXT: vmov.32 q5[2], r1
; CHECK-NEXT: vmov.u16 r1, q2[3]
; CHECK-NEXT: vmov.32 q5[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[0]
; CHECK-NEXT: vmov.32 q2[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[1]
; CHECK-NEXT: vmov.32 q2[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[2]
; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[3]
; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vcmp.i32 ne, q5, zr
; CHECK-NEXT: vmovlb.s8 q2, q2
; CHECK-NEXT: vmov.u16 r1, q3[0]
; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vpsel q2, q2, q4
; CHECK-NEXT: vmov.32 q4[0], r1
; CHECK-NEXT: vmov.u16 r1, q3[1]
; CHECK-NEXT: vmov.32 q4[1], r1
; CHECK-NEXT: vmov.u16 r1, q3[2]
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.u16 r1, q3[3]
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[8]
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[9]
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[10]
; CHECK-NEXT: vmov.32 q3[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[11]
; CHECK-NEXT: vmov.32 q3[3], r1
; CHECK-NEXT: vmovlb.s8 q0, q3
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpt.i32 ne, q4, zr
; CHECK-NEXT: vaddt.i32 q2, q2, q0
; CHECK-NEXT: vadd.i32 q0, q2, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i32> %xx = sext <16 x i8> %x to <16 x i32>
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer %s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v4i8_v4i32_acc_zext: ; CHECK-LABEL: add_v4i8_v4i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q1, q0, q2
; CHECK-NEXT: vaddva.u32 r0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = zext <4 x i8> %x to <4 x i32> %xx = zext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v4i8_v4i32_acc_sext: ; CHECK-LABEL: add_v4i8_v4i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.i32 q2, #0xff
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q1, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = sext <4 x i8> %x to <4 x i32> %xx = sext <4 x i8> %x to <4 x i32>
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Linesentry:
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %b, i16 %a) { define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %b, i16 %a) {
; CHECK-LABEL: add_v8i8_v8i16_acc_zext: ; CHECK-LABEL: add_v8i8_v8i16_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = zext <8 x i8> %x to <8 x i16> %xx = zext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %b, i16 %a) { define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %b, i16 %a) {
; CHECK-LABEL: add_v8i8_v8i16_acc_sext: ; CHECK-LABEL: add_v8i8_v8i16_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vcmp.i16 eq, q1, zr ; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = sext <8 x i8> %x to <8 x i16> %xx = sext <8 x i8> %x to <8 x i16>
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %b, i8 %a) { define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %b, i8 %a) {
; CHECK-LABEL: add_v16i8_v16i8_acc: ; CHECK-LABEL: add_v16i8_v16i8_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.i8 eq, q1, zr ; CHECK-NEXT: vpt.i8 eq, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vaddvat.u8 r0, q0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s) %z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
%r = add i8 %z, %a %r = add i8 %z, %a
ret i8 %r ret i8 %r
▲ Show 20 Lines • Show All 729 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) { define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) {
; CHECK-LABEL: add_v4i32_v4i32: ; CHECK-LABEL: add_v4i32_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vpt.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q2, zr
; CHECK-NEXT: vmult.i32 q3, q0, q1 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vaddv.u32 r0, q3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%m = mul <4 x i32> %x, %y %m = mul <4 x i32> %x, %y
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
▲ Show 20 Lines • Show All 357 Lines • ▼ Show 20 Linesentry:
%s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer %s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_zext: ; CHECK-LABEL: add_v4i16_v4i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q2, q2 ; CHECK-NEXT: vmullb.u16 q0, q0, q1
; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q2
; CHECK-NEXT: vcmp.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q2, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = zext <4 x i16> %x to <4 x i32> %xx = zext <4 x i16> %x to <4 x i32>
%yy = zext <4 x i16> %y to <4 x i32> %yy = zext <4 x i16> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) {
; CHECK-LABEL: add_v4i16_v4i32_sext: ; CHECK-LABEL: add_v4i16_v4i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q2, q2 ; CHECK-NEXT: vmullb.s16 q0, q0, q1
; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q2
; CHECK-NEXT: vcmp.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q2, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = sext <4 x i16> %x to <4 x i32> %xx = sext <4 x i16> %x to <4 x i32>
%yy = sext <4 x i16> %y to <4 x i32> %yy = sext <4 x i16> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i16: ; CHECK-LABEL: add_v8i16_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i16 q0, q0, q1
; CHECK-NEXT: vpt.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q2, zr
; CHECK-NEXT: vmult.i16 q3, q0, q1 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vaddv.u16 r0, q3
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%m = mul <8 x i16> %x, %y %m = mul <8 x i16> %x, %y
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
▲ Show 20 Lines • Show All 845 Lines • ▼ Show 20 Linesentry:
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_zext: ; CHECK-LABEL: add_v4i8_v4i32_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vmov.i32 q3, #0xff
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vcmp.i32 eq, q2, zr
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vand q0, q0, q3 ; CHECK-NEXT: vand q0, q0, q3
; CHECK-NEXT: vpst ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vmult.i32 q2, q0, q1 ; CHECK-NEXT: vand q1, q2, q3
; CHECK-NEXT: vaddv.u32 r0, q2 ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = zext <4 x i8> %x to <4 x i32> %xx = zext <4 x i8> %x to <4 x i32>
%yy = zext <4 x i8> %y to <4 x i32> %yy = zext <4 x i8> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
ret i32 %z ret i32 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) {
; CHECK-LABEL: add_v4i8_v4i32_sext: ; CHECK-LABEL: add_v4i8_v4i32_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0xff
; CHECK-NEXT: vmovlb.s8 q1, q1 ; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q2, zr
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpst ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vmult.i32 q2, q0, q1 ; CHECK-NEXT: vmov.i32 q1, #0xff
; CHECK-NEXT: vaddv.u32 r0, q2 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvt.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = sext <4 x i8> %x to <4 x i32> %xx = sext <4 x i8> %x to <4 x i32>
%yy = sext <4 x i8> %y to <4 x i32> %yy = sext <4 x i8> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesentry:
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer %s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_zext: ; CHECK-LABEL: add_v8i8_v8i16_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q2, q2 ; CHECK-NEXT: vmullb.u8 q0, q0, q1
; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q1, q2
; CHECK-NEXT: vcmp.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q2, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q2
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = zext <8 x i8> %x to <8 x i16> %xx = zext <8 x i8> %x to <8 x i16>
%yy = zext <8 x i8> %y to <8 x i16> %yy = zext <8 x i8> %y to <8 x i16>
%m = mul <8 x i16> %xx, %yy %m = mul <8 x i16> %xx, %yy
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) {
; CHECK-LABEL: add_v8i8_v8i16_sext: ; CHECK-LABEL: add_v8i8_v8i16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q2, q2 ; CHECK-NEXT: vmullb.s8 q0, q0, q1
; CHECK-NEXT: vmovlb.s8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q1, q2
; CHECK-NEXT: vcmp.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvt.u16 r0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q2, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q2
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = sext <8 x i8> %x to <8 x i16> %xx = sext <8 x i8> %x to <8 x i16>
%yy = sext <8 x i8> %y to <8 x i16> %yy = sext <8 x i8> %y to <8 x i16>
%m = mul <8 x i16> %xx, %yy %m = mul <8 x i16> %xx, %yy
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
ret i16 %z ret i16 %z
} }
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i8: ; CHECK-LABEL: add_v16i8_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i8 q0, q0, q1
; CHECK-NEXT: vpt.i8 eq, q2, zr ; CHECK-NEXT: vpt.i8 eq, q2, zr
; CHECK-NEXT: vmult.i8 q3, q0, q1 ; CHECK-NEXT: vaddvt.u8 r0, q0
; CHECK-NEXT: vaddv.u8 r0, q3
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%m = mul <16 x i8> %x, %y %m = mul <16 x i8> %x, %y
%s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer %s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s) %z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
ret i8 %z ret i8 %z
▲ Show 20 Lines • Show All 908 Lines • ▼ Show 20 Linesentry:
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer %s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s) %z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
ret i64 %z ret i64 %z
} }
define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i32 %a) {
; CHECK-LABEL: add_v4i32_v4i32_acc: ; CHECK-LABEL: add_v4i32_v4i32_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vpt.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q2, zr
; CHECK-NEXT: vmult.i32 q3, q0, q1 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vaddva.u32 r0, q3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %b, zeroinitializer %c = icmp eq <4 x i32> %b, zeroinitializer
%m = mul <4 x i32> %x, %y %m = mul <4 x i32> %x, %y
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
▲ Show 20 Lines • Show All 380 Lines • ▼ Show 20 Linesentry:
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v4i16_v4i32_acc_zext: ; CHECK-LABEL: add_v4i16_v4i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q2, q2 ; CHECK-NEXT: vmullb.u16 q0, q0, q1
; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q2
; CHECK-NEXT: vcmp.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q2, q0, q1
; CHECK-NEXT: vaddva.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = zext <4 x i16> %x to <4 x i32> %xx = zext <4 x i16> %x to <4 x i32>
%yy = zext <4 x i16> %y to <4 x i32> %yy = zext <4 x i16> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) {
; CHECK-LABEL: add_v4i16_v4i32_acc_sext: ; CHECK-LABEL: add_v4i16_v4i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u16 q2, q2 ; CHECK-NEXT: vmullb.s16 q0, q0, q1
; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.u16 q1, q2
; CHECK-NEXT: vcmp.i32 eq, q2, zr ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q2, q0, q1
; CHECK-NEXT: vaddva.u32 r0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i16> %b, zeroinitializer %c = icmp eq <4 x i16> %b, zeroinitializer
%xx = sext <4 x i16> %x to <4 x i32> %xx = sext <4 x i16> %x to <4 x i32>
%yy = sext <4 x i16> %y to <4 x i32> %yy = sext <4 x i16> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) { define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) {
; CHECK-LABEL: add_v8i16_v8i16_acc: ; CHECK-LABEL: add_v8i16_v8i16_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i16 q0, q0, q1
; CHECK-NEXT: vpt.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q2, zr
; CHECK-NEXT: vmult.i16 q3, q0, q1 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vaddva.u16 r0, q3
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %b, zeroinitializer %c = icmp eq <8 x i16> %b, zeroinitializer
%m = mul <8 x i16> %x, %y %m = mul <8 x i16> %x, %y
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
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%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v4i8_v4i32_acc_zext: ; CHECK-LABEL: add_v4i8_v4i32_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vmov.i32 q3, #0xff
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vcmp.i32 eq, q2, zr
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vand q0, q0, q3 ; CHECK-NEXT: vand q0, q0, q3
; CHECK-NEXT: vpst ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vmult.i32 q2, q0, q1 ; CHECK-NEXT: vand q1, q2, q3
; CHECK-NEXT: vaddva.u32 r0, q2 ; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = zext <4 x i8> %x to <4 x i32> %xx = zext <4 x i8> %x to <4 x i32>
%yy = zext <4 x i8> %y to <4 x i32> %yy = zext <4 x i8> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
%r = add i32 %z, %a %r = add i32 %z, %a
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) { define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v4i8_v4i32_acc_sext: ; CHECK-LABEL: add_v4i8_v4i32_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0xff
; CHECK-NEXT: vmovlb.s8 q1, q1 ; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vcmp.i32 eq, q2, zr
; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vpst ; CHECK-NEXT: vmul.i32 q0, q0, q1
; CHECK-NEXT: vmult.i32 q2, q0, q1 ; CHECK-NEXT: vmov.i32 q1, #0xff
; CHECK-NEXT: vaddva.u32 r0, q2 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vpt.i32 eq, q1, zr
; CHECK-NEXT: vaddvat.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i8> %b, zeroinitializer %c = icmp eq <4 x i8> %b, zeroinitializer
%xx = sext <4 x i8> %x to <4 x i32> %xx = sext <4 x i8> %x to <4 x i32>
%yy = sext <4 x i8> %y to <4 x i32> %yy = sext <4 x i8> %y to <4 x i32>
%m = mul <4 x i32> %xx, %yy %m = mul <4 x i32> %xx, %yy
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
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%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) {
; CHECK-LABEL: add_v8i8_v8i16_acc_zext: ; CHECK-LABEL: add_v8i8_v8i16_acc_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q2, q2 ; CHECK-NEXT: vmullb.u8 q0, q0, q1
; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q1, q2
; CHECK-NEXT: vcmp.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q2, q0, q1
; CHECK-NEXT: vaddva.u16 r0, q2
; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = zext <8 x i8> %x to <8 x i16> %xx = zext <8 x i8> %x to <8 x i16>
%yy = zext <8 x i8> %y to <8 x i16> %yy = zext <8 x i8> %y to <8 x i16>
%m = mul <8 x i16> %xx, %yy %m = mul <8 x i16> %xx, %yy
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) {
; CHECK-LABEL: add_v8i8_v8i16_acc_sext: ; CHECK-LABEL: add_v8i8_v8i16_acc_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovlb.u8 q2, q2 ; CHECK-NEXT: vmullb.s8 q0, q0, q1
; CHECK-NEXT: vmovlb.s8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q1, q2
; CHECK-NEXT: vcmp.i16 eq, q2, zr ; CHECK-NEXT: vpt.i16 eq, q1, zr
; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vaddvat.u16 r0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q2, q0, q1
; CHECK-NEXT: vaddva.u16 r0, q2
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i8> %b, zeroinitializer %c = icmp eq <8 x i8> %b, zeroinitializer
%xx = sext <8 x i8> %x to <8 x i16> %xx = sext <8 x i8> %x to <8 x i16>
%yy = sext <8 x i8> %y to <8 x i16> %yy = sext <8 x i8> %y to <8 x i16>
%m = mul <8 x i16> %xx, %yy %m = mul <8 x i16> %xx, %yy
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
%r = add i16 %z, %a %r = add i16 %z, %a
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i8 %a) { define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i8 %a) {
; CHECK-LABEL: add_v16i8_v16i8_acc: ; CHECK-LABEL: add_v16i8_v16i8_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vmul.i8 q0, q0, q1
; CHECK-NEXT: vpt.i8 eq, q2, zr ; CHECK-NEXT: vpt.i8 eq, q2, zr
; CHECK-NEXT: vmult.i8 q3, q0, q1 ; CHECK-NEXT: vaddvat.u8 r0, q0
; CHECK-NEXT: vaddva.u8 r0, q3
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%m = mul <16 x i8> %x, %y %m = mul <16 x i8> %x, %y
%s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer %s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s) %z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
%r = add i8 %z, %a %r = add i8 %z, %a
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