[ARM][TEST] Add a new test case of add-imm & sub-imm

[benshi001]

Summary

This case will show furture optimization of add-imm & sub-imm.

[MaskRay]

llvm/test/CodeGen/ARM/armv6-add-sub-imm.ll

1 ↗

(On Diff #278367)

Have you considered removing armv6- from the filename?

If people want to test armv7-, they can simply add another RUN line.

BTW, you may consider llvm/utils/update_llc_test_checks.py, which can make test updating easy.

6 ↗

(On Diff #278367)

; CHECK-LABEL: sub0:

17 ↗

(On Diff #278367)

Add -NEXT: whenever appropriate

[MaskRay]

llvm/test/CodeGen/ARM/add-sub-imm.ll

5

;; probably works better. In the future, we can ask update_llc_test_checks.py to always retain ;; comments. (There is some intricate logic retaining ; comments)

[benshi001]

ping

[SjoerdMeijer]

Although I don't mind at all new tests being added, in this case I am really wondering if the code paths are not exercised by existing tests. And also reading the description:

This case will show furture optimization of add-imm & sub-imm.

I am wondering what these future optimizations are and if these tests should simply go in with that then?

[benshi001]

In D83928#2175664, @SjoerdMeijer wrote:

Although I don't mind at all new tests being added, in this case I am really wondering if the code paths are not exercised by existing tests. And also reading the description:

This case will show furture optimization of add-imm & sub-imm.

I am wondering what these future optimizations are and if these tests should simply go in with that then?

I expect this test will show improvements in
https://reviews.llvm.org/D83745
https://reviews.llvm.org/D84100

I hope this test case first be merged, then the above two patches will affect this test.

[SjoerdMeijer]

Committed in rG85342c27a303 as part of D83745.

llvm/test/CodeGen/ARM/add-sub-imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=CHECK
+
+;; Check how immediates are handled in add/sub.
+
+define i32 @sub0(i32 %0) {
+; CHECK-LABEL: sub0:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    sub r0, r0, #23
+; CHECK-NEXT:    mov pc, lr
+  %2 = sub i32 %0, 23
+  ret i32 %2
+}
+
+define i32 @sub1(i32 %0) {
+; CHECK-LABEL: sub1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r1, .LCPI1_0
+; CHECK-NEXT:    add r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI1_0:
+; CHECK-NEXT:    .long 4294836225 @ 0xfffe0001
+  %2 = sub i32 %0, 131071
+  ret i32 %2
+}
+
+define i32 @sub2(i32 %0) {
+; CHECK-LABEL: sub2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r1, .LCPI2_0
+; CHECK-NEXT:    add r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI2_0:
+; CHECK-NEXT:    .long 4294958301 @ 0xffffdcdd
+  %2 = sub i32 %0, 8995
+  ret i32 %2
+}
+
+define i32 @add0(i32 %0) {
+; CHECK-LABEL: add0:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    add r0, r0, #23
+; CHECK-NEXT:    mov pc, lr
+  %2 = add i32 %0, 23
+  ret i32 %2
+}
+
+define i32 @add1(i32 %0) {
+; CHECK-LABEL: add1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r1, .LCPI4_0
+; CHECK-NEXT:    add r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI4_0:
+; CHECK-NEXT:    .long 131071 @ 0x1ffff
+  %2 = add i32 %0, 131071
+  ret i32 %2
+}
+
+define i32 @add2(i32 %0) {
+; CHECK-LABEL: add2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    add r0, r0, #8960
+; CHECK-NEXT:    add r0, r0, #2293760
+; CHECK-NEXT:    mov pc, lr
+  %2 = add i32 %0, 2302720
+  ret i32 %2
+}