[PowerPC][Power10] Exploit the High Order Vector Multiply Instructions on Power10

[amyk]

Summary

This patch aims to exploit the following vector multiply high instructions on Power10.

vmulhsw VRT, VRA, VRB
vmulhsd VRT, VRA, VRB
vmulhuw VRT, VRA, VRB
vmulhud VRT, VRA, VRB

Depends on D82510.

[amyk]

Updated the patch to include assembly and disassembly tests that I forgot to add.

[anil9]

llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

11

nit: that -> those / which (as you said versions)

[amyk]

Updated the patch with a more descriptive comment in p10-vector-multiply.ll.

[amyk]

llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

11

I've actually updated and the comment to be a bit more descriptive (in hopes it would make more sense).

[amyk]

Updated patch to move out MC tests and td file definitions.

[kamaub]

This LGTM

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasAltivec()) {
 
     if (Subtarget.hasP8Altivec())
       setOperationAction(ISD::MUL, MVT::v4i32, Legal);
     else
       setOperationAction(ISD::MUL, MVT::v4i32, Custom);
 
     if (Subtarget.isISA3_1()) {
       setOperationAction(ISD::MUL, MVT::v2i64, Legal);
+      setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
+      setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
+      setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
+      setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
       setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::UREM, MVT::v2i64, Legal);
       setOperationAction(ISD::SREM, MVT::v2i64, Legal);
       setOperationAction(ISD::UREM, MVT::v4i32, Legal);
       setOperationAction(ISD::SREM, MVT::v4i32, Legal);

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [IsISA3_1] in {
    def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
   def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vmulld $vD, $vA, $vB", IIC_VecGeneral,
                         [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>;
   def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vmulhsw $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>;
   def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vmulhuw $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>;
   def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vmulhsd $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>;
   def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vmulhud $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vmulhud $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>;
   def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vmodsw $vD, $vA, $vB", IIC_VecGeneral,
                         [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>;
   def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vmoduw $vD, $vA, $vB", IIC_VecGeneral,
                         [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>;
   def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vmodsd $vD, $vA, $vB", IIC_VecGeneral,

llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 
 ; This test case aims to test the vector multiply instructions on Power10.
+; This includes the low order and high order versions of vector multiply.
+; The low order version operates on doublewords, whereas the high order version
+; operates on signed and unsigned words and doublewords.
 
 define <2 x i64> @test_vmulld(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vmulld:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmulld v2, v3, v2
 ; CHECK-NEXT:    blr
 entry:
   %mul = mul <2 x i64> %b, %a
   ret <2 x i64> %mul
 }
+
+define <2 x i64> @test_vmulhsd(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhsd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmulhsd v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = sext <2 x i64> %a to <2 x i128>
+  %1 = sext <2 x i64> %b to <2 x i128>
+  %mul = mul <2 x i128> %1, %0
+  %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+  %tr = trunc <2 x i128> %shr to <2 x i64>
+  ret <2 x i64> %tr
+}
+
+define <2 x i64> @test_vmulhud(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhud:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmulhud v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = zext <2 x i64> %a to <2 x i128>
+  %1 = zext <2 x i64> %b to <2 x i128>
+  %mul = mul <2 x i128> %1, %0
+  %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+  %tr = trunc <2 x i128> %shr to <2 x i64>
+  ret <2 x i64> %tr
+}
+
+define <4 x i32> @test_vmulhsw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhsw:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmulhsw v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = sext <4 x i32> %a to <4 x i64>
+  %1 = sext <4 x i32> %b to <4 x i64>
+  %mul = mul <4 x i64> %1, %0
+  %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+  %tr = trunc <4 x i64> %shr to <4 x i32>
+  ret <4 x i32> %tr
+}
+
+define <4 x i32> @test_vmulhuw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhuw:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmulhuw v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = zext <4 x i32> %a to <4 x i64>
+  %1 = zext <4 x i32> %b to <4 x i64>
+  %mul = mul <4 x i64> %1, %0
+  %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+  %tr = trunc <4 x i64> %shr to <4 x i32>
+  ret <4 x i32> %tr
+}