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[PowerPC][Power10] Implement low-order Vector Multiply, Modulus and Divide Instructions

Authored by amyk on Jun 24 2020, 4:40 PM.



This patch aims to implement the low order vector multiply, divide and modulo instructions
available on Power10.

The patch involves legalizing the ISD nodes MUL, UDIV, SDIV, UREM and SREM for
v2i64 and v4i32 vector types in order to utilize the following instructions:

vmulld VRT, VRA, VRB
vmodsw VRT, VRA, VRB
vmoduw VRT, VRA, VRB
vmodsd VRT, VRA, VRB
vmodud VRT, VRA, VRB
vdivsw VRT, VRA, VRB
vdivuw VRT, VRA, VRB
vdivsd VRT, VRA, VRB
vdivud VRT, VRA, VRB

Depends on D82929.

Diff Detail

Event Timeline

amyk created this revision.Jun 24 2020, 4:40 PM
amyk updated this revision to Diff 273536.Jun 25 2020, 3:34 PM

Edited patch to include assembly and disassembly test.

stefanp accepted this revision as: stefanp.Jun 29 2020, 4:15 AM
stefanp added a subscriber: stefanp.


This revision is now accepted and ready to land.Jun 29 2020, 4:15 AM
amyk updated this revision to Diff 274676.Jun 30 2020, 9:06 PM
amyk edited the summary of this revision. (Show Details)

Update the patch to remove instruction definitions and MC tests.

lei added a comment.Jul 8 2020, 11:38 AM

This LGTM, just wondering why you have not included testing for BE.


BE tests?


BE tests?



amyk added a comment.Jul 8 2020, 12:55 PM

Will address the comment of adding BE tests on the commit.

This revision was automatically updated to reflect the committed changes.