[AArch64][SVE] Only support sizeless bfloat types if supported by subtarget

[fpetrogalli]

Nit: the patch doesn't seem to have any dependencies on the other patches in the "Stack" tab. If that the case, please consider removing such dependencies.

Francesco

[c-rhodes]

In D82494#2112376, @fpetrogalli wrote:

Nit: the patch doesn't seem to have any dependencies on the other patches in the "Stack" tab. If that the case, please consider removing such dependencies.

Sorry I'm not sure what you mean? I've added 2 parent patches that address missing +bf16 guards on patterns in LLVM, I believe this should be able to land after those two patches are merged.

[fpetrogalli]

In D82494#2113671, @c-rhodes wrote:

In D82494#2112376, @fpetrogalli wrote:

Nit: the patch doesn't seem to have any dependencies on the other patches in the "Stack" tab. If that the case, please consider removing such dependencies.

Sorry I'm not sure what you mean? I've added 2 parent patches that address missing +bf16 guards on patterns in LLVM, I believe this should be able to land after those two patches are merged.

This change doesn't seem to need those to patches. I think you can land it independently from them?

[c-rhodes]

This change doesn't seem to need those to patches. I think you can land it independently from them?

The two patches add missing +bf16 guards to patterns that use this register class, the tests break when I introduce this without those patches.

[c-rhodes]

Changes:

• Add nxv2bf16 and nxv4bf16.

[sdesmalen]

LGTM!

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasSVE()) {
     addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv8i16, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv4i32, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv2i64, &AArch64::ZPRRegClass);
 
     addRegisterClass(MVT::nxv2f16, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv4f16, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv8f16, &AArch64::ZPRRegClass);
-    addRegisterClass(MVT::nxv2bf16, &AArch64::ZPRRegClass);
-    addRegisterClass(MVT::nxv4bf16, &AArch64::ZPRRegClass);
-    addRegisterClass(MVT::nxv8bf16, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv2f32, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass);
     addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass);
 
+    if (Subtarget->hasBF16()) {
+      addRegisterClass(MVT::nxv2bf16, &AArch64::ZPRRegClass);
+      addRegisterClass(MVT::nxv4bf16, &AArch64::ZPRRegClass);
+      addRegisterClass(MVT::nxv8bf16, &AArch64::ZPRRegClass);
+    }
+
     if (useSVEForFixedLengthVectors()) {
       for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
         if (useSVEForFixedLengthVectorVT(VT))
           addRegisterClass(VT, &AArch64::ZPRRegClass);
 
       for (MVT VT : MVT::fp_fixedlen_vector_valuetypes())
         if (useSVEForFixedLengthVectorVT(VT))
           addRegisterClass(VT, &AArch64::ZPRRegClass);