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[amdgpu] Fix REL32 relocations with negative offsets.
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Authored by hliao on Jun 19 2020, 2:03 PM.

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Summary
  • The offset should be treated as a signed one.

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Event Timeline

hliao created this revision.Jun 19 2020, 2:03 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 19 2020, 2:03 PM
hliao added a comment.Jun 19 2020, 2:09 PM

This patch only handles the case where that offset is representable in a 32-bit signed integer. For a generic 64-bit offset out of range of 32-bit integer, we need to revise the relocation spec to enhance REL32_HI from the orginal

(S +A - P) >> 32

to

(S + (A << 32) - P) >> 32

where A is that 32-bit sword addend. In fact, we split a 64-bit offset into low 32-bit addend used in REL32_LO and high 32-bit addend used in REL32_HI. However, that needs changes in more than components. As that's the rate case, I want to address the current critical issue first and will start the discussion on relocation changes.

hliao added a comment.Jun 19 2020, 2:10 PM

BTW, in the real example, that negative offset is created by LSR pass to reduce the code strength in a loop.

GlobalISel part isn't tested

hliao added a comment.Jun 19 2020, 6:41 PM

GlobalISel part isn't tested

GlobalISel doesn't have this issue yet as it won't fold G_GLOBAL_VALUE and PTR_ADD together. So, it only observe positive offsets. But, we'd better change that interface as well.

arsenm accepted this revision.Jun 20 2020, 1:26 PM

If you could merge this with an existing test for this, that would be slightly preferable

This revision is now accepted and ready to land.Jun 20 2020, 1:26 PM
This revision was automatically updated to reflect the committed changes.