[amdgpu] Fix REL32 relocations with negative offsets.

[hliao]

Summary

• The offset should be treated as a signed one.

[hliao]

This patch only handles the case where that offset is representable in a 32-bit signed integer. For a generic 64-bit offset out of range of 32-bit integer, we need to revise the relocation spec to enhance REL32_HI from the orginal

(S +A - P) >> 32

to

(S + (A << 32) - P) >> 32

where A is that 32-bit sword addend. In fact, we split a 64-bit offset into low 32-bit addend used in REL32_LO and high 32-bit addend used in REL32_HI. However, that needs changes in more than components. As that's the rate case, I want to address the current critical issue first and will start the discussion on relocation changes.

[hliao]

BTW, in the real example, that negative offset is created by LSR pass to reduce the code strength in a loop.

[arsenm]

GlobalISel part isn't tested

[hliao]

In D82234#2104634, @arsenm wrote:

GlobalISel part isn't tested

GlobalISel doesn't have this issue yet as it won't fold G_GLOBAL_VALUE and PTR_ADD together. So, it only observe positive offsets. But, we'd better change that interface as well.

[arsenm]

If you could merge this with an existing test for this, that would be slightly preferable

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

public:
   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
                                MachineIRBuilder &B) const;
   bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
                              MachineIRBuilder &B) const;
 
   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
                       MachineIRBuilder &B) const;
 
-  bool buildPCRelGlobalAddress(
-    Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
-    unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
+  bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
+                               const GlobalValue *GV, int64_t Offset,
+                               unsigned GAFlags = SIInstrInfo::MO_NONE) const;
 
   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
                            MachineIRBuilder &B) const;
   bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
                     MachineIRBuilder &B,
                     GISelChangeObserver &Observer) const;
 
   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Intrinsic::ID TrigIntrin = MI.getOpcode() == AMDGPU::G_FSIN ?
     Intrinsic::amdgcn_sin : Intrinsic::amdgcn_cos;
   B.buildIntrinsic(TrigIntrin, makeArrayRef<Register>(DstReg), false)
     .addUse(TrigVal)
     .setMIFlags(Flags);
   MI.eraseFromParent();
   return true;
 }
 
-bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(
-  Register DstReg, LLT PtrTy,
-  MachineIRBuilder &B, const GlobalValue *GV,
-  unsigned Offset, unsigned GAFlags) const {
+bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
+                                                  MachineIRBuilder &B,
+                                                  const GlobalValue *GV,
+                                                  int64_t Offset,
+                                                  unsigned GAFlags) const {
+  assert(isInt<32>(Offset + 4) && "32-bit offset is expected!");
   // In order to support pc-relative addressing, SI_PC_ADD_REL_OFFSET is lowered
   // to the following code sequence:
   //
   // For constant address space:
   //   s_getpc_b64 s[0:1]
   //   s_add_u32 s0, s0, $symbol
   //   s_addc_u32 s1, s1, 0
   //

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
   return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
           GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
           GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
          !shouldEmitGOTReloc(GA->getGlobal());
 }
 
 static SDValue
 buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
-                        const SDLoc &DL, unsigned Offset, EVT PtrVT,
+                        const SDLoc &DL, int64_t Offset, EVT PtrVT,
                         unsigned GAFlags = SIInstrInfo::MO_NONE) {
+  assert(isInt<32>(Offset + 4) && "32-bit offset is expected!");
   // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
   // lowered to the following code sequence:
   //
   // For constant address space:
   //   s_getpc_b64 s[0:1]
   //   s_add_u32 s0, s0, $symbol
   //   s_addc_u32 s1, s1, 0
   //

llvm/test/CodeGen/AMDGPU/rel32.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
+
+@g = protected local_unnamed_addr addrspace(4) externally_initialized global i32 0, align 4
+
+; CHECK-LABEL: rel32_neg_offset:
+; CHECK: s_getpc_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{]}}
+; CHECK: s_add_u32 s[[LO]], s[[LO]], g@rel32@lo-4
+; CHECK: s_addc_u32 s[[HI]], s[[HI]], g@rel32@hi-4
+define i32 addrspace(4)* @rel32_neg_offset() {
+  %r = getelementptr i32, i32 addrspace(4)* @g, i64 -2
+  ret i32 addrspace(4)* %r
+}