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Differential D81906

[CodeGen] Expand float operand for STRICT_FSETCC/STRICT_FSETCCS
ClosedPublic

Authored by steven.zhang on Jun 15 2020, 8:57 PM.

Details

Reviewers
uweigand
cameron.mcinally
craig.topper
andrew.w.kaylor
kpn
kristof.beyls
qiucf
Group Reviewers
Restricted Project
Commits
rG61ede38da0c4: [CodeGen] Expand float operand for STRICT_FSETCC/STRICT_FSETCCS
Summary

This patch is the continue work of https://reviews.llvm.org/D69281 to implement the way that expands STRICT_FSETCC/STRICT_FSETCCS.

Diff Detail

Event Timeline

steven.zhang created this revision.Jun 15 2020, 8:57 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 15 2020, 8:57 PM
Herald added subscribers: • wuzish, hiraditya, nemanjai. · View Herald Transcript
steven.zhang added a parent revision: D81727: [PowerPC] Support constrained fp operation for setcc.Jun 15 2020, 9:02 PM
Harbormaster failed remote builds in B60416: Diff 270951!Jun 15 2020, 10:32 PM
steven.zhang added a comment.Jun 22 2020, 4:17 PM

Gentle ping

steven.zhang added a comment.Jun 28 2020, 6:43 PM

Gentle ping ...

uweigand requested changes to this revision.Jun 30 2020, 2:46 AM
uweigand added inline comments.
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
1766

This isn't handling chains correctly. The function needs to collect the output chains of the four separate SetCC operations and return an output chain to the caller.

1900

See above; this needs to use the output Chain.

This revision now requires changes to proceed.Jun 30 2020, 2:46 AM
steven.zhang updated this revision to Diff 282561.Aug 3 2020, 3:13 AM

Address comments. Chain the fsetcc together. Thank you for the good comments!

Harbormaster completed remote builds in B66742: Diff 282561.Aug 3 2020, 3:15 AM
uweigand accepted this revision.Aug 3 2020, 3:49 AM

This LGTM now.

This revision is now accepted and ready to land.Aug 3 2020, 3:49 AM
This revision was landed with ongoing or failed builds.Aug 10 2020, 10:55 PM
Closed by commit rG61ede38da0c4: [CodeGen] Expand float operand for STRICT_FSETCC/STRICT_FSETCCS (authored by steven.zhang). · Explain Why
This revision was automatically updated to reflect the committed changes.
steven.zhang added a commit: rG61ede38da0c4: [CodeGen] Expand float operand for STRICT_FSETCC/STRICT_FSETCCS.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
50 lines
4 lines
test/
CodeGen/
PowerPC/
980 lines

Diff 270951

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Show First 20 Lines • Show All 1,704 Lines • ▼ Show 20 Lines#endif
case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
case ISD::STRICT_FP_TO_UINT: case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break; case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
case ISD::LROUND: Res = ExpandFloatOp_LROUND(N); break; case ISD::LROUND: Res = ExpandFloatOp_LROUND(N); break;
case ISD::LLROUND: Res = ExpandFloatOp_LLROUND(N); break; case ISD::LLROUND: Res = ExpandFloatOp_LLROUND(N); break;
case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break; case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break;
case ISD::LLRINT: Res = ExpandFloatOp_LLRINT(N); break; case ISD::LLRINT: Res = ExpandFloatOp_LLRINT(N); break;
case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS:
case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N), case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
OpNo); break; OpNo); break;
} }
// If the result is null, the sub-method took care of registering results etc. // If the result is null, the sub-method took care of registering results etc.
if (!Res.getNode()) return false; if (!Res.getNode()) return false;
Show All 9 Lines#endif
return false; return false;
} }
/// FloatExpandSetCCOperands - Expand the operands of a comparison. This code /// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
/// is shared among BR_CC, SELECT_CC, and SETCC handlers. /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS, void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
SDValue &NewRHS, SDValue &NewRHS,
ISD::CondCode &CCCode, ISD::CondCode &CCCode,
const SDLoc &dl) { const SDLoc &dl, SDValue Chain,
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for parameter 'dl' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for parameter 'dl' [readability-identifier-naming]…
bool IsSignaling) {
SDValue LHSLo, LHSHi, RHSLo, RHSHi; SDValue LHSLo, LHSHi, RHSLo, RHSHi;
GetExpandedFloat(NewLHS, LHSLo, LHSHi); GetExpandedFloat(NewLHS, LHSLo, LHSHi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi); GetExpandedFloat(NewRHS, RHSLo, RHSHi);
assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!"); assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
// FIXME: This generated code sucks. We want to generate // FIXME: This generated code sucks. We want to generate
// FCMPU crN, hi1, hi2 // FCMPU crN, hi1, hi2
// BNE crN, L: // BNE crN, L:
// FCMPU crN, lo1, lo2 // FCMPU crN, lo1, lo2
// The following can be improved, but not that much. // The following can be improved, but not that much.
SDValue Tmp1, Tmp2, Tmp3; SDValue Tmp1, Tmp2, Tmp3;
Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
LHSHi, RHSHi, ISD::SETOEQ); RHSHi, ISD::SETOEQ, Chain, IsSignaling);
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
LHSLo, RHSLo, CCCode); RHSLo, CCCode, Chain, IsSignaling);
Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
LHSHi, RHSHi, ISD::SETUNE); RHSHi, ISD::SETUNE, Chain, IsSignaling);
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
LHSHi, RHSHi, CCCode); RHSHi, CCCode, Chain, IsSignaling);
Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
NewRHS = SDValue(); // LHS is the result, not a compare. NewRHS = SDValue(); // LHS is the result, not a compare.
} }
uweigandUnsubmitted
Not Done
ReplyInline Actions

This isn't handling chains correctly. The function needs to collect the output chains of the four separate SetCC operations and return an output chain to the caller.

uweigand: This isn't handling chains correctly. The function needs to collect the output chains of the…
SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) { SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N)); FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
// If ExpandSetCCOperands returned a scalar, we need to compare the result // If ExpandSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 LinesSDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
// Update N to have the operands specified. // Update N to have the operands specified.
return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3), N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode)), 0); DAG.getCondCode(CCCode)), 0);
} }
SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) { SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); bool IsStrict = N->isStrictFPOpcode();
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); SDValue NewLHS = N->getOperand(IsStrict ? 1 : 0);
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N)); SDValue NewRHS = N->getOperand(IsStrict ? 2 : 1);
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
ISD::CondCode CCCode =
cast<CondCodeSDNode>(N->getOperand(IsStrict ? 3 : 2))->get();
FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N), Chain,
N->getOpcode() == ISD::STRICT_FSETCCS);
// If ExpandSetCCOperands returned a scalar, use it. // FloatExpandSetCCOperands always returned a scalar.
if (!NewRHS.getNode()) { assert(!NewRHS.getNode() && "Expect to return scalar");
assert(NewLHS.getValueType() == N->getValueType(0) && assert(NewLHS.getValueType() == N->getValueType(0) &&
"Unexpected setcc expansion!"); "Unexpected setcc expansion!");
return NewLHS; if (IsStrict) {
ReplaceValueWith(SDValue(N, 0), NewLHS);
ReplaceValueWith(SDValue(N, 1), Chain);
uweigandUnsubmitted
Not Done
ReplyInline Actions

See above; this needs to use the output Chain.

uweigand: See above; this needs to use the output Chain.
return SDValue();
} }
return NewLHS;
// Otherwise, update N to have the operands specified.
return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
DAG.getCondCode(CCCode)), 0);
} }
SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) { SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
if (ISD::isNormalStore(N)) if (ISD::isNormalStore(N))
return ExpandOp_NormalStore(N, OpNo); return ExpandOp_NormalStore(N, OpNo);
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
assert(OpNo == 1 && "Can only expand the stored value so far"); assert(OpNo == 1 && "Can only expand the stored value so far");
▲ Show 20 Lines • Show All 970 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Show First 20 Lines • Show All 622 Lines • ▼ Show 20 Linesprivate:
SDValue ExpandFloatOp_LLROUND(SDNode *N); SDValue ExpandFloatOp_LLROUND(SDNode *N);
SDValue ExpandFloatOp_LRINT(SDNode *N); SDValue ExpandFloatOp_LRINT(SDNode *N);
SDValue ExpandFloatOp_LLRINT(SDNode *N); SDValue ExpandFloatOp_LLRINT(SDNode *N);
SDValue ExpandFloatOp_SELECT_CC(SDNode *N); SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
SDValue ExpandFloatOp_SETCC(SDNode *N); SDValue ExpandFloatOp_SETCC(SDNode *N);
SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo); SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
ISD::CondCode &CCCode, const SDLoc &dl); ISD::CondCode &CCCode, const SDLoc &dl,
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for parameter 'dl' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for parameter 'dl' [readability-identifier-naming]…
SDValue Chain = SDValue(),
bool IsSignaling = false);
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Float promotion support: LegalizeFloatTypes.cpp // Float promotion support: LegalizeFloatTypes.cpp
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
SDValue GetPromotedFloat(SDValue Op) { SDValue GetPromotedFloat(SDValue Op) {
TableId &PromotedId = PromotedFloats[getTableId(Op)]; TableId &PromotedId = PromotedFloats[getTableId(Op)];
SDValue PromotedOp = getSDValue(PromotedId); SDValue PromotedOp = getSDValue(PromotedId);
▲ Show 20 Lines • Show All 384 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

Show First 20 Lines • Show All 2,683 Lines • ▼ Show 20 Lines
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_olt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_olt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_olt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ole_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, gt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ole_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, gt
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, gt
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ole_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, gt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ogt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ogt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ogt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_oge_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, lt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_oge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, lt
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, lt
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_oge_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, lt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_oeq_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_oeq_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_oeq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_one_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, eq
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_one_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, eq
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, eq
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_one_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, eq
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ult_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, lt, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ult_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, lt, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, lt, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ult_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, lt, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ule_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ule_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; P9-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ule_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ugt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, gt, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ugt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, gt, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, gt, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ugt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, gt, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_uge_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_uge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; P9-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_uge_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_ueq_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, eq, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ueq_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, eq, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, eq, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ueq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, eq, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmp_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmp_une_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_une_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_une_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_olt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_olt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_olt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ole_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, gt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ole_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, gt
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, gt
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ole_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, gt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+gt
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ogt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ogt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ogt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, gt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_oge_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, lt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_oge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, lt
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, lt
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_oge_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, lt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+lt
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_oeq_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_oeq_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; P9-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_oeq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, eq
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr1+eq, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_one_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, eq
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_one_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: crnor 4*cr5+lt, un, eq
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: crnor 4*cr5+gt, un, eq
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_one_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, eq
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+un, 4*cr1+eq
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ult_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, lt, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ult_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, lt, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, lt, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ult_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, lt, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+lt, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ule_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ule_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; P9-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ule_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ugt_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, gt, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ugt_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, gt, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, gt, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ugt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, gt, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_uge_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; P8-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_uge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; P9-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_uge_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_ueq_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: cror 4*cr5+lt, eq, un
; P8-NEXT: cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ueq_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: cror 4*cr5+lt, eq, un
; P9-NEXT: fcmpu cr0, f1, f3
; P9-NEXT: cror 4*cr5+gt, eq, un
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: li r3, 1
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ueq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: cror 4*cr5+lt, eq, un
; NOVSX-NEXT: cror 4*cr5+gt, 4*cr1+eq, 4*cr1+un
; NOVSX-NEXT: crand 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr1+eq
; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @fcmps_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-LABEL: fcmps_une_ppcf128:
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: li r3, 1
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_une_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_une_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
attributes #0 = { strictfp nounwind } attributes #0 = { strictfp nounwind }
declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmps.f128(fp128, fp128, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmps.f128(fp128, fp128, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmp.f128(fp128, fp128, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmp.f128(fp128, fp128, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128, ppc_fp128, metadata, metadata)
declare i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128, ppc_fp128, metadata, metadata)