[amdgpu] Skip OR combining on 64-bit integer before legalizing ops.

[rampitec]

What's the rational and practical test?

[arsenm]

In D81710#2090252, @rampitec wrote:

What's the rational and practical test?

The full or is a better canonical form and splitting it will interfere with other combines

[rampitec]

In D81710#2090255, @arsenm wrote:

In D81710#2090252, @rampitec wrote:

What's the rational and practical test?

The full or is a better canonical form and splitting it will interfere with other combines

OK, but is there any test?

[hliao]

In D81710#2090357, @rampitec wrote:

In D81710#2090255, @arsenm wrote:

In D81710#2090252, @rampitec wrote:

What's the rational and practical test?

The full or is a better canonical form and splitting it will interfere with other combines

OK, but is there any test?

There's one existing test benefitting from that.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if (LHSMask != ~0u && RHSMask != ~0u) {
 
         return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
                            LHS.getOperand(0), RHS.getOperand(0),
                            DAG.getConstant(Sel, DL, MVT::i32));
       }
     }
   }
 
-  if (VT != MVT::i64)
+  if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
     return SDValue();
 
   // TODO: This could be a generic combine with a predicate for extracting the
   // high half of an integer being free.
 
   // (or i64:x, (zero_extend i32:y)) ->
   //   i64 (bitcast (v2i32 build_vector (or i32:y, lo_32(x)), hi_32(x)))
   if (LHS.getOpcode() == ISD::ZERO_EXTEND &&

llvm/test/CodeGen/AMDGPU/fshr.ll

 ; SI-NEXT:    v_sub_i32_e32 v4, vcc, 16, v1
 ; SI-NEXT:    v_and_b32_e32 v10, s4, v5
 ; SI-NEXT:    v_lshr_b32_e32 v3, v10, v1
 ; SI-NEXT:    v_lshl_b32_e32 v2, v2, v4
 ; SI-NEXT:    v_or_b32_e32 v2, v2, v3
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
 ; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; SI-NEXT:    v_and_b32_e32 v2, v9, v1
-; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; SI-NEXT:    v_alignbit_b32 v1, v1, v0, 16
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: v_fshr_v3i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v6, 15
 ; VI-NEXT:    v_and_b32_sdwa v6, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v2