[SVE] Disable Global and Fast ISel at -O0 if the SVE feature is found

[david-arm]

Summary

At the moment we use Global ISel by default at -O0, however it is
currently not capable of dealing with scalable vectors for two
reasons:

1. The register banks know nothing about SVE registers.
2. The LLT (Low Level Type) class knows nothing about scalable

vectors.

For now, the easiest way to avoid users hitting issues when using
the SVE ACLE is to disable Global ISel. In addition, we need to
also disable Fast ISel, since it doesn't just work for scalable
vectors at the moment either.

I've added a couple of RUN lines to existing SVE tests to ensure
we can compile at -O0.

[david-arm]

Hi @aemerson, do you know if there are any plans to add scalable vector support to global isel for AArch64?

[aemerson]

In D81368#2079185, @david-arm wrote:

Hi @aemerson, do you know if there are any plans to add scalable vector support to global isel for AArch64?

Hi Greg. I don't have plans personally to work on scalable vector support for GlobalISel, but it's a good idea for someone to do so. Bailing out of both fastisel and GISel will result in SDag being used and hit -O0 compile times significantly.

Maybe a better way would be to fall back to SelectionDAG if any scalable types are found in the IR during translation. A custom "target wants to fall back" hook might be wanted here to make it cleaner. That way, -fsve or whatever it is to enable SVE won't unnecessarily use SelectionDAG at -O0 unless there are actual scalable types present.

[david-arm]

Hi @aemerson, it's Gregg (with two g's by the way). I'm afraid I can't provide any sausage rolls at this time, but I've certainly found a way to add a hook as you suggested!

[david-arm]

I'll push a new patch soon that adds a hook to fall back to DAG ISel.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

*Fast = !Subtarget->isMisaligned128StoreSlow() ||
             Ty == LLT::vector(2, 64);
   }
   return true;
 }
 
 FastISel *
 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
                                       const TargetLibraryInfo *libInfo) const {
+  if (Subtarget->hasSVE())
+    return nullptr;
   return AArch64::createFastISel(funcInfo, libInfo);
 }
 
 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((AArch64ISD::NodeType)Opcode) {
   case AArch64ISD::FIRST_NUMBER:      break;
   case AArch64ISD::CALL:              return "AArch64ISD::CALL";
   case AArch64ISD::ADRP:              return "AArch64ISD::ADRP";

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
     this->Options.TLSSize = 24;
 
   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
   // MachO/CodeModel::Large, which GlobalISel does not support.
   if (getOptLevel() <= EnableGlobalISelAtO &&
       TT.getArch() != Triple::aarch64_32 &&
       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
-    setGlobalISel(true);
+
+    bool HasSVE = false;
+    SmallVector<StringRef, 6> Features;
+    FS.split(Features, ',');
+    for (StringRef Feature : Features) {
+      if (Feature == "+sve")
+        HasSVE = true;
+      else if (Feature == "-sve")
+        HasSVE = false;
+    }
+
+    setGlobalISel(!HasSVE);
     setGlobalISelAbort(GlobalISelAbortMode::Disable);
   }
 
   // AArch64 supports the MachineOutliner.
   setMachineOutliner(true);
 
   // AArch64 supports default outlining behaviour.
   setSupportsDefaultOutlining(true);

llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; LD1B
 ;
 
 define <vscale x 16 x i8> @ld1b_i8(<vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: ld1b_i8:
 ; CHECK: ld1b { z0.b }, p0/z, [x0]

llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; ST1B
 ;
 
 define void @st1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: st1b_i8:
 ; CHECK: st1b { z0.b }, p0, [x0]