[PowerPC] Fix RM operands for some instructions

[ZhangKang]

Summary

Some instructions have set the wrong [RM] flag, this patch is to fix it.

Instructions x(v|s)r(d|s)pi[zmp]? and fri[npzm] use fixed rounding directions without referencing current rounding mode.
This patch will remove their use to RM in instructions definition.

Also, the SETRNDi, SETRND, BCLRn, MTFSFI, MTFSB0, MTFSB1, MTFSFb, MTFSFI, MTFSFI_rec, MTFSF, MTFSF_rec should also fix the RM flag.

[ZhangKang]

Add a test case.

[ZhangKang]

Fix XSRDPI/XSRDPIM/XSRDPIP/XSRDPIZ, XVRDPI/XVRDPIM XVRDPIP XSRDPIZ, XVRSPI/XVRSPIM XVRSPIP XSRSPIZ

[jsji]

Please rebase. Also why this depends on D76042?

[ZhangKang]

In D81360#2159250, @jsji wrote:

Also why this depends on D76042?

The patch D76042 will remove the redundant the implicit operands in ppc-early-ret pass.
Below code is from the origin case test/CodeGen/PowerPC/early-ret.mir.

109   ; CHECK:   BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit $lr, implicit $rm, implicit killed $v2
110   ; CHECK: bb.1.entry:
111   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
112   ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2

The patch D76042 will fix the redundant implicit in line 109, you can see the line 112 is right. In fact, here line 112 is right,
because we have forgotten to set 'Uses = [LR, RM]', this is what this patch does. So I set this patch depends on D76042, or we will
see the line 112 will be wrong after fix the 'RM' flag.

1526     let isReturn = 1, Uses = [LR, RM] in
1527     def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1528                              "bclr 12, $bi, 0", IIC_BrB, []>;
1529     def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1530                              "bclr 4, $bi, 0", IIC_BrB, []>;

[ZhangKang]

Rebase.

[jsji]

Looks like some duplicate work in D83471, can you please sync with @qiucf , and either split the statics out or merge two patches.

[qiucf]

In D81360#2161220, @jsji wrote:

Looks like some duplicate work in D83471, can you please sync with @qiucf , and either split the statics out or merge two patches.

Oh, I didn't see this patch already contains these changes.. I'd like to abandon D83471. @ZhangKang we can also remove ref to RM for fri[npzm]. Thanks.

[ZhangKang]

Merge https://reviews.llvm.org/D83471 into this patch.

[jsji]

Please add more tests for affected opcodes, not just SETRND. Thanks.

[ZhangKang]

Add the case for MTFSF.

[ZhangKang]

Add more cases.

[jsji]

Please also add tests for mtfsb0 etc.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

1471

int_ppc_setrnd will read FPSCR which include RM, why we want to remove the use of it?

2875

mtfsb0 will only change RM when the bit is 30/31, which is actually in SETRNDi, SETRND.. So I think we should not always Def RM here? Maybe some PatLeaf to check bits and only set it with 30/31 bits?
Similar for mtfsfi, mtfsf?

[ZhangKang]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

1471

Yes, I should not remove the use for RM here, because we will use MFFS to store the FPSCR.

2875

Has removed the rm for mtfsb0 mtfsb1 and mtfsfi.

[ZhangKang]

Update the patch to follow reviewers' comments.

[ZhangKang]

FIx the comments.

[jsji]

LGTM. Thanks.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

4277

Can we split this into another patch, this is not related to RM.

[jsji]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12728 ↗

(On Diff #281264)

This will read RM as well, so we should add implicit operand here too.

[ZhangKang]

Remove the CR1

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12728 ↗

(On Diff #281264)

I only remove use/def RM for MTFSB0/MTFSB1/MTFSFI, because they use the constant, we can know whether they will use the RM.
For those instructions which use the Reg to set FPSCR, I have set it use/def RM in the td files. So MFFS will be added RM automatically.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

4277

OK, I will commit a NFC patch directly to fix the CR1.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

let isCodeGenOnly = 1 in {
                                 "bcctr 12, $bi, 0", IIC_BrB, []>;
       def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
                                 "bcctr 4, $bi, 0", IIC_BrB, []>;
     }
   }
 }
 
 // Set the float rounding mode.
-let Uses = [RM], Defs = [RM] in { 
+let Defs = [RM] in {
 def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
                     "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;
 
 def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in),
                     "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>;
 }
 
 let Defs = [LR] in
let isCodeGenOnly = 1 in {
     let Pattern = [(brcond i1:$bi, bb:$dst)] in
     def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
              "bc 12, $bi, $dst">;
 
     let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
     def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
              "bc 4, $bi, $dst">;
 
-    let isReturn = 1, Uses = [LR, RM] in
+    let isReturn = 1, Uses = [LR, RM] in {
     def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
                              "bclr 12, $bi, 0", IIC_BrB, []>;
     def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
                              "bclr 4, $bi, 0", IIC_BrB, []>;
     }
+  }
 
   let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
    def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
                              "bdzlr", IIC_BrB, []>;
    def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
                              "bdnzlr", IIC_BrB, []>;
    def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
                              "bdzlr+", IIC_BrB, []>;

 // Custom inserter instruction to perform FADD in round-to-zero mode.
 let Uses = [RM] in {
   def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
                       [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
 }
 
 // The above pseudo gets expanded to make use of the following instructions
 // to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
-let Uses = [RM], Defs = [RM] in { 
+let Defs = [RM] in {
   def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
                         "mtfsb0 $FM", IIC_IntMTFSB0, []>,
                PPC970_DGroup_Single, PPC970_Unit_FPU;
   def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
                         "mtfsb1 $FM", IIC_IntMTFSB0, []>,
                PPC970_DGroup_Single, PPC970_Unit_FPU;
   let isCodeGenOnly = 1 in
   def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
                   "mfmsr $RT", IIC_SprMFMSR, []>;
 
 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
                     "mtmsrd $RS, $L", IIC_SprMTMSRD>;
 
 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
                      "mcrfs $BF, $BFA", IIC_BrMCR>;
 
+let Defs = [RM] in {
 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                       "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
 
 def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                        "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
+}
 
 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
 
 let Predicates = [HasFPU] in {
+let Defs = [RM] in {
 def MTFSF : XFLForm_1<63, 711, (outs),
                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
                       "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
 def MTFSF_rec : XFLForm_1<63, 711, (outs),
                        (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
                        "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
+}
 
 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 }
 
 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
                         "slbie $RB", IIC_SprSLBIE, []>;