[PowerPC] Exploit vnmsubfp instruction

[qiucf]

Summary

On PowerPC, we have vnmsubfp Altivec instruction for fnmsub operation on v4f32 type. Default pattern for this instruction never works since we don't have legal fneg for v4f32 when VSX disabled.

This is based on new opcodes D76585 added.

[steven.zhang]

LGTM. Thank you for adding this.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::combineFMALike(SDNode *N,
   SelectionDAG &DAG = DCI.DAG;
   const TargetOptions &Options = getTargetMachine().Options;
   unsigned Opc = N->getOpcode();
   bool CodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
   bool LegalOps = !DCI.isBeforeLegalizeOps();
   SDLoc Loc(N);
 
   // TODO: QPX subtarget is deprecated. No transformation here.
-  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT) ||
-      (VT.isVector() && !Subtarget.hasVSX()))
+  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT))
     return SDValue();
 
   // Allowing transformation to FNMSUB may change sign of zeroes when ab-c=0
   // since (fnmsub a b c)=-0 while c-ab=+0.
   if (!Flags.hasNoSignedZeros() && !Options.NoSignedZerosFPMath)
     return SDValue();
 
   // (fma (fneg a) b c) => (fnmsub a b c)

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
           (VNOR $A, $B)>;
 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
           (VANDC $A, $B)>;
 
 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
           (VMADDFP $vA, $vB,
              (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 
 
+def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
+          (VNMSUBFP $A, $B, $C)>;
+
 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VMADDFP $A, $B, $C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VNMSUBFP $A, $B, $C)>;
 
 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
           (VPERM $vA, $vB, $vC)>;
 

llvm/test/CodeGen/PowerPC/fma-negate.ll

 ; VSX-LABEL: test_fast_neg_fma_v4f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xvnmsubasp 36, 34, 35
 ; VSX-NEXT:    vmr 2, 4
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_v4f32:
 ; NO-VSX:       # %bb.0: # %entry
-; NO-VSX-NEXT:    vspltisb 5, -1
-; NO-VSX-NEXT:    vslw 5, 5, 5
-; NO-VSX-NEXT:    vsubfp 2, 5, 2
-; NO-VSX-NEXT:    vmaddfp 2, 2, 3, 4
+; NO-VSX-NEXT:    vnmsubfp 2, 2, 3, 4
 ; NO-VSX-NEXT:    blr
                                             <4 x float> %c) {
 entry:
   %0 = fsub reassoc <4 x float> <float -0.0, float -0.0, float -0.0,
                                           float -0.0>, %a
   %1 = call reassoc nsz <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %b,
                                                     <4 x float> %c)
   ret <4 x float> %1
 }
 
 declare float  @llvm.fma.f32(float  %a, float  %b, float  %c)
 declare double @llvm.fma.f64(double %a, double %b, double %c)
 declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,
                                                     <4 x float> %c)
 declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,
                                                       <2 x double> %c)

llvm/test/CodeGen/PowerPC/recipest.ll

; CHECK-P9-NEXT:    blr
   ret float %r
 }
 
 define <4 x float> @hoo2_fmf(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo2_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 4, -1
 ; CHECK-P7-NEXT:    vrefp 5, 3
-; CHECK-P7-NEXT:    vspltisb 0, -1
-; CHECK-P7-NEXT:    vslw 0, 0, 0
 ; CHECK-P7-NEXT:    vslw 4, 4, 4
-; CHECK-P7-NEXT:    vsubfp 3, 0, 3
 ; CHECK-P7-NEXT:    vmaddfp 4, 2, 5, 4
-; CHECK-P7-NEXT:    vmaddfp 2, 3, 4, 2
+; CHECK-P7-NEXT:    vnmsubfp 2, 3, 4, 2
 ; CHECK-P7-NEXT:    vmaddfp 2, 5, 2, 4
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo2_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvresp 1, 35
 ; CHECK-P8-NEXT:    xvmulsp 0, 34, 1
 ; CHECK-P8-NEXT:    xvnmsubasp 34, 35, 0