[SVE] MOVPRFX zero merging test renaming

[cameron.mcinally]

Summary

Rename the MOVPRFX zero merging tests to prepare for a followup patch which adds general passthru merging support.

Any objections to the new name?

[efriedma]

Not sure you really needed to post a separate patch for this, but sure, LGTM

llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=sve < %s | FileCheck %s
 
 ;
 ; FADD
 ;
 
-define <vscale x 8 x half> @fadd_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fadd_h:
+define <vscale x 8 x half> @fadd_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fadd_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %pg,
                                                             <vscale x 8 x half> %a_z,
                                                             <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fadd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fadd_s:
+define <vscale x 4 x float> @fadd_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fadd_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %a_z,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fadd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fadd_d:
+define <vscale x 2 x double> @fadd_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fadd_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x double> %a_z,
                                                               <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FMAX
 ;
 
-define <vscale x 8 x half> @fmax_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fmax_h:
+define <vscale x 8 x half> @fmax_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fmax_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1> %pg,
                                                             <vscale x 8 x half> %a_z,
                                                             <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fmax_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fmax_s:
+define <vscale x 4 x float> @fmax_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fmax_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %a_z,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fmax_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fmax_d:
+define <vscale x 2 x double> @fmax_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fmax_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x double> %a_z,
                                                               <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FMAXNM
 ;
 
-define <vscale x 8 x half> @fmaxnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fmaxnm_h:
+define <vscale x 8 x half> @fmaxnm_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fmaxnm_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
                                                               <vscale x 8 x half> %a_z,
                                                               <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fmaxnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fmaxnm_s:
+define <vscale x 4 x float> @fmaxnm_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fmaxnm_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x float> %a_z,
                                                                <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fmaxnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fmaxnm_d:
+define <vscale x 2 x double> @fmaxnm_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fmaxnm_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
                                                                 <vscale x 2 x double> %a_z,
                                                                 <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FMIN
 ;
 
-define <vscale x 8 x half> @fmin_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fmin_h:
+define <vscale x 8 x half> @fmin_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fmin_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1> %pg,
                                                             <vscale x 8 x half> %a_z,
                                                             <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fmin_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fmin_s:
+define <vscale x 4 x float> @fmin_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fmin_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %a_z,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fmin_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fmin_d:
+define <vscale x 2 x double> @fmin_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fmin_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x double> %a_z,
                                                               <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FMINNM
 ;
 
-define <vscale x 8 x half> @fminnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fminnm_h:
+define <vscale x 8 x half> @fminnm_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fminnm_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %pg,
                                                               <vscale x 8 x half> %a_z,
                                                               <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fminnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fminnm_s:
+define <vscale x 4 x float> @fminnm_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fminnm_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x float> %a_z,
                                                                <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fminnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fminnm_d:
+define <vscale x 2 x double> @fminnm_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fminnm_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
                                                                 <vscale x 2 x double> %a_z,
                                                                 <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FMUL
 ;
 
-define <vscale x 8 x half> @fmul_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fmul_h:
+define <vscale x 8 x half> @fmul_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fmul_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %pg,
                                                             <vscale x 8 x half> %a_z,
                                                             <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fmul_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fmul_s:
+define <vscale x 4 x float> @fmul_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fmul_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %a_z,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fmul_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fmul_d:
+define <vscale x 2 x double> @fmul_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fmul_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x double> %a_z,
                                                               <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FSUB
 ;
 
-define <vscale x 8 x half> @fsub_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fsub_h:
+define <vscale x 8 x half> @fsub_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fsub_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %pg,
                                                             <vscale x 8 x half> %a_z,
                                                             <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fsub_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fsub_s:
+define <vscale x 4 x float> @fsub_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fsub_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %a_z,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fsub_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fsub_d:
+define <vscale x 2 x double> @fsub_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fsub_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x double> %a_z,
                                                               <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out
 }
 
 ;
 ; FSUBR
 ;
 
-define <vscale x 8 x half> @fsubr_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
-; CHECK-LABEL: fsubr_h:
+define <vscale x 8 x half> @fsubr_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: fsubr_h_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1> %pg,
                                                              <vscale x 8 x half> %a_z,
                                                              <vscale x 8 x half> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fsubr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
-; CHECK-LABEL: fsubr_s:
+define <vscale x 4 x float> @fsubr_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: fsubr_s_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
                                                               <vscale x 4 x float> %a_z,
                                                               <vscale x 4 x float> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fsubr_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
-; CHECK-LABEL: fsubr_d:
+define <vscale x 2 x double> @fsubr_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: fsubr_d_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
                                                                <vscale x 2 x double> %a_z,
                                                                <vscale x 2 x double> %b)
   ret <vscale x 2 x double> %out

llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; ADD
 ;
 
-define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: add_i8:
+define <vscale x 16 x i8> @add_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: add_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i8> %a_z,
                                                                <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: add_i16:
+define <vscale x 8 x i16> @add_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: add_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %pg,
                                                                <vscale x 8 x i16> %a_z,
                                                                <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: add_i32:
+define <vscale x 4 x i32> @add_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: add_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x i32> %a_z,
                                                                <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: add_i64:
+define <vscale x 2 x i64> @add_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: add_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %pg,
                                                                <vscale x 2 x i64> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
 ;
 ; SUB
 ;
 
-define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: sub_i8:
+define <vscale x 16 x i8> @sub_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: sub_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i8> %a_z,
                                                                <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: sub_i16:
+define <vscale x 8 x i16> @sub_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: sub_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %pg,
                                                                <vscale x 8 x i16> %a_z,
                                                                <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: sub_i32:
+define <vscale x 4 x i32> @sub_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: sub_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x i32> %a_z,
                                                                <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: sub_i64:
+define <vscale x 2 x i64> @sub_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: sub_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %pg,
                                                                <vscale x 2 x i64> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
 ;
 ; SUBR
 ;
 
-define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: subr_i8:
+define <vscale x 16 x i8> @subr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: subr_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: subr z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i8> %a_z,
                                                                 <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: subr_i16:
+define <vscale x 8 x i16> @subr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: subr_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: subr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,
                                                                 <vscale x 8 x i16> %a_z,
                                                                 <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: subr_i32:
+define <vscale x 4 x i32> @subr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: subr_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,
                                                                 <vscale x 4 x i32> %a_z,
                                                                 <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: subr_i64:
+define <vscale x 2 x i64> @subr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: subr_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: subr z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,
                                                                 <vscale x 2 x i64> %a_z,
                                                                 <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out

llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; ASR
 ;
 
-define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: asr_i8:
+define <vscale x 16 x i8> @asr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: asr_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg,
                                                           <vscale x 16 x i8> %a_z,
                                                           <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: asr_i16:
+define <vscale x 8 x i16> @asr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: asr_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg,
                                                           <vscale x 8 x i16> %a_z,
                                                           <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: asr_i32:
+define <vscale x 4 x i32> @asr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: asr_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg,
                                                           <vscale x 4 x i32> %a_z,
                                                           <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: asr_i64:
+define <vscale x 2 x i64> @asr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: asr_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg,
                                                           <vscale x 2 x i64> %a_z,
                                                           <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 16 x i8> @asr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: asr_wide_i8:
+define <vscale x 16 x i8> @asr_wide_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: asr_wide_i8_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: asr z0.b, p0/m, z0.b, z1.d
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i8> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @asr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: asr_wide_i16:
+define <vscale x 8 x i16> @asr_wide_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: asr_wide_i16_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: asr z0.h, p0/m, z0.h, z1.d
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.wide.nxv8i16(<vscale x 8 x i1> %pg,
                                                                <vscale x 8 x i16> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @asr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: asr_wide_i32:
+define <vscale x 4 x i32> @asr_wide_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: asr_wide_i32_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: asr z0.s, p0/m, z0.s, z1.d
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.wide.nxv4i32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x i32> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 4 x i32> %out
 }
 
 ;
 ; ASRD
 ;
 
-define <vscale x 16 x i8> @asrd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
-; CHECK-LABEL: asrd_i8:
+define <vscale x 16 x i8> @asrd_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
+; CHECK-LABEL: asrd_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #1
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg,
                                                            <vscale x 16 x i8> %a_z,
                                                            i32 1)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @asrd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
-; CHECK-LABEL: asrd_i16:
+define <vscale x 8 x i16> @asrd_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
+; CHECK-LABEL: asrd_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #2
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %pg,
                                                            <vscale x 8 x i16> %a_z,
                                                            i32 2)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @asrd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
-; CHECK-LABEL: asrd_i32:
+define <vscale x 4 x i32> @asrd_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
+; CHECK-LABEL: asrd_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #31
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %pg,
                                                            <vscale x 4 x i32> %a_z,
                                                            i32 31)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @asrd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
-; CHECK-LABEL: asrd_i64:
+define <vscale x 2 x i64> @asrd_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
+; CHECK-LABEL: asrd_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #64
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %pg,
                                                            <vscale x 2 x i64> %a_z,
                                                            i32 64)
   ret <vscale x 2 x i64> %out
 }
 
 ;
 ; LSL
 ;
 
-define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: lsl_i8:
+define <vscale x 16 x i8> @lsl_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: lsl_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,
                                                           <vscale x 16 x i8> %a_z,
                                                           <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: lsl_i16:
+define <vscale x 8 x i16> @lsl_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: lsl_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,
                                                           <vscale x 8 x i16> %a_z,
                                                           <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: lsl_i32:
+define <vscale x 4 x i32> @lsl_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: lsl_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,
                                                           <vscale x 4 x i32> %a_z,
                                                           <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsl_i64:
+define <vscale x 2 x i64> @lsl_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsl_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,
                                                           <vscale x 2 x i64> %a_z,
                                                           <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 16 x i8> @lsl_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsl_wide_i8:
+define <vscale x 16 x i8> @lsl_wide_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsl_wide_i8_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsl z0.b, p0/m, z0.b, z1.d
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i8> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @lsl_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsl_wide_i16:
+define <vscale x 8 x i16> @lsl_wide_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsl_wide_i16_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsl z0.h, p0/m, z0.h, z1.d
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.wide.nxv8i16(<vscale x 8 x i1> %pg,
                                                                <vscale x 8 x i16> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @lsl_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsl_wide_i32:
+define <vscale x 4 x i32> @lsl_wide_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsl_wide_i32_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsl z0.s, p0/m, z0.s, z1.d
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.wide.nxv4i32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x i32> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 4 x i32> %out
 }
 
 ;
 ; LSR
 ;
 
-define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
-; CHECK-LABEL: lsr_i8:
+define <vscale x 16 x i8> @lsr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: lsr_i8_zero:
 ; CHECK:      movprfx z0.b, p0/z, z0.b
 ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg,
                                                           <vscale x 16 x i8> %a_z,
                                                           <vscale x 16 x i8> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
-; CHECK-LABEL: lsr_i16:
+define <vscale x 8 x i16> @lsr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: lsr_i16_zero:
 ; CHECK:      movprfx z0.h, p0/z, z0.h
 ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg,
                                                           <vscale x 8 x i16> %a_z,
                                                           <vscale x 8 x i16> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-; CHECK-LABEL: lsr_i32:
+define <vscale x 4 x i32> @lsr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: lsr_i32_zero:
 ; CHECK:      movprfx z0.s, p0/z, z0.s
 ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg,
                                                           <vscale x 4 x i32> %a_z,
                                                           <vscale x 4 x i32> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsr_i64:
+define <vscale x 2 x i64> @lsr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsr_i64_zero:
 ; CHECK:      movprfx z0.d, p0/z, z0.d
 ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT: ret
   %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg,
                                                           <vscale x 2 x i64> %a_z,
                                                           <vscale x 2 x i64> %b)
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 16 x i8> @lsr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsr_wide_i8:
+define <vscale x 16 x i8> @lsr_wide_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsr_wide_i8_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsr z0.b, p0/m, z0.b, z1.d
   %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i8> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 16 x i8> %out
 }
 
-define <vscale x 8 x i16> @lsr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsr_wide_i16:
+define <vscale x 8 x i16> @lsr_wide_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsr_wide_i16_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsr z0.h, p0/m, z0.h, z1.d
   %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
   %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.wide.nxv8i16(<vscale x 8 x i1> %pg,
                                                                <vscale x 8 x i16> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 8 x i16> %out
 }
 
-define <vscale x 4 x i32> @lsr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
-; CHECK-LABEL: lsr_wide_i32:
+define <vscale x 4 x i32> @lsr_wide_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: lsr_wide_i32_zero:
 ; CHECK-NOT:  movprfx
 ; CHECK: lsr z0.s, p0/m, z0.s, z1.d
   %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.wide.nxv4i32(<vscale x 4 x i1> %pg,
                                                                <vscale x 4 x i32> %a_z,
                                                                <vscale x 2 x i64> %b)
   ret <vscale x 4 x i32> %out
 }