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Differential D79968

StoreInst should store Align, not MaybeAlign
ClosedPublic

Authored by efriedma on May 14 2020, 2:50 PM.

Details

Reviewers
jdoerfert
mehdi_amini
sstefan1
Commits
rG11aa3707e30f: StoreInst should store Align, not MaybeAlign
Summary

This is D77454, except for stores. All the infrastructure work was done for loads, so the remaining changes necessary are relatively small.

Diff Detail

Event Timeline

efriedma created this revision.May 14 2020, 2:50 PM
Herald added a reviewer: sstefan1. · View Herald TranscriptMay 14 2020, 2:50 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald Transcript
Herald added subscribers: cfe-commits, kuter, dantrushin and 12 others. · View Herald Transcript
Harbormaster failed remote builds in B56795: Diff 264107!May 14 2020, 4:54 PM
jdoerfert accepted this revision.May 14 2020, 8:48 PM

LGTM, two minor things below.

clang/lib/CodeGen/CGExpr.cpp
130

Nit: I guess /* volatile */ false

llvm/lib/IR/Instructions.cpp
1422

Minor: Do we want toe keep the name? computeAccessAlign maybe? Or a shallow computeStoreAlign wrapper? No strong feelings, just odd.

This revision is now accepted and ready to land.May 14 2020, 8:48 PM
Closed by commit rG11aa3707e30f: StoreInst should store Align, not MaybeAlign (authored by efriedma). · Explain WhyMay 15 2020, 12:32 PM
This revision was automatically updated to reflect the committed changes.
efriedma mentioned this in rG1a6e4a2cf68b: Fix polly tests after D79968..May 15 2020, 3:16 PM
efriedma mentioned this in D80044: AllocaInst should store Align instead of MaybeAlign..May 15 2020, 3:59 PM
efriedma mentioned this in rG4f04db4b5439: AllocaInst should store Align instead of MaybeAlign..May 16 2020, 3:22 PM

Revision Contents

PathSize
clang/
lib/
CodeGen/
4 lines
llvm/
examples/
ThinLtoJIT/
2 lines
include/
llvm/
IR/
23 lines
lib/
AsmParser/
6 lines
Bitcode/
Reader/
8 lines
CodeGen/
5 lines
GlobalISel/
6 lines
SelectionDAG/
2 lines
3 lines
IR/
2 lines
39 lines
Target/
AMDGPU/
4 lines
NVPTX/
2 lines
Transforms/
InstCombine/
14 lines
6 lines
Scalar/
5 lines
5 lines
14 lines
Utils/
3 lines
test/
Analysis/
CostModel/
AArch64/
2 lines
MemorySSA/
4 lines
Bitcode/
4 lines
Feature/
2 lines
Instrumentation/
MemorySanitizer/
4 lines
Transforms/
Attributor/
IPConstantProp/
4 lines
4 lines
4 lines
6 lines
4 lines
2 lines
CodeGenPrepare/
X86/
4 lines
CorrelatedValuePropagation/
4 lines
DeadStoreElimination/
MSSA/
6 lines
24 lines
38 lines
6 lines
42 lines
4 lines
28 lines
22 lines
EarlyCSE/
72 lines
4 lines
16 lines
GVN/
2 lines
42 lines
68 lines
InstCombine/
2 lines
2 lines
InterleavedAccess/
ARM/
6 lines
LoopIdiom/
X86/
4 lines
LoopUnroll/
20 lines
NewGVN/
6 lines
12 lines
6 lines
14 lines
SLPVectorizer/
X86/
8 lines
Util/
22 lines
Verifier/
40 lines

Diff 264316

clang/lib/CodeGen/CGExpr.cpp

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 LinesAddress CodeGenFunction::CreateDefaultAlignTempAlloca(llvm::Type *Ty,
const Twine &Name) { const Twine &Name) {
CharUnits Align = CharUnits Align =
CharUnits::fromQuantity(CGM.getDataLayout().getABITypeAlignment(Ty)); CharUnits::fromQuantity(CGM.getDataLayout().getABITypeAlignment(Ty));
return CreateTempAlloca(Ty, Align, Name); return CreateTempAlloca(Ty, Align, Name);
} }
void CodeGenFunction::InitTempAlloca(Address Var, llvm::Value *Init) { void CodeGenFunction::InitTempAlloca(Address Var, llvm::Value *Init) {
assert(isa<llvm::AllocaInst>(Var.getPointer())); assert(isa<llvm::AllocaInst>(Var.getPointer()));
auto *Store = new llvm::StoreInst(Init, Var.getPointer()); auto *Store = new llvm::StoreInst(Init, Var.getPointer(), /*volatile*/ false,
Store->setAlignment(Var.getAlignment().getAsAlign()); Var.getAlignment().getAsAlign());
jdoerfertUnsubmitted
Not Done
ReplyInline Actions

Nit: I guess /* volatile */ false

jdoerfert: Nit: I guess `/* volatile */ false`
llvm::BasicBlock *Block = AllocaInsertPt->getParent(); llvm::BasicBlock *Block = AllocaInsertPt->getParent();
Block->getInstList().insertAfter(AllocaInsertPt->getIterator(), Store); Block->getInstList().insertAfter(AllocaInsertPt->getIterator(), Store);
} }
Address CodeGenFunction::CreateIRTemp(QualType Ty, const Twine &Name) { Address CodeGenFunction::CreateIRTemp(QualType Ty, const Twine &Name) {
CharUnits Align = getContext().getTypeAlignInChars(Ty); CharUnits Align = getContext().getTypeAlignInChars(Ty);
return CreateTempAlloca(ConvertType(Ty), Align, Name); return CreateTempAlloca(ConvertType(Ty), Align, Name);
} }
▲ Show 20 Lines • Show All 5,151 Lines • Show Last 20 Lines

llvm/examples/ThinLtoJIT/ThinLtoInstrumentationLayer.cpp

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines if (MemFence & ThinLtoJIT::FenceJITedCode) {
static constexpr bool IsVolatile = true; static constexpr bool IsVolatile = true;
static constexpr Instruction *NoInsertBefore = nullptr; static constexpr Instruction *NoInsertBefore = nullptr;
auto SyncFlagAddr = pointerToJITTargetAddress(&FlagsSync); auto SyncFlagAddr = pointerToJITTargetAddress(&FlagsSync);
B.Insert( B.Insert(
new StoreInst(ConstantInt::get(Int64Ty, 0), new StoreInst(ConstantInt::get(Int64Ty, 0),
B.CreateIntToPtr(ConstantInt::get(Int64Ty, SyncFlagAddr), B.CreateIntToPtr(ConstantInt::get(Int64Ty, SyncFlagAddr),
Int64Ty->getPointerTo()), Int64Ty->getPointerTo()),
IsVolatile, MaybeAlign(64), AtomicOrdering::Release, IsVolatile, Align(64), AtomicOrdering::Release,
SyncScope::System, NoInsertBefore)); SyncScope::System, NoInsertBefore));
} }
} }
void ThinLtoInstrumentationLayer::dump(raw_ostream &OS) { void ThinLtoInstrumentationLayer::dump(raw_ostream &OS) {
OS << "Discovery flags stats\n"; OS << "Discovery flags stats\n";
unsigned NumFlagsFired = 0; unsigned NumFlagsFired = 0;
Show All 23 Lines

llvm/include/llvm/IR/Instructions.h

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Linesprotected:
// Note: Instruction needs to be a friend here to call cloneImpl. // Note: Instruction needs to be a friend here to call cloneImpl.
friend class Instruction; friend class Instruction;
StoreInst *cloneImpl() const; StoreInst *cloneImpl() const;
public: public:
StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore); StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore);
StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd); StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd);
StoreInst(Value *Val, Value *Ptr, bool isVolatile = false, StoreInst(Value *Val, Value *Ptr, bool isVolatile, Instruction *InsertBefore);
Instruction *InsertBefore = nullptr);
StoreInst(Value *Val, Value *Ptr, bool isVolatile, BasicBlock *InsertAtEnd); StoreInst(Value *Val, Value *Ptr, bool isVolatile, BasicBlock *InsertAtEnd);
StoreInst(Value *Val, Value *Ptr, bool isVolatile, MaybeAlign Align, StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align,
Instruction *InsertBefore = nullptr); Instruction *InsertBefore = nullptr);
StoreInst(Value *Val, Value *Ptr, bool isVolatile, MaybeAlign Align, StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align,
BasicBlock *InsertAtEnd); BasicBlock *InsertAtEnd);
StoreInst(Value *Val, Value *Ptr, bool isVolatile, MaybeAlign Align, StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align,
AtomicOrdering Order, SyncScope::ID SSID = SyncScope::System, AtomicOrdering Order, SyncScope::ID SSID = SyncScope::System,
Instruction *InsertBefore = nullptr); Instruction *InsertBefore = nullptr);
StoreInst(Value *Val, Value *Ptr, bool isVolatile, MaybeAlign Align, StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align,
AtomicOrdering Order, SyncScope::ID SSID, BasicBlock *InsertAtEnd); AtomicOrdering Order, SyncScope::ID SSID, BasicBlock *InsertAtEnd);
// allocate space for exactly two operands // allocate space for exactly two operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 2); return User::operator new(s, 2);
} }
/// Return true if this is a store to a volatile memory location. /// Return true if this is a store to a volatile memory location.
bool isVolatile() const { return getSubclassDataFromInstruction() & 1; } bool isVolatile() const { return getSubclassDataFromInstruction() & 1; }
/// Specify whether this is a volatile store or not. /// Specify whether this is a volatile store or not.
void setVolatile(bool V) { void setVolatile(bool V) {
setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) | setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) |
(V ? 1 : 0)); (V ? 1 : 0));
} }
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// Return the alignment of the access that is being performed /// Return the alignment of the access that is being performed
/// FIXME: Remove this function once transition to Align is over. /// FIXME: Remove this function once transition to Align is over.
/// Use getAlign() instead. /// Use getAlign() instead.
unsigned getAlignment() const { unsigned getAlignment() const { return getAlign().value(); }
if (const auto MA = getAlign())
return MA->value();
return 0;
}
MaybeAlign getAlign() const { Align getAlign() const {
return decodeMaybeAlign((getSubclassDataFromInstruction() >> 1) & 31); return *decodeMaybeAlign((getSubclassDataFromInstruction() >> 1) & 31);
} }
void setAlignment(MaybeAlign Alignment); void setAlignment(Align Alignment);
/// Returns the ordering constraint of this store instruction. /// Returns the ordering constraint of this store instruction.
AtomicOrdering getOrdering() const { AtomicOrdering getOrdering() const {
return AtomicOrdering((getSubclassDataFromInstruction() >> 7) & 7); return AtomicOrdering((getSubclassDataFromInstruction() >> 7) & 7);
} }
/// Sets the ordering constraint of this store instruction. May not be /// Sets the ordering constraint of this store instruction. May not be
/// Acquire or AcquireRelease. /// Acquire or AcquireRelease.
▲ Show 20 Lines • Show All 4,854 Lines • Show Last 20 Lines

llvm/lib/AsmParser/LLParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,106 Lines • ▼ Show 20 Lines if (!Val->getType()->isFirstClassType())
return Error(Loc, "store operand must be a first class value"); return Error(Loc, "store operand must be a first class value");
if (cast<PointerType>(Ptr->getType())->getElementType() != Val->getType()) if (cast<PointerType>(Ptr->getType())->getElementType() != Val->getType())
return Error(Loc, "stored value and pointer type do not match"); return Error(Loc, "stored value and pointer type do not match");
if (isAtomic && !Alignment) if (isAtomic && !Alignment)
return Error(Loc, "atomic store must have explicit non-zero alignment"); return Error(Loc, "atomic store must have explicit non-zero alignment");
if (Ordering == AtomicOrdering::Acquire || if (Ordering == AtomicOrdering::Acquire ||
Ordering == AtomicOrdering::AcquireRelease) Ordering == AtomicOrdering::AcquireRelease)
return Error(Loc, "atomic store cannot use Acquire ordering"); return Error(Loc, "atomic store cannot use Acquire ordering");
if (!Alignment && !Val->getType()->isSized())
return Error(Loc, "storing unsized types is not allowed");
if (!Alignment)
Alignment = M->getDataLayout().getABITypeAlign(Val->getType());
Inst = new StoreInst(Val, Ptr, isVolatile, Alignment, Ordering, SSID); Inst = new StoreInst(Val, Ptr, isVolatile, *Alignment, Ordering, SSID);
return AteExtraComma ? InstExtraComma : InstNormal; return AteExtraComma ? InstExtraComma : InstNormal;
} }
/// ParseCmpXchg /// ParseCmpXchg
/// ::= 'cmpxchg' 'weak'? 'volatile'? TypeAndValue ',' TypeAndValue ',' /// ::= 'cmpxchg' 'weak'? 'volatile'? TypeAndValue ',' TypeAndValue ','
/// TypeAndValue 'singlethread'? AtomicOrdering AtomicOrdering /// TypeAndValue 'singlethread'? AtomicOrdering AtomicOrdering
int LLParser::ParseCmpXchg(Instruction *&Inst, PerFunctionState &PFS) { int LLParser::ParseCmpXchg(Instruction *&Inst, PerFunctionState &PFS) {
Value *Ptr, *Cmp, *New; LocTy PtrLoc, CmpLoc, NewLoc; Value *Ptr, *Cmp, *New; LocTy PtrLoc, CmpLoc, NewLoc;
▲ Show 20 Lines • Show All 1,886 Lines • Show Last 20 Lines

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

Show First 20 Lines • Show All 4,916 Lines • ▼ Show 20 Lines case bitc::FUNC_CODE_INST_STORE_OLD: { // STORE2:[ptrty, ptr, val, align, vol]
OpNum + 2 != Record.size()) OpNum + 2 != Record.size())
return error("Invalid record"); return error("Invalid record");
if (Error Err = typeCheckLoadStoreInst(Val->getType(), Ptr->getType())) if (Error Err = typeCheckLoadStoreInst(Val->getType(), Ptr->getType()))
return Err; return Err;
MaybeAlign Align; MaybeAlign Align;
if (Error Err = parseAlignmentValue(Record[OpNum], Align)) if (Error Err = parseAlignmentValue(Record[OpNum], Align))
return Err; return Err;
I = new StoreInst(Val, Ptr, Record[OpNum + 1], Align); if (!Align)
Align = TheModule->getDataLayout().getABITypeAlign(Val->getType());
I = new StoreInst(Val, Ptr, Record[OpNum + 1], *Align);
InstructionList.push_back(I); InstructionList.push_back(I);
break; break;
} }
case bitc::FUNC_CODE_INST_STOREATOMIC: case bitc::FUNC_CODE_INST_STOREATOMIC:
case bitc::FUNC_CODE_INST_STOREATOMIC_OLD: { case bitc::FUNC_CODE_INST_STOREATOMIC_OLD: {
// STOREATOMIC: [ptrty, ptr, val, align, vol, ordering, ssid] // STOREATOMIC: [ptrty, ptr, val, align, vol, ordering, ssid]
unsigned OpNum = 0; unsigned OpNum = 0;
Value *Val, *Ptr; Value *Val, *Ptr;
Show All 16 Lines case bitc::FUNC_CODE_INST_STOREATOMIC_OLD: {
return error("Invalid record"); return error("Invalid record");
SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 3]); SyncScope::ID SSID = getDecodedSyncScopeID(Record[OpNum + 3]);
if (Ordering != AtomicOrdering::NotAtomic && Record[OpNum] == 0) if (Ordering != AtomicOrdering::NotAtomic && Record[OpNum] == 0)
return error("Invalid record"); return error("Invalid record");
MaybeAlign Align; MaybeAlign Align;
if (Error Err = parseAlignmentValue(Record[OpNum], Align)) if (Error Err = parseAlignmentValue(Record[OpNum], Align))
return Err; return Err;
I = new StoreInst(Val, Ptr, Record[OpNum + 1], Align, Ordering, SSID); if (!Align)
return error("Alignment missing from atomic store");
I = new StoreInst(Val, Ptr, Record[OpNum + 1], *Align, Ordering, SSID);
InstructionList.push_back(I); InstructionList.push_back(I);
break; break;
} }
case bitc::FUNC_CODE_INST_CMPXCHG_OLD: case bitc::FUNC_CODE_INST_CMPXCHG_OLD:
case bitc::FUNC_CODE_INST_CMPXCHG: { case bitc::FUNC_CODE_INST_CMPXCHG: {
// CMPXCHG:[ptrty, ptr, cmp, new, vol, successordering, ssid, // CMPXCHG:[ptrty, ptr, cmp, new, vol, successordering, ssid,
// failureordering?, isweak?] // failureordering?, isweak?]
unsigned OpNum = 0; unsigned OpNum = 0;
▲ Show 20 Lines • Show All 1,824 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GCRootLowering.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines if (StoreInst *SI = dyn_cast<StoreInst>(IP))
dyn_cast<AllocaInst>(SI->getOperand(1)->stripPointerCasts())) dyn_cast<AllocaInst>(SI->getOperand(1)->stripPointerCasts()))
InitedRoots.insert(AI); InitedRoots.insert(AI);
// Add root initializers. // Add root initializers.
bool MadeChange = false; bool MadeChange = false;
for (AllocaInst *Root : Roots) for (AllocaInst *Root : Roots)
if (!InitedRoots.count(Root)) { if (!InitedRoots.count(Root)) {
StoreInst *SI = new StoreInst( new StoreInst(
ConstantPointerNull::get(cast<PointerType>(Root->getAllocatedType())), ConstantPointerNull::get(cast<PointerType>(Root->getAllocatedType())),
Root); Root, Root->getNextNode());
SI->insertAfter(Root);
MadeChange = true; MadeChange = true;
} }
return MadeChange; return MadeChange;
} }
/// runOnFunction - Replace gcread/gcwrite intrinsics with loads and stores. /// runOnFunction - Replace gcread/gcwrite intrinsics with loads and stores.
/// Leave gcroot intrinsics; the code generator needs to see those. /// Leave gcroot intrinsics; the code generator needs to see those.
▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 238 Lines • ▼ Show 20 Lines if (!Alignment)
Alignment = DL->getABITypeAlignment(AI.getAllocatedType()); Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
int &FI = FrameIndices[&AI]; int &FI = FrameIndices[&AI];
FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI); FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
return FI; return FI;
} }
Align IRTranslator::getMemOpAlign(const Instruction &I) { Align IRTranslator::getMemOpAlign(const Instruction &I) {
if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) { if (const StoreInst *SI = dyn_cast<StoreInst>(&I))
Type *ValTy = SI->getValueOperand()->getType(); return SI->getAlign();
return SI->getAlign().getValueOr(DL->getABITypeAlign(ValTy));
}
if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) { if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
return DL->getValueOrABITypeAlignment(LI->getAlign(), LI->getType()); return DL->getValueOrABITypeAlignment(LI->getAlign(), LI->getType());
} }
if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) { if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
// TODO(PR27168): This instruction has no alignment attribute, but unlike // TODO(PR27168): This instruction has no alignment attribute, but unlike
// the default alignment for load/store, the default here is to assume // the default alignment for load/store, the default here is to assume
// it has NATURAL alignment, not DataLayout-specified alignment. // it has NATURAL alignment, not DataLayout-specified alignment.
const DataLayout &DL = AI->getModule()->getDataLayout(); const DataLayout &DL = AI->getModule()->getDataLayout();
▲ Show 20 Lines • Show All 2,197 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,610 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
if (I.getAlignment() < MemVT.getSizeInBits() / 8) if (I.getAlignment() < MemVT.getSizeInBits() / 8)
report_fatal_error("Cannot generate unaligned atomic store"); report_fatal_error("Cannot generate unaligned atomic store");
auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineMemOperand *MMO = MF.getMachineMemOperand( MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
*I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering); I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering);
SDValue Val = getValue(I.getValueOperand()); SDValue Val = getValue(I.getValueOperand());
if (Val.getValueType() != MemVT) if (Val.getValueType() != MemVT)
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT); Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT);
SDValue Ptr = getValue(I.getPointerOperand()); SDValue Ptr = getValue(I.getPointerOperand());
if (TLI.lowerAtomicStoreAsStoreSDNode(I)) { if (TLI.lowerAtomicStoreAsStoreSDNode(I)) {
// TODO: Once this is better exercised by tests, it should be merged with // TODO: Once this is better exercised by tests, it should be merged with
▲ Show 20 Lines • Show All 5,942 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SjLjEHPrepare.cpp

Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines for (Instruction &I : BB) {
if (auto *CI = dyn_cast<CallInst>(&I)) { if (auto *CI = dyn_cast<CallInst>(&I)) {
if (CI->getCalledFunction() != StackRestoreFn) if (CI->getCalledFunction() != StackRestoreFn)
continue; continue;
} else if (!isa<AllocaInst>(&I)) { } else if (!isa<AllocaInst>(&I)) {
continue; continue;
} }
Instruction *StackAddr = CallInst::Create(StackAddrFn, "sp"); Instruction *StackAddr = CallInst::Create(StackAddrFn, "sp");
StackAddr->insertAfter(&I); StackAddr->insertAfter(&I);
Instruction *StoreStackAddr = new StoreInst(StackAddr, StackPtr, true); new StoreInst(StackAddr, StackPtr, true, StackAddr->getNextNode());
StoreStackAddr->insertAfter(StackAddr);
} }
} }
// Finally, for any returns from this function, if this function contains an // Finally, for any returns from this function, if this function contains an
// invoke, add a call to unregister the function context. // invoke, add a call to unregister the function context.
for (ReturnInst *Return : Returns) for (ReturnInst *Return : Returns)
CallInst::Create(UnregisterFn, FuncCtx, "", Return); CallInst::Create(UnregisterFn, FuncCtx, "", Return);
Show All 26 Lines

llvm/lib/IR/Core.cpp

Show First 20 Lines • Show All 2,019 Lines • ▼ Show 20 Linesvoid LLVMSetAlignment(LLVMValueRef V, unsigned Bytes) {
Value *P = unwrap<Value>(V); Value *P = unwrap<Value>(V);
if (GlobalObject *GV = dyn_cast<GlobalObject>(P)) if (GlobalObject *GV = dyn_cast<GlobalObject>(P))
GV->setAlignment(MaybeAlign(Bytes)); GV->setAlignment(MaybeAlign(Bytes));
else if (AllocaInst *AI = dyn_cast<AllocaInst>(P)) else if (AllocaInst *AI = dyn_cast<AllocaInst>(P))
AI->setAlignment(MaybeAlign(Bytes)); AI->setAlignment(MaybeAlign(Bytes));
else if (LoadInst *LI = dyn_cast<LoadInst>(P)) else if (LoadInst *LI = dyn_cast<LoadInst>(P))
LI->setAlignment(Align(Bytes)); LI->setAlignment(Align(Bytes));
else if (StoreInst *SI = dyn_cast<StoreInst>(P)) else if (StoreInst *SI = dyn_cast<StoreInst>(P))
SI->setAlignment(MaybeAlign(Bytes)); SI->setAlignment(Align(Bytes));
else else
llvm_unreachable( llvm_unreachable(
"only GlobalValue, AllocaInst, LoadInst and StoreInst have alignment"); "only GlobalValue, AllocaInst, LoadInst and StoreInst have alignment");
} }
LLVMValueMetadataEntry *LLVMGlobalCopyAllMetadata(LLVMValueRef Value, LLVMValueMetadataEntry *LLVMGlobalCopyAllMetadata(LLVMValueRef Value,
size_t *NumEntries) { size_t *NumEntries) {
return llvm_getMetadata(NumEntries, [&Value](MetadataEntries &Entries) { return llvm_getMetadata(NumEntries, [&Value](MetadataEntries &Entries) {
▲ Show 20 Lines • Show All 2,088 Lines • Show Last 20 Lines

llvm/lib/IR/Instructions.cpp

Show First 20 Lines • Show All 1,320 Lines • ▼ Show 20 Lines
void LoadInst::AssertOK() { void LoadInst::AssertOK() {
assert(getOperand(0)->getType()->isPointerTy() && assert(getOperand(0)->getType()->isPointerTy() &&
"Ptr must have pointer type."); "Ptr must have pointer type.");
assert(!(isAtomic() && getAlignment() == 0) && assert(!(isAtomic() && getAlignment() == 0) &&
"Alignment required for atomic load"); "Alignment required for atomic load");
} }
Align computeLoadAlign(Type *Ty, BasicBlock *BB) { Align computeLoadStoreDefaultAlign(Type *Ty, BasicBlock *BB) {
const DataLayout &DL = BB->getModule()->getDataLayout(); const DataLayout &DL = BB->getModule()->getDataLayout();
return DL.getABITypeAlign(Ty); return DL.getABITypeAlign(Ty);
} }
Align computeLoadAlign(Type *Ty, Instruction *I) { Align computeLoadStoreDefaultAlign(Type *Ty, Instruction *I) {
return computeLoadAlign(Ty, I->getParent()); return computeLoadStoreDefaultAlign(Ty, I->getParent());
} }
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name,
Instruction *InsertBef) Instruction *InsertBef)
: LoadInst(Ty, Ptr, Name, /*isVolatile=*/false, InsertBef) {} : LoadInst(Ty, Ptr, Name, /*isVolatile=*/false, InsertBef) {}
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name,
BasicBlock *InsertAE) BasicBlock *InsertAE)
: LoadInst(Ty, Ptr, Name, /*isVolatile=*/false, InsertAE) {} : LoadInst(Ty, Ptr, Name, /*isVolatile=*/false, InsertAE) {}
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile,
Instruction *InsertBef) Instruction *InsertBef)
: LoadInst(Ty, Ptr, Name, isVolatile, computeLoadAlign(Ty, InsertBef), : LoadInst(Ty, Ptr, Name, isVolatile,
InsertBef) {} computeLoadStoreDefaultAlign(Ty, InsertBef), InsertBef) {}
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile,
BasicBlock *InsertAE) BasicBlock *InsertAE)
: LoadInst(Ty, Ptr, Name, isVolatile, computeLoadAlign(Ty, InsertAE), : LoadInst(Ty, Ptr, Name, isVolatile,
InsertAE) {} computeLoadStoreDefaultAlign(Ty, InsertAE), InsertAE) {}
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile,
Align Align, Instruction *InsertBef) Align Align, Instruction *InsertBef)
: LoadInst(Ty, Ptr, Name, isVolatile, Align, AtomicOrdering::NotAtomic, : LoadInst(Ty, Ptr, Name, isVolatile, Align, AtomicOrdering::NotAtomic,
SyncScope::System, InsertBef) {} SyncScope::System, InsertBef) {}
LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile, LoadInst::LoadInst(Type *Ty, Value *Ptr, const Twine &Name, bool isVolatile,
Align Align, BasicBlock *InsertAE) Align Align, BasicBlock *InsertAE)
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StoreInst::StoreInst(Value *val, Value *addr, Instruction *InsertBefore) StoreInst::StoreInst(Value *val, Value *addr, Instruction *InsertBefore)
: StoreInst(val, addr, /*isVolatile=*/false, InsertBefore) {} : StoreInst(val, addr, /*isVolatile=*/false, InsertBefore) {}
StoreInst::StoreInst(Value *val, Value *addr, BasicBlock *InsertAtEnd) StoreInst::StoreInst(Value *val, Value *addr, BasicBlock *InsertAtEnd)
: StoreInst(val, addr, /*isVolatile=*/false, InsertAtEnd) {} : StoreInst(val, addr, /*isVolatile=*/false, InsertAtEnd) {}
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile,
Instruction *InsertBefore) Instruction *InsertBefore)
: StoreInst(val, addr, isVolatile, /*Align=*/None, InsertBefore) {} : StoreInst(val, addr, isVolatile,
computeLoadStoreDefaultAlign(val->getType(), InsertBefore),
jdoerfertUnsubmitted
Not Done
ReplyInline Actions

Minor: Do we want toe keep the name? computeAccessAlign maybe? Or a shallow computeStoreAlign wrapper? No strong feelings, just odd.

jdoerfert: Minor: Do we want toe keep the name? `computeAccessAlign` maybe? Or a shallow…
InsertBefore) {}
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile,
BasicBlock *InsertAtEnd) BasicBlock *InsertAtEnd)
: StoreInst(val, addr, isVolatile, /*Align=*/None, InsertAtEnd) {} : StoreInst(val, addr, isVolatile,
computeLoadStoreDefaultAlign(val->getType(), InsertAtEnd),
InsertAtEnd) {}
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, MaybeAlign Align, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, Align Align,
Instruction *InsertBefore) Instruction *InsertBefore)
: StoreInst(val, addr, isVolatile, Align, AtomicOrdering::NotAtomic, : StoreInst(val, addr, isVolatile, Align, AtomicOrdering::NotAtomic,
SyncScope::System, InsertBefore) {} SyncScope::System, InsertBefore) {}
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, MaybeAlign Align, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, Align Align,
BasicBlock *InsertAtEnd) BasicBlock *InsertAtEnd)
: StoreInst(val, addr, isVolatile, Align, AtomicOrdering::NotAtomic, : StoreInst(val, addr, isVolatile, Align, AtomicOrdering::NotAtomic,
SyncScope::System, InsertAtEnd) {} SyncScope::System, InsertAtEnd) {}
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, MaybeAlign Align, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, Align Align,
AtomicOrdering Order, SyncScope::ID SSID, AtomicOrdering Order, SyncScope::ID SSID,
Instruction *InsertBefore) Instruction *InsertBefore)
: Instruction(Type::getVoidTy(val->getContext()), Store, : Instruction(Type::getVoidTy(val->getContext()), Store,
OperandTraits<StoreInst>::op_begin(this), OperandTraits<StoreInst>::op_begin(this),
OperandTraits<StoreInst>::operands(this), InsertBefore) { OperandTraits<StoreInst>::operands(this), InsertBefore) {
Op<0>() = val; Op<0>() = val;
Op<1>() = addr; Op<1>() = addr;
setVolatile(isVolatile); setVolatile(isVolatile);
setAlignment(Align); setAlignment(Align);
setAtomic(Order, SSID); setAtomic(Order, SSID);
AssertOK(); AssertOK();
} }
StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, MaybeAlign Align, StoreInst::StoreInst(Value *val, Value *addr, bool isVolatile, Align Align,
AtomicOrdering Order, SyncScope::ID SSID, AtomicOrdering Order, SyncScope::ID SSID,
BasicBlock *InsertAtEnd) BasicBlock *InsertAtEnd)
: Instruction(Type::getVoidTy(val->getContext()), Store, : Instruction(Type::getVoidTy(val->getContext()), Store,
OperandTraits<StoreInst>::op_begin(this), OperandTraits<StoreInst>::op_begin(this),
OperandTraits<StoreInst>::operands(this), InsertAtEnd) { OperandTraits<StoreInst>::operands(this), InsertAtEnd) {
Op<0>() = val; Op<0>() = val;
Op<1>() = addr; Op<1>() = addr;
setVolatile(isVolatile); setVolatile(isVolatile);
setAlignment(Align); setAlignment(Align);
setAtomic(Order, SSID); setAtomic(Order, SSID);
AssertOK(); AssertOK();
} }
void StoreInst::setAlignment(MaybeAlign Alignment) { void StoreInst::setAlignment(Align Alignment) {
assert((!Alignment || *Alignment <= MaximumAlignment) && assert(Alignment <= MaximumAlignment &&
"Alignment is greater than MaximumAlignment!"); "Alignment is greater than MaximumAlignment!");
setInstructionSubclassData((getSubclassDataFromInstruction() & ~(31 << 1)) | setInstructionSubclassData((getSubclassDataFromInstruction() & ~(31 << 1)) |
(encode(Alignment) << 1)); (encode(Alignment) << 1));
assert(getAlign() == Alignment && "Alignment representation error!"); assert(getAlign() == Alignment && "Alignment representation error!");
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AtomicCmpXchgInst Implementation // AtomicCmpXchgInst Implementation
▲ Show 20 Lines • Show All 2,768 Lines • ▼ Show 20 Lines
} }
LoadInst *LoadInst::cloneImpl() const { LoadInst *LoadInst::cloneImpl() const {
return new LoadInst(getType(), getOperand(0), Twine(), isVolatile(), return new LoadInst(getType(), getOperand(0), Twine(), isVolatile(),
getAlign(), getOrdering(), getSyncScopeID()); getAlign(), getOrdering(), getSyncScopeID());
} }
StoreInst *StoreInst::cloneImpl() const { StoreInst *StoreInst::cloneImpl() const {
return new StoreInst(getOperand(0), getOperand(1), isVolatile(), return new StoreInst(getOperand(0), getOperand(1), isVolatile(), getAlign(),
MaybeAlign(getAlignment()), getOrdering(), getOrdering(), getSyncScopeID());
getSyncScopeID());
} }
AtomicCmpXchgInst *AtomicCmpXchgInst::cloneImpl() const { AtomicCmpXchgInst *AtomicCmpXchgInst::cloneImpl() const {
AtomicCmpXchgInst *Result = AtomicCmpXchgInst *Result =
new AtomicCmpXchgInst(getOperand(0), getOperand(1), getOperand(2), new AtomicCmpXchgInst(getOperand(0), getOperand(1), getOperand(2),
getSuccessOrdering(), getFailureOrdering(), getSuccessOrdering(), getFailureOrdering(),
getSyncScopeID()); getSyncScopeID());
Result->setVolatile(isVolatile()); Result->setVolatile(isVolatile());
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llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp

Show First 20 Lines • Show All 381 Lines • ▼ Show 20 Lines if (ConstExpr) {
GetElementPtrInst *BufferIdx = GetElementPtrInst *BufferIdx =
dyn_cast<GetElementPtrInst>(GetElementPtrInst::Create( dyn_cast<GetElementPtrInst>(GetElementPtrInst::Create(
nullptr, pcall, ZeroIdxList, "PrintBuffID", Brnch)); nullptr, pcall, ZeroIdxList, "PrintBuffID", Brnch));
Type *idPointer = PointerType::get(I32Ty, AMDGPUAS::GLOBAL_ADDRESS); Type *idPointer = PointerType::get(I32Ty, AMDGPUAS::GLOBAL_ADDRESS);
Value *id_gep_cast = Value *id_gep_cast =
new BitCastInst(BufferIdx, idPointer, "PrintBuffIdCast", Brnch); new BitCastInst(BufferIdx, idPointer, "PrintBuffIdCast", Brnch);
StoreInst *stbuff = new StoreInst(ConstantInt::get(I32Ty, UniqID), id_gep_cast, Brnch);
new StoreInst(ConstantInt::get(I32Ty, UniqID), id_gep_cast);
stbuff->insertBefore(Brnch); // to Remove unused variable warning
SmallVector<Value *, 2> FourthIdxList; SmallVector<Value *, 2> FourthIdxList;
ConstantInt *fourInt = ConstantInt *fourInt =
ConstantInt::get(Ctx, APInt(32, StringRef("4"), 10)); ConstantInt::get(Ctx, APInt(32, StringRef("4"), 10));
FourthIdxList.push_back(fourInt); // 1st 4 bytes hold the printf_id FourthIdxList.push_back(fourInt); // 1st 4 bytes hold the printf_id
// the following GEP is the buffer pointer // the following GEP is the buffer pointer
BufferIdx = cast<GetElementPtrInst>(GetElementPtrInst::Create( BufferIdx = cast<GetElementPtrInst>(GetElementPtrInst::Create(
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llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines for (LoadInst *LI : AggrLoads) {
unsigned NumLoads = DL.getTypeStoreSize(LI->getType()); unsigned NumLoads = DL.getTypeStoreSize(LI->getType());
ConstantInt *CopyLen = ConstantInt *CopyLen =
ConstantInt::get(Type::getInt32Ty(Context), NumLoads); ConstantInt::get(Type::getInt32Ty(Context), NumLoads);
createMemCpyLoopKnownSize(/* ConvertedInst */ SI, createMemCpyLoopKnownSize(/* ConvertedInst */ SI,
/* SrcAddr */ SrcAddr, /* DstAddr */ DstAddr, /* SrcAddr */ SrcAddr, /* DstAddr */ DstAddr,
/* CopyLen */ CopyLen, /* CopyLen */ CopyLen,
/* SrcAlign */ LI->getAlign(), /* SrcAlign */ LI->getAlign(),
/* DestAlign */ SI->getAlign().valueOrOne(), /* DestAlign */ SI->getAlign(),
/* SrcIsVolatile */ LI->isVolatile(), /* SrcIsVolatile */ LI->isVolatile(),
/* DstIsVolatile */ SI->isVolatile(), TTI); /* DstIsVolatile */ SI->isVolatile(), TTI);
SI->eraseFromParent(); SI->eraseFromParent();
LI->eraseFromParent(); LI->eraseFromParent();
} }
// Transform mem* intrinsic calls. // Transform mem* intrinsic calls.
Show All 27 Lines

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 LinesInstruction *InstCombiner::SimplifyAnyMemTransfer(AnyMemTransferInst *MI) {
if (Size > 8 || (Size&(Size-1))) if (Size > 8 || (Size&(Size-1)))
return nullptr; // If not 1/2/4/8 bytes, exit. return nullptr; // If not 1/2/4/8 bytes, exit.
// If it is an atomic and alignment is less than the size then we will // If it is an atomic and alignment is less than the size then we will
// introduce the unaligned memory access which will be later transformed // introduce the unaligned memory access which will be later transformed
// into libcall in CodeGen. This is not evident performance gain so disable // into libcall in CodeGen. This is not evident performance gain so disable
// it now. // it now.
if (isa<AtomicMemTransferInst>(MI)) if (isa<AtomicMemTransferInst>(MI))
if (CopyDstAlign < Size || CopySrcAlign < Size) if (*CopyDstAlign < Size || *CopySrcAlign < Size)
return nullptr; return nullptr;
// Use an integer load+store unless we can find something better. // Use an integer load+store unless we can find something better.
unsigned SrcAddrSp = unsigned SrcAddrSp =
cast<PointerType>(MI->getArgOperand(1)->getType())->getAddressSpace(); cast<PointerType>(MI->getArgOperand(1)->getType())->getAddressSpace();
unsigned DstAddrSp = unsigned DstAddrSp =
cast<PointerType>(MI->getArgOperand(0)->getType())->getAddressSpace(); cast<PointerType>(MI->getArgOperand(0)->getType())->getAddressSpace();
Show All 30 LinesInstruction *InstCombiner::SimplifyAnyMemTransfer(AnyMemTransferInst *MI) {
if (LoopMemParallelMD) if (LoopMemParallelMD)
L->setMetadata(LLVMContext::MD_mem_parallel_loop_access, LoopMemParallelMD); L->setMetadata(LLVMContext::MD_mem_parallel_loop_access, LoopMemParallelMD);
MDNode *AccessGroupMD = MI->getMetadata(LLVMContext::MD_access_group); MDNode *AccessGroupMD = MI->getMetadata(LLVMContext::MD_access_group);
if (AccessGroupMD) if (AccessGroupMD)
L->setMetadata(LLVMContext::MD_access_group, AccessGroupMD); L->setMetadata(LLVMContext::MD_access_group, AccessGroupMD);
StoreInst *S = Builder.CreateStore(L, Dest); StoreInst *S = Builder.CreateStore(L, Dest);
// Alignment from the mem intrinsic will be better, so use it. // Alignment from the mem intrinsic will be better, so use it.
S->setAlignment( S->setAlignment(*CopyDstAlign);
MaybeAlign(CopyDstAlign)); // FIXME: Check if we can use Align instead.
if (CopyMD) if (CopyMD)
S->setMetadata(LLVMContext::MD_tbaa, CopyMD); S->setMetadata(LLVMContext::MD_tbaa, CopyMD);
if (LoopMemParallelMD) if (LoopMemParallelMD)
S->setMetadata(LLVMContext::MD_mem_parallel_loop_access, LoopMemParallelMD); S->setMetadata(LLVMContext::MD_mem_parallel_loop_access, LoopMemParallelMD);
if (AccessGroupMD) if (AccessGroupMD)
S->setMetadata(LLVMContext::MD_access_group, AccessGroupMD); S->setMetadata(LLVMContext::MD_access_group, AccessGroupMD);
if (auto *MT = dyn_cast<MemTransferInst>(MI)) { if (auto *MT = dyn_cast<MemTransferInst>(MI)) {
▲ Show 20 Lines • Show All 919 Lines • ▼ Show 20 LinesInstruction *InstCombiner::simplifyMaskedStore(IntrinsicInst &II) {
// If the mask is all zeros, this instruction does nothing. // If the mask is all zeros, this instruction does nothing.
if (ConstMask->isNullValue()) if (ConstMask->isNullValue())
return eraseInstFromFunction(II); return eraseInstFromFunction(II);
// If the mask is all ones, this is a plain vector store of the 1st argument. // If the mask is all ones, this is a plain vector store of the 1st argument.
if (ConstMask->isAllOnesValue()) { if (ConstMask->isAllOnesValue()) {
Value *StorePtr = II.getArgOperand(1); Value *StorePtr = II.getArgOperand(1);
MaybeAlign Alignment( Align Alignment(cast<ConstantInt>(II.getArgOperand(2))->getZExtValue());
cast<ConstantInt>(II.getArgOperand(2))->getZExtValue());
return new StoreInst(II.getArgOperand(0), StorePtr, false, Alignment); return new StoreInst(II.getArgOperand(0), StorePtr, false, Alignment);
} }
// Use masked off lanes to simplify operands via SimplifyDemandedVectorElts // Use masked off lanes to simplify operands via SimplifyDemandedVectorElts
APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask); APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask);
APInt UndefElts(DemandedElts.getBitWidth(), 0); APInt UndefElts(DemandedElts.getBitWidth(), 0);
if (Value *V = SimplifyDemandedVectorElts(II.getOperand(0), if (Value *V = SimplifyDemandedVectorElts(II.getOperand(0),
DemandedElts, UndefElts)) DemandedElts, UndefElts))
▲ Show 20 Lines • Show All 1,320 Lines • ▼ Show 20 LinesInstruction *InstCombiner::visitCallInst(CallInst &CI) {
case Intrinsic::ppc_altivec_stvx: case Intrinsic::ppc_altivec_stvx:
case Intrinsic::ppc_altivec_stvxl: case Intrinsic::ppc_altivec_stvxl:
// Turn stvx -> store if the pointer is known aligned. // Turn stvx -> store if the pointer is known aligned.
if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(16), DL, II, &AC, if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(16), DL, II, &AC,
&DT) >= 16) { &DT) >= 16) {
Type *OpPtrTy = Type *OpPtrTy =
PointerType::getUnqual(II->getArgOperand(0)->getType()); PointerType::getUnqual(II->getArgOperand(0)->getType());
Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy); Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy);
return new StoreInst(II->getArgOperand(0), Ptr); return new StoreInst(II->getArgOperand(0), Ptr, false, Align(16));
} }
break; break;
case Intrinsic::ppc_vsx_stxvw4x: case Intrinsic::ppc_vsx_stxvw4x:
case Intrinsic::ppc_vsx_stxvd2x: { case Intrinsic::ppc_vsx_stxvd2x: {
// Turn PPC VSX stores into normal stores. // Turn PPC VSX stores into normal stores.
Type *OpPtrTy = PointerType::getUnqual(II->getArgOperand(0)->getType()); Type *OpPtrTy = PointerType::getUnqual(II->getArgOperand(0)->getType());
Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy); Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy);
return new StoreInst(II->getArgOperand(0), Ptr, false, Align(1)); return new StoreInst(II->getArgOperand(0), Ptr, false, Align(1));
Show All 25 Lines case Intrinsic::ppc_qpx_qvstfs:
if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(16), DL, II, &AC, if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(16), DL, II, &AC,
&DT) >= 16) { &DT) >= 16) {
Type *VTy = VectorType::get( Type *VTy = VectorType::get(
Builder.getFloatTy(), Builder.getFloatTy(),
cast<VectorType>(II->getArgOperand(0)->getType())->getElementCount()); cast<VectorType>(II->getArgOperand(0)->getType())->getElementCount());
Value *TOp = Builder.CreateFPTrunc(II->getArgOperand(0), VTy); Value *TOp = Builder.CreateFPTrunc(II->getArgOperand(0), VTy);
Type *OpPtrTy = PointerType::getUnqual(VTy); Type *OpPtrTy = PointerType::getUnqual(VTy);
Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy); Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy);
return new StoreInst(TOp, Ptr); return new StoreInst(TOp, Ptr, false, Align(16));
} }
break; break;
case Intrinsic::ppc_qpx_qvstfd: case Intrinsic::ppc_qpx_qvstfd:
// Turn PPC QPX qvstfd -> store if the pointer is known aligned. // Turn PPC QPX qvstfd -> store if the pointer is known aligned.
if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(32), DL, II, &AC, if (getOrEnforceKnownAlignment(II->getArgOperand(1), Align(32), DL, II, &AC,
&DT) >= 32) { &DT) >= 32) {
Type *OpPtrTy = Type *OpPtrTy =
PointerType::getUnqual(II->getArgOperand(0)->getType()); PointerType::getUnqual(II->getArgOperand(0)->getType());
Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy); Value *Ptr = Builder.CreateBitCast(II->getArgOperand(1), OpPtrTy);
return new StoreInst(II->getArgOperand(0), Ptr); return new StoreInst(II->getArgOperand(0), Ptr, false, Align(32));
} }
break; break;
case Intrinsic::x86_bmi_bextr_32: case Intrinsic::x86_bmi_bextr_32:
case Intrinsic::x86_bmi_bextr_64: case Intrinsic::x86_bmi_bextr_64:
case Intrinsic::x86_tbm_bextri_u32: case Intrinsic::x86_tbm_bextri_u32:
case Intrinsic::x86_tbm_bextri_u64: case Intrinsic::x86_tbm_bextri_u64:
// If the RHS is a constant we can try some simplifications. // If the RHS is a constant we can try some simplifications.
▲ Show 20 Lines • Show All 2,549 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

Show First 20 Lines • Show All 1,565 Lines • ▼ Show 20 Lines if (MergedVal != SI.getOperand(0)) {
PN->addIncoming(SI.getOperand(0), SI.getParent()); PN->addIncoming(SI.getOperand(0), SI.getParent());
PN->addIncoming(OtherStore->getOperand(0), OtherBB); PN->addIncoming(OtherStore->getOperand(0), OtherBB);
MergedVal = InsertNewInstBefore(PN, DestBB->front()); MergedVal = InsertNewInstBefore(PN, DestBB->front());
PN->setDebugLoc(MergedLoc); PN->setDebugLoc(MergedLoc);
} }
// Advance to a place where it is safe to insert the new store and insert it. // Advance to a place where it is safe to insert the new store and insert it.
BBI = DestBB->getFirstInsertionPt(); BBI = DestBB->getFirstInsertionPt();
StoreInst *NewSI = new StoreInst(MergedVal, SI.getOperand(1), SI.isVolatile(), StoreInst *NewSI =
MaybeAlign(SI.getAlignment()), new StoreInst(MergedVal, SI.getOperand(1), SI.isVolatile(), SI.getAlign(),
SI.getOrdering(), SI.getSyncScopeID()); SI.getOrdering(), SI.getSyncScopeID());
InsertNewInstBefore(NewSI, *BBI); InsertNewInstBefore(NewSI, *BBI);
NewSI->setDebugLoc(MergedLoc); NewSI->setDebugLoc(MergedLoc);
// If the two stores had AA tags, merge them. // If the two stores had AA tags, merge them.
AAMDNodes AATags; AAMDNodes AATags;
SI.getAAMetadata(AATags); SI.getAAMetadata(AATags);
if (AATags) { if (AATags) {
OtherStore->getAAMetadata(AATags, /* Merge = */ true); OtherStore->getAAMetadata(AATags, /* Merge = */ true);
NewSI->setAAMetadata(AATags); NewSI->setAAMetadata(AATags);
} }
// Nuke the old stores. // Nuke the old stores.
eraseInstFromFunction(SI); eraseInstFromFunction(SI);
eraseInstFromFunction(*OtherStore); eraseInstFromFunction(*OtherStore);
return true; return true;
} }

llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp

Show First 20 Lines • Show All 1,326 Lines • ▼ Show 20 Lines while (InstDep.isDef() || InstDep.isClobber()) {
APInt Merged = APInt Merged =
(EarlierValue & ~Mask) | (LaterValue << LShiftAmount); (EarlierValue & ~Mask) | (LaterValue << LShiftAmount);
LLVM_DEBUG(dbgs() << "DSE: Merge Stores:\n Earlier: " << *DepWrite LLVM_DEBUG(dbgs() << "DSE: Merge Stores:\n Earlier: " << *DepWrite
<< "\n Later: " << *Inst << "\n Later: " << *Inst
<< "\n Merged Value: " << Merged << '\n'); << "\n Merged Value: " << Merged << '\n');
auto *SI = new StoreInst( auto *SI = new StoreInst(
ConstantInt::get(Earlier->getValueOperand()->getType(), Merged), ConstantInt::get(Earlier->getValueOperand()->getType(), Merged),
Earlier->getPointerOperand(), false, Earlier->getPointerOperand(), false, Earlier->getAlign(),
MaybeAlign(Earlier->getAlignment()), Earlier->getOrdering(), Earlier->getOrdering(), Earlier->getSyncScopeID(), DepWrite);
Earlier->getSyncScopeID(), DepWrite);
unsigned MDToKeep[] = {LLVMContext::MD_dbg, LLVMContext::MD_tbaa, unsigned MDToKeep[] = {LLVMContext::MD_dbg, LLVMContext::MD_tbaa,
LLVMContext::MD_alias_scope, LLVMContext::MD_alias_scope,
LLVMContext::MD_noalias, LLVMContext::MD_noalias,
LLVMContext::MD_nontemporal}; LLVMContext::MD_nontemporal};
SI->copyMetadata(*DepWrite, MDToKeep); SI->copyMetadata(*DepWrite, MDToKeep);
++NumModifiedStores; ++NumModifiedStores;
▲ Show 20 Lines • Show All 737 Lines • Show Last 20 Lines

llvm/lib/Transforms/Scalar/GVNHoist.cpp

Show First 20 Lines • Show All 888 Lines • ▼ Show 20 Linesprivate:
} }
void updateAlignment(Instruction *I, Instruction *Repl) { void updateAlignment(Instruction *I, Instruction *Repl) {
if (auto *ReplacementLoad = dyn_cast<LoadInst>(Repl)) { if (auto *ReplacementLoad = dyn_cast<LoadInst>(Repl)) {
ReplacementLoad->setAlignment( ReplacementLoad->setAlignment(
std::min(ReplacementLoad->getAlign(), cast<LoadInst>(I)->getAlign())); std::min(ReplacementLoad->getAlign(), cast<LoadInst>(I)->getAlign()));
++NumLoadsRemoved; ++NumLoadsRemoved;
} else if (auto *ReplacementStore = dyn_cast<StoreInst>(Repl)) { } else if (auto *ReplacementStore = dyn_cast<StoreInst>(Repl)) {
ReplacementStore->setAlignment( ReplacementStore->setAlignment(std::min(ReplacementStore->getAlign(),
MaybeAlign(std::min(ReplacementStore->getAlignment(), cast<StoreInst>(I)->getAlign()));
cast<StoreInst>(I)->getAlignment())));
++NumStoresRemoved; ++NumStoresRemoved;
} else if (auto *ReplacementAlloca = dyn_cast<AllocaInst>(Repl)) { } else if (auto *ReplacementAlloca = dyn_cast<AllocaInst>(Repl)) {
ReplacementAlloca->setAlignment( ReplacementAlloca->setAlignment(
MaybeAlign(std::max(ReplacementAlloca->getAlignment(), MaybeAlign(std::max(ReplacementAlloca->getAlignment(),
cast<AllocaInst>(I)->getAlignment()))); cast<AllocaInst>(I)->getAlignment())));
} else if (isa<CallInst>(Repl)) { } else if (isa<CallInst>(Repl)) {
++NumCallsRemoved; ++NumCallsRemoved;
} }
▲ Show 20 Lines • Show All 304 Lines • Show Last 20 Lines

llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp

Show First 20 Lines • Show All 1,706 Lines • ▼ Show 20 Lines for (User *U : GCRelocs) {
assert(Relocate->getNextNode() && assert(Relocate->getNextNode() &&
"Should always have one since it's not a terminator"); "Should always have one since it's not a terminator");
IRBuilder<> Builder(Relocate->getNextNode()); IRBuilder<> Builder(Relocate->getNextNode());
Value *CastedRelocatedValue = Value *CastedRelocatedValue =
Builder.CreateBitCast(Relocate, Builder.CreateBitCast(Relocate,
cast<AllocaInst>(Alloca)->getAllocatedType(), cast<AllocaInst>(Alloca)->getAllocatedType(),
suffixed_name_or(Relocate, ".casted", "")); suffixed_name_or(Relocate, ".casted", ""));
StoreInst *Store = new StoreInst(CastedRelocatedValue, Alloca); new StoreInst(CastedRelocatedValue, Alloca,
Store->insertAfter(cast<Instruction>(CastedRelocatedValue)); cast<Instruction>(CastedRelocatedValue)->getNextNode());
#ifndef NDEBUG #ifndef NDEBUG
VisitedLiveValues.insert(OriginalValue); VisitedLiveValues.insert(OriginalValue);
#endif #endif
} }
} }
// Helper function for the "relocationViaAlloca". Similar to the // Helper function for the "relocationViaAlloca". Similar to the
// "insertRelocationStores" but works for rematerialized values. // "insertRelocationStores" but works for rematerialized values.
static void insertRematerializationStores( static void insertRematerializationStores(
const RematerializedValueMapTy &RematerializedValues, const RematerializedValueMapTy &RematerializedValues,
DenseMap<Value *, AllocaInst *> &AllocaMap, DenseMap<Value *, AllocaInst *> &AllocaMap,
DenseSet<Value *> &VisitedLiveValues) { DenseSet<Value *> &VisitedLiveValues) {
for (auto RematerializedValuePair: RematerializedValues) { for (auto RematerializedValuePair: RematerializedValues) {
Instruction *RematerializedValue = RematerializedValuePair.first; Instruction *RematerializedValue = RematerializedValuePair.first;
Value *OriginalValue = RematerializedValuePair.second; Value *OriginalValue = RematerializedValuePair.second;
assert(AllocaMap.count(OriginalValue) && assert(AllocaMap.count(OriginalValue) &&
"Can not find alloca for rematerialized value"); "Can not find alloca for rematerialized value");
Value *Alloca = AllocaMap[OriginalValue]; Value *Alloca = AllocaMap[OriginalValue];
StoreInst *Store = new StoreInst(RematerializedValue, Alloca); new StoreInst(RematerializedValue, Alloca,
Store->insertAfter(RematerializedValue); RematerializedValue->getNextNode());
#ifndef NDEBUG #ifndef NDEBUG
VisitedLiveValues.insert(OriginalValue); VisitedLiveValues.insert(OriginalValue);
#endif #endif
} }
} }
/// Do all the relocation update via allocas and mem2reg /// Do all the relocation update via allocas and mem2reg
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines if (ClobberNonLive) {
} }
ToClobber.push_back(Alloca); ToClobber.push_back(Alloca);
} }
auto InsertClobbersAt = [&](Instruction *IP) { auto InsertClobbersAt = [&](Instruction *IP) {
for (auto *AI : ToClobber) { for (auto *AI : ToClobber) {
auto PT = cast<PointerType>(AI->getAllocatedType()); auto PT = cast<PointerType>(AI->getAllocatedType());
Constant *CPN = ConstantPointerNull::get(PT); Constant *CPN = ConstantPointerNull::get(PT);
StoreInst *Store = new StoreInst(CPN, AI); new StoreInst(CPN, AI, IP);
Store->insertBefore(IP);
} }
}; };
// Insert the clobbering stores. These may get intermixed with the // Insert the clobbering stores. These may get intermixed with the
// gc.results and gc.relocates, but that's fine. // gc.results and gc.relocates, but that's fine.
if (auto II = dyn_cast<InvokeInst>(Statepoint)) { if (auto II = dyn_cast<InvokeInst>(Statepoint)) {
InsertClobbersAt(&*II->getNormalDest()->getFirstInsertionPt()); InsertClobbersAt(&*II->getNormalDest()->getFirstInsertionPt());
InsertClobbersAt(&*II->getUnwindDest()->getFirstInsertionPt()); InsertClobbersAt(&*II->getUnwindDest()->getFirstInsertionPt());
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines for (Instruction *Use : Uses) {
new LoadInst(Alloca->getAllocatedType(), Alloca, "", Use); new LoadInst(Alloca->getAllocatedType(), Alloca, "", Use);
Use->replaceUsesOfWith(Def, Load); Use->replaceUsesOfWith(Def, Load);
} }
} }
// Emit store for the initial gc value. Store must be inserted after load, // Emit store for the initial gc value. Store must be inserted after load,
// otherwise store will be in alloca's use list and an extra load will be // otherwise store will be in alloca's use list and an extra load will be
// inserted before it. // inserted before it.
StoreInst *Store = new StoreInst(Def, Alloca); StoreInst *Store = new StoreInst(Def, Alloca, /*volatile*/ false,
DL.getABITypeAlign(Def->getType()));
if (Instruction *Inst = dyn_cast<Instruction>(Def)) { if (Instruction *Inst = dyn_cast<Instruction>(Def)) {
if (InvokeInst *Invoke = dyn_cast<InvokeInst>(Inst)) { if (InvokeInst *Invoke = dyn_cast<InvokeInst>(Inst)) {
// InvokeInst is a terminator so the store need to be inserted into its // InvokeInst is a terminator so the store need to be inserted into its
// normal destination block. // normal destination block.
BasicBlock *NormalDest = Invoke->getNormalDest(); BasicBlock *NormalDest = Invoke->getNormalDest();
Store->insertBefore(NormalDest->getFirstNonPHI()); Store->insertBefore(NormalDest->getFirstNonPHI());
} else { } else {
assert(!Inst->isTerminator() && assert(!Inst->isTerminator() &&
▲ Show 20 Lines • Show All 994 Lines • Show Last 20 Lines

llvm/lib/Transforms/Utils/CodeExtractor.cpp

Show First 20 Lines • Show All 1,128 Lines • ▼ Show 20 Lines if (AggregateArgs && (inputs.size() + outputs.size() > 0)) {
for (unsigned i = 0, e = inputs.size(); i != e; ++i) { for (unsigned i = 0, e = inputs.size(); i != e; ++i) {
Value *Idx[2]; Value *Idx[2];
Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context)); Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context));
Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), i); Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), i);
GetElementPtrInst *GEP = GetElementPtrInst::Create( GetElementPtrInst *GEP = GetElementPtrInst::Create(
StructArgTy, Struct, Idx, "gep_" + StructValues[i]->getName()); StructArgTy, Struct, Idx, "gep_" + StructValues[i]->getName());
codeReplacer->getInstList().push_back(GEP); codeReplacer->getInstList().push_back(GEP);
StoreInst *SI = new StoreInst(StructValues[i], GEP); new StoreInst(StructValues[i], GEP, codeReplacer);
codeReplacer->getInstList().push_back(SI);
} }
} }
// Emit the call to the function // Emit the call to the function
call = CallInst::Create(newFunction, params, call = CallInst::Create(newFunction, params,
NumExitBlocks > 1 ? "targetBlock" : ""); NumExitBlocks > 1 ? "targetBlock" : "");
// Add debug location to the new call, if the original function has debug // Add debug location to the new call, if the original function has debug
// info. In that case, the terminator of the entry block of the extracted // info. In that case, the terminator of the entry block of the extracted
▲ Show 20 Lines • Show All 613 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/AArch64/store.ll

; RUN: opt < %s -cost-model -analyze -mtriple=aarch64-unknown | FileCheck %s ; RUN: opt < %s -cost-model -analyze -mtriple=aarch64-unknown | FileCheck %s
; RUN: opt < %s -cost-model -analyze -mtriple=aarch64-unknown -mattr=slow-misaligned-128store | FileCheck %s --check-prefix=SLOW_MISALIGNED_128_STORE ; RUN: opt < %s -cost-model -analyze -mtriple=aarch64-unknown -mattr=slow-misaligned-128store | FileCheck %s --check-prefix=SLOW_MISALIGNED_128_STORE
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-v256:32:256-a0:0:32-n32-S32"
; CHECK-LABEL: getMemoryOpCost ; CHECK-LABEL: getMemoryOpCost
; SLOW_MISALIGNED_128_STORE-LABEL: getMemoryOpCost ; SLOW_MISALIGNED_128_STORE-LABEL: getMemoryOpCost
define void @getMemoryOpCost() { define void @getMemoryOpCost() {
; If FeatureSlowMisaligned128Store is set, we penalize 128-bit stores. ; If FeatureSlowMisaligned128Store is set, we penalize 128-bit stores.
; The unlegalized 256-bit stores are further penalized when legalized down ; The unlegalized 256-bit stores are further penalized when legalized down
; to 128-bit stores. ; to 128-bit stores.
; CHECK: cost of 2 for {{.*}} store <4 x i64> ; CHECK: cost of 2 for {{.*}} store <4 x i64>
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llvm/test/Analysis/MemorySSA/invariant-groups.ll

Show First 20 Lines • Show All 293 Lines • ▼ Show 20 Lines
} }
; In the future we would like to CSE barriers if there is no clobber between. ; In the future we would like to CSE barriers if there is no clobber between.
; CHECK-LABEL: define i8 @optimizable() ; CHECK-LABEL: define i8 @optimizable()
define i8 @optimizable() { define i8 @optimizable() {
entry: entry:
%ptr = alloca i8 %ptr = alloca i8
; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK: 1 = MemoryDef(liveOnEntry)
; CHECK-NEXT: store i8 42, i8* %ptr, !invariant.group !0 ; CHECK-NEXT: store i8 42, i8* %ptr, align 1, !invariant.group !0
store i8 42, i8* %ptr, !invariant.group !0 store i8 42, i8* %ptr, !invariant.group !0
; CHECK: 2 = MemoryDef(1) ; CHECK: 2 = MemoryDef(1)
; CHECK-NEXT: call i8* @llvm.launder.invariant.group ; CHECK-NEXT: call i8* @llvm.launder.invariant.group
%ptr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr) %ptr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr)
; FIXME: This one could be CSEd. ; FIXME: This one could be CSEd.
; CHECK: 3 = MemoryDef(2) ; CHECK: 3 = MemoryDef(2)
; CHECK: call i8* @llvm.launder.invariant.group ; CHECK: call i8* @llvm.launder.invariant.group
%ptr3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr) %ptr3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr)
Show All 12 Lines; CHECK-NEXT: load i8, i8* %ptr3, {{.*}}!invariant.group
ret i8 %v ret i8 %v
} }
; CHECK-LABEL: define i8 @unoptimizable2() ; CHECK-LABEL: define i8 @unoptimizable2()
define i8 @unoptimizable2() { define i8 @unoptimizable2() {
%ptr = alloca i8 %ptr = alloca i8
; CHECK: 1 = MemoryDef(liveOnEntry) ; CHECK: 1 = MemoryDef(liveOnEntry)
; CHECK-NEXT: store i8 42, i8* %ptr, !invariant.group !0 ; CHECK-NEXT: store i8 42, i8* %ptr, align 1, !invariant.group !0
store i8 42, i8* %ptr, !invariant.group !0 store i8 42, i8* %ptr, !invariant.group !0
; CHECK: 2 = MemoryDef(1) ; CHECK: 2 = MemoryDef(1)
; CHECK-NEXT: call i8* @llvm.launder.invariant.group ; CHECK-NEXT: call i8* @llvm.launder.invariant.group
%ptr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr) %ptr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr)
; CHECK: 3 = MemoryDef(2) ; CHECK: 3 = MemoryDef(2)
store i8 43, i8* %ptr store i8 43, i8* %ptr
; CHECK: 4 = MemoryDef(3) ; CHECK: 4 = MemoryDef(3)
; CHECK-NEXT: call i8* @llvm.launder.invariant.group ; CHECK-NEXT: call i8* @llvm.launder.invariant.group
Show All 23 Lines

llvm/test/Bitcode/memInstructions.3.2.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines; CHECK-NEXT: store volatile i8 2, i8* %ptr1
store volatile i8 2, i8* %ptr1 store volatile i8 2, i8* %ptr1
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1 ; CHECK-NEXT: store i8 2, i8* %ptr1, align 1
store i8 2, i8* %ptr1, align 1 store i8 2, i8* %ptr1, align 1
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1 ; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1
store volatile i8 2, i8* %ptr1, align 1 store volatile i8 2, i8* %ptr1, align 1
; CHECK-NEXT: store i8 2, i8* %ptr1, !nontemporal !0 ; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0
store i8 2, i8* %ptr1, !nontemporal !0 store i8 2, i8* %ptr1, !nontemporal !0
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, !nontemporal !0 ; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
store volatile i8 2, i8* %ptr1, !nontemporal !0 store volatile i8 2, i8* %ptr1, !nontemporal !0
; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0 ; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0
store i8 2, i8* %ptr1, align 1, !nontemporal !0 store i8 2, i8* %ptr1, align 1, !nontemporal !0
; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0 ; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0 store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
▲ Show 20 Lines • Show All 165 Lines • Show Last 20 Lines

llvm/test/Feature/md_on_instruction.ll

; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
define i32 @foo() nounwind ssp { define i32 @foo() nounwind ssp {
entry: entry:
; CHECK: %retval = alloca i32 ; CHECK: %retval = alloca i32
; CHECK: store i32 42, i32* %retval, !md !0 ; CHECK: store i32 42, i32* %retval, align 4, !md !0
; CHECK: br label %0, !md !1 ; CHECK: br label %0, !md !1
%retval = alloca i32 %retval = alloca i32
store i32 42, i32* %retval, !md !0 store i32 42, i32* %retval, !md !0
br label %0, !md !1 br label %0, !md !1
; <label:0> ; <label:0>
; CHECK: %1 = load i32, i32* %retval, align 4, !md !2 ; CHECK: %1 = load i32, i32* %retval, align 4, !md !2
; CHECK: ret i32 %1, !md !3 ; CHECK: ret i32 %1, !md !3
Show All 14 Lines

llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; CHECK: @__msan_metadata_ptr_for_store_8(i8* [[REG]]) ; CHECK: @__msan_metadata_ptr_for_store_8(i8* [[REG]])
; CHECK: store i64 ; CHECK: store i64
; If the new shadow is non-zero, jump to __msan_chain_origin() ; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp ; CHECK: icmp
; CHECK: br i1 ; CHECK: br i1
; CHECK: {{^[0-9]+}}: ; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin ; CHECK: @__msan_chain_origin
; Storing origin here: ; Storing origin here:
; CHECK: store i32 ; CHECK: store i64
; CHECK: br label ; CHECK: br label
; CHECK: {{^[0-9]+}}: ; CHECK: {{^[0-9]+}}:
; CHECK: store i64 ; CHECK: store i64
; CHECK: ret void ; CHECK: ret void
define void @Store16(i128* nocapture %p, i128 %x) nounwind uwtable sanitize_memory { define void @Store16(i128* nocapture %p, i128 %x) nounwind uwtable sanitize_memory {
entry: entry:
store i128 %x, i128* %p store i128 %x, i128* %p
Show All 15 Lines
; CHECK: @__msan_metadata_ptr_for_store_n(i8* [[REG]], i64 16) ; CHECK: @__msan_metadata_ptr_for_store_n(i8* [[REG]], i64 16)
; CHECK: store i128 ; CHECK: store i128
; If the new shadow is non-zero, jump to __msan_chain_origin() ; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp ; CHECK: icmp
; CHECK: br i1 ; CHECK: br i1
; CHECK: {{^[0-9]+}}: ; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin ; CHECK: @__msan_chain_origin
; Storing origin here: ; Storing origin here:
; CHECK: store i32 ; CHECK: store i64
; CHECK: br label ; CHECK: br label
; CHECK: {{^[0-9]+}}: ; CHECK: {{^[0-9]+}}:
; CHECK: store i128 ; CHECK: store i128
; CHECK: ret void ; CHECK: ret void
; Check instrumentation of loads ; Check instrumentation of loads
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll

Show All 12 Lines
; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: entry:
; IS__TUNIT____-NEXT: br label [[IF_END:%.*]] ; IS__TUNIT____-NEXT: br label [[IF_END:%.*]]
; IS__TUNIT____: for.cond1: ; IS__TUNIT____: for.cond1:
; IS__TUNIT____-NEXT: br i1 [[C]], label [[IF_END]], label [[EXIT:%.*]] ; IS__TUNIT____-NEXT: br i1 [[C]], label [[IF_END]], label [[EXIT:%.*]]
; IS__TUNIT____: if.end: ; IS__TUNIT____: if.end:
; IS__TUNIT____-NEXT: [[E_2:%.*]] = phi i32* [ [[P]], [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ] ; IS__TUNIT____-NEXT: [[E_2:%.*]] = phi i32* [ [[P]], [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ]
; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* [[E_2]], align 4 ; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* [[E_2]], align 4
; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]]) ; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]])
; IS__TUNIT____-NEXT: store i32 [[CALL]], i32* [[P]], align 1 ; IS__TUNIT____-NEXT: store i32 [[CALL]], i32* [[P]], align 4
; IS__TUNIT____-NEXT: br label [[FOR_COND1]] ; IS__TUNIT____-NEXT: br label [[FOR_COND1]]
; IS__TUNIT____: exit: ; IS__TUNIT____: exit:
; IS__TUNIT____-NEXT: ret void ; IS__TUNIT____-NEXT: ret void
; ;
; IS__CGSCC____-LABEL: define {{[^@]+}}@fn2 ; IS__CGSCC____-LABEL: define {{[^@]+}}@fn2
; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull align 4 dereferenceable(4) [[P:%.*]], i1 [[C:%.*]]) ; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull align 4 dereferenceable(4) [[P:%.*]], i1 [[C:%.*]])
; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: entry:
; IS__CGSCC____-NEXT: br label [[IF_END:%.*]] ; IS__CGSCC____-NEXT: br label [[IF_END:%.*]]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: entry:
; IS__TUNIT____-NEXT: br label [[IF_END:%.*]] ; IS__TUNIT____-NEXT: br label [[IF_END:%.*]]
; IS__TUNIT____: for.cond1: ; IS__TUNIT____: for.cond1:
; IS__TUNIT____-NEXT: br i1 [[C]], label [[IF_END]], label [[EXIT:%.*]] ; IS__TUNIT____-NEXT: br i1 [[C]], label [[IF_END]], label [[EXIT:%.*]]
; IS__TUNIT____: if.end: ; IS__TUNIT____: if.end:
; IS__TUNIT____-NEXT: [[E_2:%.*]] = phi i32* [ undef, [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ] ; IS__TUNIT____-NEXT: [[E_2:%.*]] = phi i32* [ undef, [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ]
; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* null, align 4 ; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* null, align 4
; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32 @fn0(i32 [[TMP0]]) ; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32 @fn0(i32 [[TMP0]])
; IS__TUNIT____-NEXT: store i32 [[CALL]], i32* [[P]], align 1 ; IS__TUNIT____-NEXT: store i32 [[CALL]], i32* [[P]], align 4
; IS__TUNIT____-NEXT: br label [[FOR_COND1]] ; IS__TUNIT____-NEXT: br label [[FOR_COND1]]
; IS__TUNIT____: exit: ; IS__TUNIT____: exit:
; IS__TUNIT____-NEXT: ret void ; IS__TUNIT____-NEXT: ret void
; ;
; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@fn_no_null_opt ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@fn_no_null_opt
; IS__CGSCC_OPM-SAME: (i32* nocapture nofree writeonly align 4 dereferenceable_or_null(4) [[P:%.*]], i1 [[C:%.*]]) ; IS__CGSCC_OPM-SAME: (i32* nocapture nofree writeonly align 4 dereferenceable_or_null(4) [[P:%.*]], i1 [[C:%.*]])
; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: entry:
; IS__CGSCC_OPM-NEXT: br label [[IF_END:%.*]] ; IS__CGSCC_OPM-NEXT: br label [[IF_END:%.*]]
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/Transforms/Attributor/align.ll

Show First 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
define i32* @test10a(i32* align 32 %p) { define i32* @test10a(i32* align 32 %p) {
; CHECK-LABEL: define {{[^@]+}}@test10a ; CHECK-LABEL: define {{[^@]+}}@test10a
; CHECK-SAME: (i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) ; CHECK-SAME: (i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]])
; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 ; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0
; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t: ; CHECK: t:
; CHECK-NEXT: [[R:%.*]] = call i32* @test10a(i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) ; CHECK-NEXT: [[R:%.*]] = call i32* @test10a(i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]])
; CHECK-NEXT: store i32 1, i32* [[R]], align 1 ; CHECK-NEXT: store i32 1, i32* [[R]], align 4
; CHECK-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 ; CHECK-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8
; CHECK-NEXT: br label [[E:%.*]] ; CHECK-NEXT: br label [[E:%.*]]
; CHECK: f: ; CHECK: f:
; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8 ; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8
; CHECK-NEXT: store i32 -1, i32* [[G1]], align 4 ; CHECK-NEXT: store i32 -1, i32* [[G1]], align 4
; CHECK-NEXT: br label [[E]] ; CHECK-NEXT: br label [[E]]
; CHECK: e: ; CHECK: e:
; CHECK-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ]
Show All 25 Lines
define i32* @test10b(i32* align 32 %p) { define i32* @test10b(i32* align 32 %p) {
; CHECK-LABEL: define {{[^@]+}}@test10b ; CHECK-LABEL: define {{[^@]+}}@test10b
; CHECK-SAME: (i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) ; CHECK-SAME: (i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]])
; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 ; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0
; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t: ; CHECK: t:
; CHECK-NEXT: [[R:%.*]] = call i32* @test10b(i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) ; CHECK-NEXT: [[R:%.*]] = call i32* @test10b(i32* nofree nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]])
; CHECK-NEXT: store i32 1, i32* [[R]], align 1 ; CHECK-NEXT: store i32 1, i32* [[R]], align 4
; CHECK-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 ; CHECK-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8
; CHECK-NEXT: br label [[E:%.*]] ; CHECK-NEXT: br label [[E:%.*]]
; CHECK: f: ; CHECK: f:
; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8 ; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8
; CHECK-NEXT: store i32 -1, i32* [[G1]], align 4 ; CHECK-NEXT: store i32 -1, i32* [[G1]], align 4
; CHECK-NEXT: br label [[E]] ; CHECK-NEXT: br label [[E]]
; CHECK: e: ; CHECK: e:
; CHECK-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] ; CHECK-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ]
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llvm/test/Transforms/Attributor/dereferenceable-2.ll

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; IS________OPM: l3: ; IS________OPM: l3:
; IS________OPM-NEXT: br label [[L5:%.*]] ; IS________OPM-NEXT: br label [[L5:%.*]]
; IS________OPM: l4: ; IS________OPM: l4:
; IS________OPM-NEXT: br label [[L5]] ; IS________OPM-NEXT: br label [[L5]]
; IS________OPM: l5: ; IS________OPM: l5:
; IS________OPM-NEXT: [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4 ; IS________OPM-NEXT: [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4
; IS________OPM-NEXT: br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]] ; IS________OPM-NEXT: br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]]
; IS________OPM: l6: ; IS________OPM: l6:
; IS________OPM-NEXT: store i32 0, i32* [[P]], align 1 ; IS________OPM-NEXT: store i32 0, i32* [[P]], align 4
; IS________OPM-NEXT: br label [[END:%.*]] ; IS________OPM-NEXT: br label [[END:%.*]]
; IS________OPM: l7: ; IS________OPM: l7:
; IS________OPM-NEXT: store i32 1, i32* [[P]], align 1 ; IS________OPM-NEXT: store i32 1, i32* [[P]], align 4
; IS________OPM-NEXT: br label [[END]] ; IS________OPM-NEXT: br label [[END]]
; IS________OPM: end: ; IS________OPM: end:
; IS________OPM-NEXT: ret i32 1 ; IS________OPM-NEXT: ret i32 1
; ;
; IS________NPM-LABEL: define {{[^@]+}}@require_cfg_analysis ; IS________NPM-LABEL: define {{[^@]+}}@require_cfg_analysis
; IS________NPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[P:%.*]]) ; IS________NPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[P:%.*]])
; IS________NPM-NEXT: [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0 ; IS________NPM-NEXT: [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0
; IS________NPM-NEXT: br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]] ; IS________NPM-NEXT: br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]]
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llvm/test/Transforms/Attributor/heap_to_stack.ll

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tail call void @free(i8* nonnull dereferenceable(1) %1) tail call void @free(i8* nonnull dereferenceable(1) %1)
ret void ret void
} }
define void @test16b(i8 %v, i8** %P) { define void @test16b(i8 %v, i8** %P) {
; CHECK-LABEL: define {{[^@]+}}@test16b ; CHECK-LABEL: define {{[^@]+}}@test16b
; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]]) ; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4)
; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 1 ; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 8
; CHECK-NEXT: tail call void @no_sync_func(i8* nocapture nofree [[TMP1]]) ; CHECK-NEXT: tail call void @no_sync_func(i8* nocapture nofree [[TMP1]])
; CHECK-NEXT: tail call void @free(i8* nocapture [[TMP1]]) ; CHECK-NEXT: tail call void @free(i8* nocapture [[TMP1]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%1 = tail call noalias i8* @malloc(i64 4) %1 = tail call noalias i8* @malloc(i64 4)
store i8* %1, i8** %P store i8* %1, i8** %P
tail call void @no_sync_func(i8* %1) tail call void @no_sync_func(i8* %1)
tail call void @free(i8* %1) tail call void @free(i8* %1)
ret void ret void
} }
define void @test16c(i8 %v, i8** %P) { define void @test16c(i8 %v, i8** %P) {
; CHECK-LABEL: define {{[^@]+}}@test16c ; CHECK-LABEL: define {{[^@]+}}@test16c
; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]]) ; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4)
; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 1 ; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 8
; CHECK-NEXT: tail call void @no_sync_func(i8* nocapture nofree [[TMP1]]) ; CHECK-NEXT: tail call void @no_sync_func(i8* nocapture nofree [[TMP1]])
; CHECK-NEXT: tail call void @free(i8* nocapture [[TMP1]]) ; CHECK-NEXT: tail call void @free(i8* nocapture [[TMP1]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%1 = tail call noalias i8* @malloc(i64 4) %1 = tail call noalias i8* @malloc(i64 4)
store i8* %1, i8** %P store i8* %1, i8** %P
tail call void @no_sync_func(i8* %1) nounwind tail call void @no_sync_func(i8* %1) nounwind
tail call void @free(i8* %1) tail call void @free(i8* %1)
ret void ret void
} }
define void @test16d(i8 %v, i8** %P) { define void @test16d(i8 %v, i8** %P) {
; CHECK-LABEL: define {{[^@]+}}@test16d ; CHECK-LABEL: define {{[^@]+}}@test16d
; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]]) ; CHECK-SAME: (i8 [[V:%.*]], i8** nocapture writeonly [[P:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 4)
; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 1 ; CHECK-NEXT: store i8* [[TMP1]], i8** [[P]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%1 = tail call noalias i8* @malloc(i64 4) %1 = tail call noalias i8* @malloc(i64 4)
store i8* %1, i8** %P store i8* %1, i8** %P
ret void ret void
} }

llvm/test/Transforms/Attributor/nocapture-2.ll

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declare i32* @unknown_i32p(i32*) declare i32* @unknown_i32p(i32*)
define void @nocapture_is_not_subsumed_1(i32* nocapture %b) { define void @nocapture_is_not_subsumed_1(i32* nocapture %b) {
; CHECK-LABEL: define {{[^@]+}}@nocapture_is_not_subsumed_1 ; CHECK-LABEL: define {{[^@]+}}@nocapture_is_not_subsumed_1
; CHECK-SAME: (i32* nocapture [[B:%.*]]) ; CHECK-SAME: (i32* nocapture [[B:%.*]])
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL:%.*]] = call i32* @unknown_i32p(i32* [[B]]) ; CHECK-NEXT: [[CALL:%.*]] = call i32* @unknown_i32p(i32* [[B]])
; CHECK-NEXT: store i32 0, i32* [[CALL]], align 1 ; CHECK-NEXT: store i32 0, i32* [[CALL]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%call = call i32* @unknown_i32p(i32* %b) %call = call i32* @unknown_i32p(i32* %b)
store i32 0, i32* %call store i32 0, i32* %call
ret void ret void
} }
declare i32* @readonly_i32p(i32*) readonly declare i32* @readonly_i32p(i32*) readonly
define void @nocapture_is_not_subsumed_2(i32* nocapture %b) { define void @nocapture_is_not_subsumed_2(i32* nocapture %b) {
; CHECK-LABEL: define {{[^@]+}}@nocapture_is_not_subsumed_2 ; CHECK-LABEL: define {{[^@]+}}@nocapture_is_not_subsumed_2
; CHECK-SAME: (i32* nocapture [[B:%.*]]) ; CHECK-SAME: (i32* nocapture [[B:%.*]])
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_i32p(i32* readonly [[B]]) ; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_i32p(i32* readonly [[B]])
; CHECK-NEXT: store i32 0, i32* [[CALL]], align 1 ; CHECK-NEXT: store i32 0, i32* [[CALL]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%call = call i32* @readonly_i32p(i32* %b) %call = call i32* @readonly_i32p(i32* %b)
store i32 0, i32* %call store i32 0, i32* %call
ret void ret void
} }
attributes #0 = { noinline nounwind uwtable } attributes #0 = { noinline nounwind uwtable }

llvm/test/Transforms/Attributor/value-simplify.ll

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; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: switch i32 [[J_0]], label [[SW_EPILOG]] [ ; CHECK-NEXT: switch i32 [[J_0]], label [[SW_EPILOG]] [
; CHECK-NEXT: i32 1, label [[SW_BB:%.*]] ; CHECK-NEXT: i32 1, label [[SW_BB:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: sw.bb: ; CHECK: sw.bb:
; CHECK-NEXT: br label [[SW_EPILOG]] ; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog: ; CHECK: sw.epilog:
; CHECK-NEXT: [[X_0:%.*]] = phi i32 [ 255, [[FOR_BODY]] ], [ 253, [[SW_BB]] ] ; CHECK-NEXT: [[X_0:%.*]] = phi i32 [ 255, [[FOR_BODY]] ], [ 253, [[SW_BB]] ]
; CHECK-NEXT: store i32 [[X_0]], i32* [[P]], align 1 ; CHECK-NEXT: store i32 [[X_0]], i32* [[P]], align 4
; CHECK-NEXT: [[INC]] = add nsw i32 [[J_0]], 1 ; CHECK-NEXT: [[INC]] = add nsw i32 [[J_0]], 1
; CHECK-NEXT: br label [[FOR_COND]] ; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
br label %for.cond br label %for.cond
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llvm/test/Transforms/CodeGenPrepare/X86/invariant.group.ll

; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s ; RUN: opt -codegenprepare -S -mtriple=x86_64 < %s | FileCheck %s
@tmp = global i8 0 @tmp = global i8 0
; CHECK-LABEL: define void @foo() { ; CHECK-LABEL: define void @foo() {
define void @foo() { define void @foo() {
enter: enter:
; CHECK-NOT: !invariant.group ; CHECK-NOT: !invariant.group
; CHECK-NOT: @llvm.launder.invariant.group.p0i8( ; CHECK-NOT: @llvm.launder.invariant.group.p0i8(
; CHECK: %val = load i8, i8* @tmp, align 1{{$}} ; CHECK: %val = load i8, i8* @tmp, align 1{{$}}
%val = load i8, i8* @tmp, !invariant.group !0 %val = load i8, i8* @tmp, !invariant.group !0
%ptr = call i8* @llvm.launder.invariant.group.p0i8(i8* @tmp) %ptr = call i8* @llvm.launder.invariant.group.p0i8(i8* @tmp)
; CHECK: store i8 42, i8* @tmp{{$}} ; CHECK: store i8 42, i8* @tmp, align 1{{$}}
store i8 42, i8* %ptr, !invariant.group !0 store i8 42, i8* %ptr, !invariant.group !0
ret void ret void
} }
; CHECK-LABEL: } ; CHECK-LABEL: }
; CHECK-LABEL: define void @foo2() { ; CHECK-LABEL: define void @foo2() {
define void @foo2() { define void @foo2() {
enter: enter:
; CHECK-NOT: !invariant.group ; CHECK-NOT: !invariant.group
; CHECK-NOT: @llvm.strip.invariant.group.p0i8( ; CHECK-NOT: @llvm.strip.invariant.group.p0i8(
; CHECK: %val = load i8, i8* @tmp, align 1{{$}} ; CHECK: %val = load i8, i8* @tmp, align 1{{$}}
%val = load i8, i8* @tmp, !invariant.group !0 %val = load i8, i8* @tmp, !invariant.group !0
%ptr = call i8* @llvm.strip.invariant.group.p0i8(i8* @tmp) %ptr = call i8* @llvm.strip.invariant.group.p0i8(i8* @tmp)
; CHECK: store i8 42, i8* @tmp{{$}} ; CHECK: store i8 42, i8* @tmp, align 1{{$}}
store i8 42, i8* %ptr, !invariant.group !0 store i8 42, i8* %ptr, !invariant.group !0
ret void ret void
} }
; CHECK-LABEL: } ; CHECK-LABEL: }
declare i8* @llvm.launder.invariant.group.p0i8(i8*) declare i8* @llvm.launder.invariant.group.p0i8(i8*)
declare i8* @llvm.strip.invariant.group.p0i8(i8*) declare i8* @llvm.strip.invariant.group.p0i8(i8*)
!0 = !{} !0 = !{}

llvm/test/Transforms/CorrelatedValuePropagation/non-null.ll

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br label %bb br label %bb
bb: bb:
icmp ne i8* %ptr, null icmp ne i8* %ptr, null
ret void ret void
} }
define void @test2(i8* %ptr) { define void @test2(i8* %ptr) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: store i8 0, i8* [[PTR:%.*]] ; CHECK-NEXT: store i8 0, i8* [[PTR:%.*]], align 1
; CHECK-NEXT: br label [[BB:%.*]] ; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb: ; CHECK: bb:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i8 0, i8* %ptr store i8 0, i8* %ptr
br label %bb br label %bb
bb: bb:
icmp ne i8* %ptr, null icmp ne i8* %ptr, null
ret void ret void
} }
define void @test2_no_null_opt(i8* %ptr) #0 { define void @test2_no_null_opt(i8* %ptr) #0 {
; CHECK-LABEL: @test2_no_null_opt( ; CHECK-LABEL: @test2_no_null_opt(
; CHECK-NEXT: store i8 0, i8* [[PTR:%.*]] ; CHECK-NEXT: store i8 0, i8* [[PTR:%.*]], align 1
; CHECK-NEXT: br label [[BB:%.*]] ; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb: ; CHECK: bb:
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8* [[PTR]], null ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8* [[PTR]], null
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i8 0, i8* %ptr store i8 0, i8* %ptr
br label %bb br label %bb
bb: bb:
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llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll

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declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret, i64) declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret, i64)
define void @test1(i32 *%ptr) { define void @test1(i32 *%ptr) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[BPTR:%.*]] = bitcast i32* [[PTR:%.*]] to i8* ; CHECK-NEXT: [[BPTR:%.*]] = bitcast i32* [[PTR:%.*]] to i8*
; CHECK-NEXT: [[WPTR:%.*]] = bitcast i32* [[PTR]] to i16* ; CHECK-NEXT: [[WPTR:%.*]] = bitcast i32* [[PTR]] to i16*
; CHECK-NEXT: store i16 -30062, i16* [[WPTR]] ; CHECK-NEXT: store i16 -30062, i16* [[WPTR]], align 2
; CHECK-NEXT: [[BPTR3:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 3 ; CHECK-NEXT: [[BPTR3:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 3
; CHECK-NEXT: store i8 47, i8* [[BPTR3]] ; CHECK-NEXT: store i8 47, i8* [[BPTR3]], align 1
; CHECK-NEXT: [[BPTR1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 1 ; CHECK-NEXT: [[BPTR1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 1
; CHECK-NEXT: [[WPTRP:%.*]] = bitcast i8* [[BPTR1]] to i16* ; CHECK-NEXT: [[WPTRP:%.*]] = bitcast i8* [[BPTR1]] to i16*
; CHECK-NEXT: store i16 2020, i16* [[WPTRP]], align 1 ; CHECK-NEXT: store i16 2020, i16* [[WPTRP]], align 1
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i32 5, i32* %ptr store i32 5, i32* %ptr
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ret void ret void
} }
define signext i8 @test3(i32 *%ptr) { define signext i8 @test3(i32 *%ptr) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 5, i32* [[PTR:%.*]] ; CHECK-NEXT: store i32 5, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: [[BPTR:%.*]] = bitcast i32* [[PTR]] to i8* ; CHECK-NEXT: [[BPTR:%.*]] = bitcast i32* [[PTR]] to i8*
; CHECK-NEXT: [[BPTRM1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 -1 ; CHECK-NEXT: [[BPTRM1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 -1
; CHECK-NEXT: [[BPTR1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 1 ; CHECK-NEXT: [[BPTR1:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 1
; CHECK-NEXT: [[BPTR2:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 2 ; CHECK-NEXT: [[BPTR2:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 2
; CHECK-NEXT: [[BPTR3:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 3 ; CHECK-NEXT: [[BPTR3:%.*]] = getelementptr inbounds i8, i8* [[BPTR]], i64 3
; CHECK-NEXT: [[WPTR:%.*]] = bitcast i8* [[BPTR]] to i16* ; CHECK-NEXT: [[WPTR:%.*]] = bitcast i8* [[BPTR]] to i16*
; CHECK-NEXT: [[WPTRM1:%.*]] = bitcast i8* [[BPTRM1]] to i16* ; CHECK-NEXT: [[WPTRM1:%.*]] = bitcast i8* [[BPTRM1]] to i16*
; CHECK-NEXT: [[WPTR1:%.*]] = bitcast i8* [[BPTR1]] to i16* ; CHECK-NEXT: [[WPTR1:%.*]] = bitcast i8* [[BPTR1]] to i16*
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llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath-throwing.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
declare void @readnone_may_throw() readnone declare void @readnone_may_throw() readnone
declare void @use(i32 *) declare void @use(i32 *)
; Tests where the pointer/object is accessible after the function returns. ; Tests where the pointer/object is accessible after the function returns.
; Cannot remove the store from the entry block, because the call in bb2 may throw. ; Cannot remove the store from the entry block, because the call in bb2 may throw.
define void @accessible_after_return_1(i32* noalias %P, i1 %c1) { define void @accessible_after_return_1(i32* noalias %P, i1 %c1) {
; CHECK-LABEL: @accessible_after_return_1( ; CHECK-LABEL: @accessible_after_return_1(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: call void @readnone_may_throw() ; CHECK-NEXT: call void @readnone_may_throw()
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c1, label %bb1, label %bb2 br i1 %c1, label %bb1, label %bb2
Show All 10 Linesbb5:
call void @use(i32* %P) call void @use(i32* %P)
ret void ret void
} }
; Cannot remove the store from the entry block, because the call in bb3 may throw. ; Cannot remove the store from the entry block, because the call in bb3 may throw.
define void @accessible_after_return6(i32* %P, i1 %c.1, i1 %c.2) { define void @accessible_after_return6(i32* %P, i1 %c.1, i1 %c.2) {
; CHECK-LABEL: @accessible_after_return6( ; CHECK-LABEL: @accessible_after_return6(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]] ; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: call void @readnone_may_throw() ; CHECK-NEXT: call void @readnone_may_throw()
; CHECK-NEXT: store i32 2, i32* [[P]] ; CHECK-NEXT: store i32 2, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i32 0, i32* %P store i32 0, i32* %P
br i1 %c.1, label %bb1, label %bb2 br i1 %c.1, label %bb1, label %bb2
bb1: bb1:
br i1 %c.2, label %bb3, label %bb4 br i1 %c.2, label %bb3, label %bb4
Show All 18 Lines
; on all paths to the exit. As the location is not visible to the caller, the ; on all paths to the exit. As the location is not visible to the caller, the
; call in bb2 (which may throw) can be ignored. ; call in bb2 (which may throw) can be ignored.
define void @alloca_1(i1 %c1) { define void @alloca_1(i1 %c1) {
; CHECK-LABEL: @alloca_1( ; CHECK-LABEL: @alloca_1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: call void @readnone_may_throw() ; CHECK-NEXT: call void @readnone_may_throw()
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%P = alloca i32 %P = alloca i32
store i32 1, i32* %P store i32 1, i32* %P
Show All 16 Lines
; The store in the entry block can be eliminated, because it is overwritten ; The store in the entry block can be eliminated, because it is overwritten
; on all paths to the exit. As the location is not visible to the caller, the ; on all paths to the exit. As the location is not visible to the caller, the
; call in bb3 (which may throw) can be ignored. ; call in bb3 (which may throw) can be ignored.
define void @alloca_2(i1 %c.1, i1 %c.2) { define void @alloca_2(i1 %c.1, i1 %c.2) {
; CHECK-LABEL: @alloca_2( ; CHECK-LABEL: @alloca_2(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]] ; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: call void @readnone_may_throw() ; CHECK-NEXT: call void @readnone_may_throw()
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: store i32 5, i32* [[P]] ; CHECK-NEXT: store i32 5, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c.1, label %bb1, label %bb2 br i1 %c.1, label %bb1, label %bb2
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llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
declare void @use(i32 *) declare void @use(i32 *)
; Tests where the pointer/object is accessible after the function returns. ; Tests where the pointer/object is accessible after the function returns.
define void @accessible_after_return_1(i32* noalias %P, i1 %c1) { define void @accessible_after_return_1(i32* noalias %P, i1 %c1) {
; CHECK-LABEL: @accessible_after_return_1( ; CHECK-LABEL: @accessible_after_return_1(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c1, label %bb1, label %bb2 br i1 %c1, label %bb1, label %bb2
bb1: bb1:
store i32 0, i32* %P store i32 0, i32* %P
br label %bb5 br label %bb5
bb2: bb2:
store i32 3, i32* %P store i32 3, i32* %P
br label %bb5 br label %bb5
bb5: bb5:
call void @use(i32* %P) call void @use(i32* %P)
ret void ret void
} }
define void @accessible_after_return_2(i32* noalias %P, i1 %c.1, i1 %c.2) { define void @accessible_after_return_2(i32* noalias %P, i1 %c.1, i1 %c.2) {
; CHECK-LABEL: @accessible_after_return_2( ; CHECK-LABEL: @accessible_after_return_2(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]] ; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: store i32 5, i32* [[P]] ; CHECK-NEXT: store i32 5, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c.1, label %bb1, label %bb2 br i1 %c.1, label %bb1, label %bb2
bb1: bb1:
Show All 13 Lines
bb5: bb5:
call void @use(i32* %P) call void @use(i32* %P)
ret void ret void
} }
define void @accessible_after_return_3(i32* noalias %P, i1 %c1) { define void @accessible_after_return_3(i32* noalias %P, i1 %c1) {
; CHECK-LABEL: @accessible_after_return_3( ; CHECK-LABEL: @accessible_after_return_3(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c1, label %bb1, label %bb2 br i1 %c1, label %bb1, label %bb2
bb1: bb1:
store i32 0, i32* %P store i32 0, i32* %P
br label %bb5 br label %bb5
bb2: bb2:
br label %bb5 br label %bb5
bb5: bb5:
call void @use(i32* %P) call void @use(i32* %P)
ret void ret void
} }
define void @accessible_after_return_4(i32* noalias %P, i1 %c1) { define void @accessible_after_return_4(i32* noalias %P, i1 %c1) {
; CHECK-LABEL: @accessible_after_return_4( ; CHECK-LABEL: @accessible_after_return_4(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
Show All 16 Lines
; The store in the entry block can be eliminated, because it is overwritten ; The store in the entry block can be eliminated, because it is overwritten
; on all paths to the exit. ; on all paths to the exit.
define void @alloca_1(i1 %c1) { define void @alloca_1(i1 %c1) {
; CHECK-LABEL: @alloca_1( ; CHECK-LABEL: @alloca_1(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c1, label %bb1, label %bb2 br i1 %c1, label %bb1, label %bb2
Show All 12 Lines
; The store in the entry block can be eliminated, because it is overwritten ; The store in the entry block can be eliminated, because it is overwritten
; on all paths to the exit. ; on all paths to the exit.
define void @alloca_2(i1 %c.1, i1 %c.2) { define void @alloca_2(i1 %c.1, i1 %c.2) {
; CHECK-LABEL: @alloca_2( ; CHECK-LABEL: @alloca_2(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C_1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]] ; CHECK-NEXT: br i1 [[C_2:%.*]], label [[BB3:%.*]], label [[BB4:%.*]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 3, i32* [[P]] ; CHECK-NEXT: store i32 3, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: store i32 5, i32* [[P]] ; CHECK-NEXT: store i32 5, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
store i32 1, i32* %P store i32 1, i32* %P
br i1 %c.1, label %bb1, label %bb2 br i1 %c.1, label %bb1, label %bb2
Show All 18 Linesbb5:
ret void ret void
} }
; The store in the entry block cannot be eliminated. There's a path from the ; The store in the entry block cannot be eliminated. There's a path from the
; first store to the read in bb5, where the location is not overwritten. ; first store to the read in bb5, where the location is not overwritten.
define void @alloca_3(i1 %c1) { define void @alloca_3(i1 %c1) {
; CHECK-LABEL: @alloca_3( ; CHECK-LABEL: @alloca_3(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
Show All 14 Lines
; The store in the entry block can be eliminated, because it is overwritten ; The store in the entry block can be eliminated, because it is overwritten
; before the use in bb1 and not read on other paths to the function exit. The ; before the use in bb1 and not read on other paths to the function exit. The
; object cannot be accessed by the caller. ; object cannot be accessed by the caller.
define void @alloca_4(i1 %c1) { define void @alloca_4(i1 %c1) {
; CHECK-LABEL: @alloca_4( ; CHECK-LABEL: @alloca_4(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: call void @use(i32* [[P]]) ; CHECK-NEXT: call void @use(i32* [[P]])
; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK-NEXT: br label [[BB5:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB5]] ; CHECK-NEXT: br label [[BB5]]
; CHECK: bb5: ; CHECK: bb5:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
Show All 14 Lines

llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
define void @second_store_smaller(i32* noalias %P) { define void @second_store_smaller(i32* noalias %P) {
; CHECK-LABEL: @second_store_smaller( ; CHECK-LABEL: @second_store_smaller(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[P_I16:%.*]] = bitcast i32* [[P]] to i16* ; CHECK-NEXT: [[P_I16:%.*]] = bitcast i32* [[P]] to i16*
; CHECK-NEXT: store i16 0, i16* [[P_I16]] ; CHECK-NEXT: store i16 0, i16* [[P_I16]], align 2
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
bb2: bb2:
br label %bb3 br label %bb3
bb3: bb3:
%P.i16 = bitcast i32* %P to i16* %P.i16 = bitcast i32* %P to i16*
store i16 0, i16* %P.i16 store i16 0, i16* %P.i16
ret void ret void
} }
define void @second_store_bigger(i32* noalias %P) { define void @second_store_bigger(i32* noalias %P) {
; CHECK-LABEL: @second_store_bigger( ; CHECK-LABEL: @second_store_bigger(
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[P_I64:%.*]] = bitcast i32* [[P:%.*]] to i64* ; CHECK-NEXT: [[P_I64:%.*]] = bitcast i32* [[P:%.*]] to i64*
; CHECK-NEXT: store i64 0, i64* [[P_I64]] ; CHECK-NEXT: store i64 0, i64* [[P_I64]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
bb2: bb2:
br label %bb3 br label %bb3
bb3: bb3:
%P.i64 = bitcast i32* %P to i64* %P.i64 = bitcast i32* %P to i64*
store i64 0, i64* %P.i64 store i64 0, i64* %P.i64
ret void ret void
} }

llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
define void @test2(i32* noalias %P) { define void @test2(i32* noalias %P) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
bb2: bb2:
br label %bb3 br label %bb3
bb3: bb3:
store i32 0, i32* %P store i32 0, i32* %P
ret void ret void
} }
define void @test3(i32* noalias %P) { define void @test3(i32* noalias %P) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
Show All 9 Lines
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[P:%.*]], align 4
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 0, i32* [[Q:%.*]] ; CHECK-NEXT: store i32 0, i32* [[Q:%.*]], align 4
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %Q store i32 1, i32* %Q
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
load i32, i32* %P load i32, i32* %P
br label %bb3 br label %bb3
bb2: bb2:
br label %bb3 br label %bb3
bb3: bb3:
store i32 0, i32* %Q store i32 0, i32* %Q
store i32 0, i32* %P store i32 0, i32* %P
ret void ret void
} }
define i32 @test22(i32* %P, i32* noalias %Q, i32* %R) { define i32 @test22(i32* %P, i32* noalias %Q, i32* %R) {
; CHECK-LABEL: @test22( ; CHECK-LABEL: @test22(
; CHECK-NEXT: store i32 2, i32* [[P:%.*]] ; CHECK-NEXT: store i32 2, i32* [[P:%.*]], align 4
; CHECK-NEXT: store i32 3, i32* [[Q:%.*]] ; CHECK-NEXT: store i32 3, i32* [[Q:%.*]], align 4
; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[R:%.*]], align 4 ; CHECK-NEXT: [[L:%.*]] = load i32, i32* [[R:%.*]], align 4
; CHECK-NEXT: ret i32 [[L]] ; CHECK-NEXT: ret i32 [[L]]
; ;
store i32 1, i32* %Q store i32 1, i32* %Q
store i32 2, i32* %P store i32 2, i32* %P
store i32 3, i32* %Q store i32 3, i32* %Q
%l = load i32, i32* %R %l = load i32, i32* %R
ret i32 %l ret i32 %l
} }
define void @test9(i32* noalias %P) { define void @test9(i32* noalias %P) {
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
bb2: bb2:
ret void ret void
bb3: bb3:
store i32 0, i32* %P store i32 0, i32* %P
ret void ret void
} }
; We cannot eliminate `store i32 0, i32* %P`, as it is read by the later load. ; We cannot eliminate `store i32 0, i32* %P`, as it is read by the later load.
; Make sure that we check the uses of `store i32 1, i32* %P.1 which does not ; Make sure that we check the uses of `store i32 1, i32* %P.1 which does not
; alias %P. Note that uses point to the *first* def that may alias. ; alias %P. Note that uses point to the *first* def that may alias.
define void @overlapping_read(i32* %P) { define void @overlapping_read(i32* %P) {
; CHECK-LABEL: @overlapping_read( ; CHECK-LABEL: @overlapping_read(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: [[P_1:%.*]] = getelementptr i32, i32* [[P]], i32 1 ; CHECK-NEXT: [[P_1:%.*]] = getelementptr i32, i32* [[P]], i32 1
; CHECK-NEXT: store i32 1, i32* [[P_1]] ; CHECK-NEXT: store i32 1, i32* [[P_1]], align 4
; CHECK-NEXT: [[P_64:%.*]] = bitcast i32* [[P]] to i64* ; CHECK-NEXT: [[P_64:%.*]] = bitcast i32* [[P]] to i64*
; CHECK-NEXT: [[LV:%.*]] = load i64, i64* [[P_64]], align 8 ; CHECK-NEXT: [[LV:%.*]] = load i64, i64* [[P_64]], align 8
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i32 2, i32* [[P]] ; CHECK-NEXT: store i32 2, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
%P.1 = getelementptr i32, i32* %P, i32 1 %P.1 = getelementptr i32, i32* %P, i32 1
store i32 1, i32* %P.1 store i32 1, i32* %P.1
%P.64 = bitcast i32* %P to i64* %P.64 = bitcast i32* %P to i64*
%lv = load i64, i64* %P.64 %lv = load i64, i64* %P.64
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
br label %bb3 br label %bb3
bb2: bb2:
br label %bb3 br label %bb3
bb3: bb3:
store i32 2, i32* %P store i32 2, i32* %P
ret void ret void
} }
define void @test10(i32* %P) { define void @test10(i32* %P) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
store i32 0, i32* %P store i32 0, i32* %P
br label %bb3 br label %bb3
bb2: bb2:
ret void ret void
bb3: bb3:
ret void ret void
} }
define void @test11() { define void @test11() {
; CHECK-LABEL: @test11( ; CHECK-LABEL: @test11(
; CHECK-NEXT: [[P:%.*]] = alloca i32 ; CHECK-NEXT: [[P:%.*]] = alloca i32
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P = alloca i32 %P = alloca i32
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
store i32 0, i32* %P store i32 0, i32* %P
br label %bb3 br label %bb3
bb2: bb2:
ret void ret void
bb3: bb3:
ret void ret void
} }
define void @test12(i32* %P) { define void @test12(i32* %P) {
; CHECK-LABEL: @test12( ; CHECK-LABEL: @test12(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
store i32 1, i32* %P store i32 1, i32* %P
br label %bb3 br label %bb3
bb2: bb2:
store i32 1, i32* %P store i32 1, i32* %P
ret void ret void
bb3: bb3:
ret void ret void
} }
define void @test13(i32* %P) { define void @test13(i32* %P) {
; CHECK-LABEL: @test13( ; CHECK-LABEL: @test13(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 0, i32* %P store i32 0, i32* %P
br i1 true, label %bb1, label %bb2 br i1 true, label %bb1, label %bb2
bb1: bb1:
store i32 1, i32* %P store i32 1, i32* %P
br label %bb3 br label %bb3
bb2: bb2:
store i32 1, i32* %P store i32 1, i32* %P
br label %bb3 br label %bb3
bb3: bb3:
ret void ret void
} }

llvm/test/Transforms/DeadStoreElimination/MSSA/simple-preservation.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -enable-knowledge-retention -S | FileCheck %s ; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -enable-knowledge-retention -S | FileCheck %s
target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
define void @test1(i32* %Q, i32* %P) { define void @test1(i32* %Q, i32* %P) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[Q:%.*]], i64 4), "nonnull"(i32* [[Q]]), "align"(i32* [[Q]], i64 4) ] ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[Q:%.*]], i64 4), "nonnull"(i32* [[Q]]), "align"(i32* [[Q]], i64 4) ]
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P:%.*]], i64 4), "nonnull"(i32* [[P]]) ] ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P:%.*]], i64 4), "nonnull"(i32* [[P]]), "align"(i32* [[P]], i64 4) ]
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%DEAD = load i32, i32* %Q %DEAD = load i32, i32* %Q
store i32 %DEAD, i32* %P store i32 %DEAD, i32* %P
store i32 0, i32* %P store i32 0, i32* %P
ret void ret void
} }

llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s
; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -S | FileCheck %s
target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture, i8, i64, i32) nounwind declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture, i8, i64, i32) nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
declare void @llvm.init.trampoline(i8*, i8*, i8*) declare void @llvm.init.trampoline(i8*, i8*, i8*)
define void @test1(i32* %Q, i32* %P) { define void @test1(i32* %Q, i32* %P) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%DEAD = load i32, i32* %Q %DEAD = load i32, i32* %Q
store i32 %DEAD, i32* %P store i32 %DEAD, i32* %P
store i32 0, i32* %P store i32 0, i32* %P
ret void ret void
} }
Show All 14 Lines;
%tmp3 = load i32, i32* @g, align 4 %tmp3 = load i32, i32* @g, align 4
ret i32 %tmp3 ret i32 %tmp3
} }
define void @test4(i32* %Q) { define void @test4(i32* %Q) {
; CHECK-LABEL: @test4( ; CHECK-LABEL: @test4(
; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q:%.*]], align 4 ; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q:%.*]], align 4
; CHECK-NEXT: store volatile i32 [[A]], i32* [[Q]] ; CHECK-NEXT: store volatile i32 [[A]], i32* [[Q]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%a = load i32, i32* %Q %a = load i32, i32* %Q
store volatile i32 %a, i32* %Q store volatile i32 %a, i32* %Q
ret void ret void
} }
; PR8576 - Should delete store of 10 even though p/q are may aliases. ; PR8576 - Should delete store of 10 even though p/q are may aliases.
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ret void ret void
} }
; va_arg has fuzzy dependence, the store shouldn't be zapped. ; va_arg has fuzzy dependence, the store shouldn't be zapped.
define double @test10(i8* %X) { define double @test10(i8* %X) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8* ; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8*
; CHECK-NEXT: store i8* [[X:%.*]], i8** [[X_ADDR]] ; CHECK-NEXT: store i8* [[X:%.*]], i8** [[X_ADDR]], align 8
; CHECK-NEXT: [[TMP_0:%.*]] = va_arg i8** [[X_ADDR]], double ; CHECK-NEXT: [[TMP_0:%.*]] = va_arg i8** [[X_ADDR]], double
; CHECK-NEXT: ret double [[TMP_0]] ; CHECK-NEXT: ret double [[TMP_0]]
; ;
%X_addr = alloca i8* %X_addr = alloca i8*
store i8* %X, i8** %X_addr store i8* %X, i8** %X_addr
%tmp.0 = va_arg i8** %X_addr, double %tmp.0 = va_arg i8** %X_addr, double
ret double %tmp.0 ret double %tmp.0
} }
; %P doesn't escape, the DEAD instructions should be removed. ; %P doesn't escape, the DEAD instructions should be removed.
declare void @test13f() declare void @test13f()
define i32* @test13() { define i32* @test13() {
; CHECK-LABEL: @test13( ; CHECK-LABEL: @test13(
; CHECK-NEXT: [[PTR:%.*]] = tail call i8* @malloc(i32 4) ; CHECK-NEXT: [[PTR:%.*]] = tail call i8* @malloc(i32 4)
; CHECK-NEXT: [[P:%.*]] = bitcast i8* [[PTR]] to i32* ; CHECK-NEXT: [[P:%.*]] = bitcast i8* [[PTR]] to i32*
; CHECK-NEXT: call void @test13f() ; CHECK-NEXT: call void @test13f()
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: ret i32* [[P]] ; CHECK-NEXT: ret i32* [[P]]
; ;
%ptr = tail call i8* @malloc(i32 4) %ptr = tail call i8* @malloc(i32 4)
%P = bitcast i8* %ptr to i32* %P = bitcast i8* %ptr to i32*
%DEAD = load i32, i32* %P %DEAD = load i32, i32* %P
%DEAD2 = add i32 %DEAD, 1 %DEAD2 = add i32 %DEAD, 1
store i32 %DEAD2, i32* %P store i32 %DEAD2, i32* %P
call void @test13f( ) call void @test13f( )
store i32 0, i32* %P store i32 0, i32* %P
ret i32* %P ret i32* %P
} }
define i32 addrspace(1)* @test13_addrspacecast() { define i32 addrspace(1)* @test13_addrspacecast() {
; CHECK-LABEL: @test13_addrspacecast( ; CHECK-LABEL: @test13_addrspacecast(
; CHECK-NEXT: [[P:%.*]] = tail call i8* @malloc(i32 4) ; CHECK-NEXT: [[P:%.*]] = tail call i8* @malloc(i32 4)
; CHECK-NEXT: [[P_BC:%.*]] = bitcast i8* [[P]] to i32* ; CHECK-NEXT: [[P_BC:%.*]] = bitcast i8* [[P]] to i32*
; CHECK-NEXT: [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)* ; CHECK-NEXT: [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)*
; CHECK-NEXT: call void @test13f() ; CHECK-NEXT: call void @test13f()
; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]] ; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]], align 4
; CHECK-NEXT: ret i32 addrspace(1)* [[P]] ; CHECK-NEXT: ret i32 addrspace(1)* [[P]]
; ;
%p = tail call i8* @malloc(i32 4) %p = tail call i8* @malloc(i32 4)
%p.bc = bitcast i8* %p to i32* %p.bc = bitcast i8* %p to i32*
%P = addrspacecast i32* %p.bc to i32 addrspace(1)* %P = addrspacecast i32* %p.bc to i32 addrspace(1)*
%DEAD = load i32, i32 addrspace(1)* %P %DEAD = load i32, i32 addrspace(1)* %P
%DEAD2 = add i32 %DEAD, 1 %DEAD2 = add i32 %DEAD, 1
store i32 %DEAD2, i32 addrspace(1)* %P store i32 %DEAD2, i32 addrspace(1)* %P
call void @test13f( ) call void @test13f( )
store i32 0, i32 addrspace(1)* %P store i32 0, i32 addrspace(1)* %P
ret i32 addrspace(1)* %P ret i32 addrspace(1)* %P
} }
declare noalias i8* @malloc(i32) declare noalias i8* @malloc(i32)
declare noalias i8* @calloc(i32, i32) declare noalias i8* @calloc(i32, i32)
; The store here is not dead because the byval call reads it. ; The store here is not dead because the byval call reads it.
declare void @test19f({i32}* byval align 4 %P) declare void @test19f({i32}* byval align 4 %P)
define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp { define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp {
; CHECK-LABEL: @test19( ; CHECK-LABEL: @test19(
; CHECK-NEXT: bb: ; CHECK-NEXT: bb:
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0
; CHECK-NEXT: store i32 912, i32* [[TMP7]] ; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4
; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) ; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
bb: bb:
%tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0 %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0
store i32 912, i32* %tmp7 store i32 912, i32* %tmp7
call void @test19f({i32}* byval align 4 %arg5) call void @test19f({i32}* byval align 4 %arg5)
ret void ret void
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} }
; TODO ; TODO
; We can remove redundant store, as noalias %p guarantees that the function does ; We can remove redundant store, as noalias %p guarantees that the function does
; only access it via %p. This also holds for the call to unknown_func even though ; only access it via %p. This also holds for the call to unknown_func even though
; it could unwind ; it could unwind
define void @test34(i32* noalias %p) { define void @test34(i32* noalias %p) {
; CHECK-LABEL: @test34( ; CHECK-LABEL: @test34(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: call void @unknown_func() ; CHECK-NEXT: call void @unknown_func()
; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: store i32 0, i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %p store i32 1, i32* %p
call void @unknown_func() call void @unknown_func()
store i32 0, i32* %p store i32 0, i32* %p
ret void ret void
} }
; Remove redundant store even with an unwinding function in the same block ; Remove redundant store even with an unwinding function in the same block
define void @test35(i32* noalias %p) { define void @test35(i32* noalias %p) {
; CHECK-LABEL: @test35( ; CHECK-LABEL: @test35(
; CHECK-NEXT: call void @unknown_func() ; CHECK-NEXT: call void @unknown_func()
; CHECK-NEXT: store i32 0, i32* [[P:%.*]] ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
call void @unknown_func() call void @unknown_func()
store i32 1, i32* %p store i32 1, i32* %p
store i32 0, i32* %p store i32 0, i32* %p
ret void ret void
} }
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} }
; I think this case is currently handled incorrectly by memdeps dse ; I think this case is currently handled incorrectly by memdeps dse
; throwing should leave store i32 1, not remove from the free. ; throwing should leave store i32 1, not remove from the free.
declare void @free(i8* nocapture) declare void @free(i8* nocapture)
define void @test41(i32* noalias %P) { define void @test41(i32* noalias %P) {
; CHECK-LABEL: @test41( ; CHECK-LABEL: @test41(
; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P:%.*]] to i8* ; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P:%.*]] to i8*
; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: store i32 1, i32* [[P]], align 4
; CHECK-NEXT: call void @unknown_func() ; CHECK-NEXT: call void @unknown_func()
; CHECK-NEXT: store i32 2, i32* [[P]] ; CHECK-NEXT: store i32 2, i32* [[P]], align 4
; CHECK-NEXT: call void @free(i8* [[P2]]) ; CHECK-NEXT: call void @free(i8* [[P2]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%P2 = bitcast i32* %P to i8* %P2 = bitcast i32* %P to i8*
store i32 1, i32* %P store i32 1, i32* %P
call void @unknown_func() call void @unknown_func()
store i32 2, i32* %P store i32 2, i32* %P
call void @free(i8* %P2) call void @free(i8* %P2)
ret void ret void
} }
define void @test42(i32* %P, i32* %Q) { define void @test42(i32* %P, i32* %Q) {
; CHECK-LABEL: @test42( ; CHECK-LABEL: @test42(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8* ; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8*
; CHECK-NEXT: store i32 2, i32* [[Q:%.*]] ; CHECK-NEXT: store i32 2, i32* [[Q:%.*]], align 4
; CHECK-NEXT: store i8 3, i8* [[P2]] ; CHECK-NEXT: store i8 3, i8* [[P2]], align 1
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
%P2 = bitcast i32* %P to i8* %P2 = bitcast i32* %P to i8*
store i32 2, i32* %Q store i32 2, i32* %Q
store i8 3, i8* %P2 store i8 3, i8* %P2
ret void ret void
} }
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llvm/test/Transforms/DeadStoreElimination/merge-stores.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -dse -enable-dse-partial-store-merging -S < %s | FileCheck %s ; RUN: opt -dse -enable-dse-partial-store-merging -S < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
define void @byte_by_byte_replacement(i32 *%ptr) { define void @byte_by_byte_replacement(i32 *%ptr) {
; CHECK-LABEL: @byte_by_byte_replacement( ; CHECK-LABEL: @byte_by_byte_replacement(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 202050057, i32* [[PTR:%.*]] ; CHECK-NEXT: store i32 202050057, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
;; This store's value should be modified as it should be better to use one ;; This store's value should be modified as it should be better to use one
;; larger store than several smaller ones. ;; larger store than several smaller ones.
;; store will turn into 0x0C0B0A09 == 202050057 ;; store will turn into 0x0C0B0A09 == 202050057
store i32 305419896, i32* %ptr ; 0x12345678 store i32 305419896, i32* %ptr ; 0x12345678
%bptr = bitcast i32* %ptr to i8* %bptr = bitcast i32* %ptr to i8*
Show All 9 Linesentry:
store i8 12, i8* %bptr3 ; 0C store i8 12, i8* %bptr3 ; 0C
; 0x0C0B0A09 ; 0x0C0B0A09
ret void ret void
} }
define void @word_replacement(i64 *%ptr) { define void @word_replacement(i64 *%ptr) {
; CHECK-LABEL: @word_replacement( ; CHECK-LABEL: @word_replacement(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i64 8106482645252179720, i64* [[PTR:%.*]] ; CHECK-NEXT: store i64 8106482645252179720, i64* [[PTR:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i64 72623859790382856, i64* %ptr ; 0x0102030405060708 store i64 72623859790382856, i64* %ptr ; 0x0102030405060708
%wptr = bitcast i64* %ptr to i16* %wptr = bitcast i64* %ptr to i16*
%wptr1 = getelementptr inbounds i16, i16* %wptr, i64 1 %wptr1 = getelementptr inbounds i16, i16* %wptr, i64 1
%wptr2 = getelementptr inbounds i16, i16* %wptr, i64 2 %wptr2 = getelementptr inbounds i16, i16* %wptr, i64 2
%wptr3 = getelementptr inbounds i16, i16* %wptr, i64 3 %wptr3 = getelementptr inbounds i16, i16* %wptr, i64 3
;; We should be able to merge these two stores with the i64 one above ;; We should be able to merge these two stores with the i64 one above
; value (not bytes) stored before ; 0x0102030405060708 ; value (not bytes) stored before ; 0x0102030405060708
store i16 4128, i16* %wptr1 ; 1020 store i16 4128, i16* %wptr1 ; 1020
store i16 28800, i16* %wptr3 ; 7080 store i16 28800, i16* %wptr3 ; 7080
; 0x7080030410200708 ; 0x7080030410200708
ret void ret void
} }
define void @differently_sized_replacements(i64 *%ptr) { define void @differently_sized_replacements(i64 *%ptr) {
; CHECK-LABEL: @differently_sized_replacements( ; CHECK-LABEL: @differently_sized_replacements(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i64 578437695752307201, i64* [[PTR:%.*]] ; CHECK-NEXT: store i64 578437695752307201, i64* [[PTR:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f
%bptr = bitcast i64* %ptr to i8* %bptr = bitcast i64* %ptr to i8*
%bptr6 = getelementptr inbounds i8, i8* %bptr, i64 6 %bptr6 = getelementptr inbounds i8, i8* %bptr, i64 6
%wptr = bitcast i64* %ptr to i16* %wptr = bitcast i64* %ptr to i16*
%wptr2 = getelementptr inbounds i16, i16* %wptr, i64 2 %wptr2 = getelementptr inbounds i16, i16* %wptr, i64 2
%dptr = bitcast i64* %ptr to i32* %dptr = bitcast i64* %ptr to i32*
;; We should be able to merge all these stores with the i64 one above ;; We should be able to merge all these stores with the i64 one above
; value (not bytes) stored before ; 0x08090a0b0c0d0e0f ; value (not bytes) stored before ; 0x08090a0b0c0d0e0f
store i8 7, i8* %bptr6 ; 07 store i8 7, i8* %bptr6 ; 07
store i16 1541, i16* %wptr2 ; 0605 store i16 1541, i16* %wptr2 ; 0605
store i32 67305985, i32* %dptr ; 04030201 store i32 67305985, i32* %dptr ; 04030201
; 0x0807060504030201 ; 0x0807060504030201
ret void ret void
} }
define void @multiple_replacements_to_same_byte(i64 *%ptr) { define void @multiple_replacements_to_same_byte(i64 *%ptr) {
; CHECK-LABEL: @multiple_replacements_to_same_byte( ; CHECK-LABEL: @multiple_replacements_to_same_byte(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i64 579005069522043393, i64* [[PTR:%.*]] ; CHECK-NEXT: store i64 579005069522043393, i64* [[PTR:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f
%bptr = bitcast i64* %ptr to i8* %bptr = bitcast i64* %ptr to i8*
%bptr3 = getelementptr inbounds i8, i8* %bptr, i64 3 %bptr3 = getelementptr inbounds i8, i8* %bptr, i64 3
%wptr = bitcast i64* %ptr to i16* %wptr = bitcast i64* %ptr to i16*
%wptr1 = getelementptr inbounds i16, i16* %wptr, i64 1 %wptr1 = getelementptr inbounds i16, i16* %wptr, i64 1
%dptr = bitcast i64* %ptr to i32* %dptr = bitcast i64* %ptr to i32*
;; We should be able to merge all these stores with the i64 one above ;; We should be able to merge all these stores with the i64 one above
; value (not bytes) stored before ; 0x08090a0b0c0d0e0f ; value (not bytes) stored before ; 0x08090a0b0c0d0e0f
store i8 7, i8* %bptr3 ; 07 store i8 7, i8* %bptr3 ; 07
store i16 1541, i16* %wptr1 ; 0605 store i16 1541, i16* %wptr1 ; 0605
store i32 67305985, i32* %dptr ; 04030201 store i32 67305985, i32* %dptr ; 04030201
; 0x08090a0b04030201 ; 0x08090a0b04030201
ret void ret void
} }
define void @merged_merges(i64 *%ptr) { define void @merged_merges(i64 *%ptr) {
; CHECK-LABEL: @merged_merges( ; CHECK-LABEL: @merged_merges(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i64 579005069572506113, i64* [[PTR:%.*]] ; CHECK-NEXT: store i64 579005069572506113, i64* [[PTR:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f store i64 579005069656919567, i64* %ptr ; 0x08090a0b0c0d0e0f
%bptr = bitcast i64* %ptr to i8* %bptr = bitcast i64* %ptr to i8*
%bptr3 = getelementptr inbounds i8, i8* %bptr, i64 3 %bptr3 = getelementptr inbounds i8, i8* %bptr, i64 3
%wptr = bitcast i64* %ptr to i16* %wptr = bitcast i64* %ptr to i16*
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;; Test case from PR31777 ;; Test case from PR31777
%union.U = type { i64 } %union.U = type { i64 }
define void @foo(%union.U* nocapture %u) { define void @foo(%union.U* nocapture %u) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[UNION_U:%.*]], %union.U* [[U:%.*]], i64 0, i32 0 ; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[UNION_U:%.*]], %union.U* [[U:%.*]], i64 0, i32 0
; CHECK-NEXT: store i64 42, i64* [[I]], align 8 ; CHECK-NEXT: store i64 42, i64* [[I]], align 8, !tbaa !0, !noalias !3, !nontemporal !4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%i = getelementptr inbounds %union.U, %union.U* %u, i64 0, i32 0 %i = getelementptr inbounds %union.U, %union.U* %u, i64 0, i32 0
store i64 0, i64* %i, align 8, !dbg !22, !tbaa !26, !noalias !30, !nontemporal !29 store i64 0, i64* %i, align 8, !dbg !22, !tbaa !26, !noalias !30, !nontemporal !29
%s = bitcast %union.U* %u to i16* %s = bitcast %union.U* %u to i16*
store i16 42, i16* %s, align 8 store i16 42, i16* %s, align 8
ret void ret void
} }
; Don't crash by operating on stale data if we merge (kill) the last 2 stores. ; Don't crash by operating on stale data if we merge (kill) the last 2 stores.
define void @PR34074(i32* %x, i64* %y) { define void @PR34074(i32* %x, i64* %y) {
; CHECK-LABEL: @PR34074( ; CHECK-LABEL: @PR34074(
; CHECK-NEXT: store i64 42, i64* %y ; CHECK-NEXT: store i64 42, i64* [[Y:%.*]], align 8
; CHECK-NEXT: store i32 4, i32* %x ; CHECK-NEXT: store i32 4, i32* [[X:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i64 42, i64* %y ; independent store store i64 42, i64* %y ; independent store
%xbc = bitcast i32* %x to i8* %xbc = bitcast i32* %x to i8*
store i32 0, i32* %x ; big store of constant store i32 0, i32* %x ; big store of constant
store i8 4, i8* %xbc ; small store with mergeable constant store i8 4, i8* %xbc ; small store with mergeable constant
ret void ret void
} }
; We can't eliminate the last store because P and Q may alias. ; We can't eliminate the last store because P and Q may alias.
define void @PR36129(i32* %P, i32* %Q) { define void @PR36129(i32* %P, i32* %Q) {
; CHECK-LABEL: @PR36129( ; CHECK-LABEL: @PR36129(
; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8* ; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8*
; CHECK-NEXT: store i32 2, i32* [[Q:%.*]] ; CHECK-NEXT: store i32 2, i32* [[Q:%.*]], align 4
; CHECK-NEXT: store i8 3, i8* [[P2]] ; CHECK-NEXT: store i8 3, i8* [[P2]], align 1
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 1, i32* %P store i32 1, i32* %P
%P2 = bitcast i32* %P to i8* %P2 = bitcast i32* %P to i8*
store i32 2, i32* %Q store i32 2, i32* %Q
store i8 3, i8* %P2 store i8 3, i8* %P2
ret void ret void
} }
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llvm/test/Transforms/EarlyCSE/guards.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -early-cse < %s | FileCheck %s --check-prefixes=CHECK,NO_ASSUME ; RUN: opt -S -early-cse < %s | FileCheck %s --check-prefixes=CHECK,NO_ASSUME
; RUN: opt < %s -S -basicaa -early-cse-memssa | FileCheck %s --check-prefixes=CHECK,NO_ASSUME ; RUN: opt < %s -S -basicaa -early-cse-memssa | FileCheck %s --check-prefixes=CHECK,NO_ASSUME
; RUN: opt < %s -S -basicaa -early-cse-memssa --enable-knowledge-retention | FileCheck %s --check-prefixes=CHECK,USE_ASSUME ; RUN: opt < %s -S -basicaa -early-cse-memssa --enable-knowledge-retention | FileCheck %s --check-prefixes=CHECK,USE_ASSUME
declare void @llvm.experimental.guard(i1,...) declare void @llvm.experimental.guard(i1,...)
declare void @llvm.assume(i1) declare void @llvm.assume(i1)
define i32 @test0(i32* %ptr, i1 %cond) { define i32 @test0(i32* %ptr, i1 %cond) {
; We can do store to load forwarding over a guard, since it does not ; We can do store to load forwarding over a guard, since it does not
; clobber memory ; clobber memory
; NO_ASSUME-LABEL: @test0( ; NO_ASSUME-LABEL: @test0(
; NO_ASSUME-NEXT: store i32 40, i32* [[PTR:%.*]] ; NO_ASSUME-NEXT: store i32 40, i32* [[PTR:%.*]], align 4
; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND:%.*]]) [ "deopt"() ] ; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND:%.*]]) [ "deopt"() ]
; NO_ASSUME-NEXT: ret i32 40 ; NO_ASSUME-NEXT: ret i32 40
; ;
; USE_ASSUME-LABEL: @test0( ; USE_ASSUME-LABEL: @test0(
; USE_ASSUME-NEXT: store i32 40, i32* [[PTR:%.*]] ; USE_ASSUME-NEXT: store i32 40, i32* [[PTR:%.*]], align 4
; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND:%.*]]) [ "deopt"() ] ; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND:%.*]]) [ "deopt"() ]
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ]
; USE_ASSUME-NEXT: ret i32 40 ; USE_ASSUME-NEXT: ret i32 40
; ;
store i32 40, i32* %ptr store i32 40, i32* %ptr
call void(i1,...) @llvm.experimental.guard(i1 %cond) [ "deopt"() ] call void(i1,...) @llvm.experimental.guard(i1 %cond) [ "deopt"() ]
%rval = load i32, i32* %ptr %rval = load i32, i32* %ptr
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Linesright:
br label %left br label %left
} }
define void @test6(i1 %c, i32* %ptr) { define void @test6(i1 %c, i32* %ptr) {
; Check that we do not DSE over calls to @llvm.experimental.guard. ; Check that we do not DSE over calls to @llvm.experimental.guard.
; Guard intrinsics do _read_ memory, so th call to guard below needs ; Guard intrinsics do _read_ memory, so th call to guard below needs
; to see the store of 500 to %ptr ; to see the store of 500 to %ptr
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK-NEXT: store i32 500, i32* [[PTR:%.*]] ; CHECK-NEXT: store i32 500, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[C:%.*]]) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[C:%.*]]) [ "deopt"() ]
; CHECK-NEXT: store i32 600, i32* [[PTR]] ; CHECK-NEXT: store i32 600, i32* [[PTR]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i32 500, i32* %ptr store i32 500, i32* %ptr
call void(i1,...) @llvm.experimental.guard(i1 %c) [ "deopt"() ] call void(i1,...) @llvm.experimental.guard(i1 %c) [ "deopt"() ]
store i32 600, i32* %ptr store i32 600, i32* %ptr
ret void ret void
Show All 15 Lines;
ret void ret void
} }
define void @test08(i32 %a, i32 %b, i32* %ptr) { define void @test08(i32 %a, i32 %b, i32* %ptr) {
; Check that we deal correctly with stores when removing guards in the same ; Check that we deal correctly with stores when removing guards in the same
; block in case when the condition is not recalculated. ; block in case when the condition is not recalculated.
; NO_ASSUME-LABEL: @test08( ; NO_ASSUME-LABEL: @test08(
; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; NO_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]] ; NO_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; NO_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: @test08( ; USE_ASSUME-LABEL: @test08(
; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; USE_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]] ; USE_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ]
; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
store i32 100, i32* %ptr store i32 100, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 200, i32* %ptr store i32 200, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 300, i32* %ptr store i32 300, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 400, i32* %ptr store i32 400, i32* %ptr
ret void ret void
} }
define void @test09(i32 %a, i32 %b, i1 %c, i32* %ptr) { define void @test09(i32 %a, i32 %b, i1 %c, i32* %ptr) {
; Similar to test08, but with more control flow. ; Similar to test08, but with more control flow.
; TODO: Can we get rid of the store in the end of entry given that it is ; TODO: Can we get rid of the store in the end of entry given that it is
; post-dominated by other stores? ; post-dominated by other stores?
; NO_ASSUME-LABEL: @test09( ; NO_ASSUME-LABEL: @test09(
; NO_ASSUME-NEXT: entry: ; NO_ASSUME-NEXT: entry:
; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; NO_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]] ; NO_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; NO_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; NO_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; NO_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; NO_ASSUME: if.true: ; NO_ASSUME: if.true:
; NO_ASSUME-NEXT: store i32 500, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 500, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: br label [[MERGE:%.*]] ; NO_ASSUME-NEXT: br label [[MERGE:%.*]]
; NO_ASSUME: if.false: ; NO_ASSUME: if.false:
; NO_ASSUME-NEXT: store i32 600, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 600, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: br label [[MERGE]] ; NO_ASSUME-NEXT: br label [[MERGE]]
; NO_ASSUME: merge: ; NO_ASSUME: merge:
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: @test09( ; USE_ASSUME-LABEL: @test09(
; USE_ASSUME-NEXT: entry: ; USE_ASSUME-NEXT: entry:
; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; USE_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]] ; USE_ASSUME-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; USE_ASSUME-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ]
; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; USE_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; USE_ASSUME: if.true: ; USE_ASSUME: if.true:
; USE_ASSUME-NEXT: store i32 500, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 500, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br label [[MERGE:%.*]] ; USE_ASSUME-NEXT: br label [[MERGE:%.*]]
; USE_ASSUME: if.false: ; USE_ASSUME: if.false:
; USE_ASSUME-NEXT: store i32 600, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 600, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br label [[MERGE]] ; USE_ASSUME-NEXT: br label [[MERGE]]
; USE_ASSUME: merge: ; USE_ASSUME: merge:
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
store i32 100, i32* %ptr store i32 100, i32* %ptr
Show All 22 Lines
define void @test10(i32 %a, i32 %b, i1 %c, i32* %ptr) { define void @test10(i32 %a, i32 %b, i1 %c, i32* %ptr) {
; Make sure that non-dominating guards do not cause other guards removal. ; Make sure that non-dominating guards do not cause other guards removal.
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK: if.true: ; CHECK: if.true:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; CHECK-NEXT: store i32 100, i32* [[PTR:%.*]] ; CHECK-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false: ; CHECK: if.false:
; CHECK-NEXT: store i32 200, i32* [[PTR]] ; CHECK-NEXT: store i32 200, i32* [[PTR]], align 4
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: store i32 300, i32* [[PTR]] ; CHECK-NEXT: store i32 300, i32* [[PTR]], align 4
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; CHECK-NEXT: store i32 400, i32* [[PTR]] ; CHECK-NEXT: store i32 400, i32* [[PTR]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
br i1 %c, label %if.true, label %if.false br i1 %c, label %if.true, label %if.false
if.true: if.true:
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines;
ret void ret void
} }
define void @test13(i32 %a, i32 %b, i32* %ptr) { define void @test13(i32 %a, i32 %b, i32* %ptr) {
; Check that we deal correctly with stores when removing guards due to assume. ; Check that we deal correctly with stores when removing guards due to assume.
; NO_ASSUME-LABEL: @test13( ; NO_ASSUME-LABEL: @test13(
; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; NO_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]]) ; NO_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]])
; NO_ASSUME-NEXT: store i32 400, i32* [[PTR:%.*]] ; NO_ASSUME-NEXT: store i32 400, i32* [[PTR:%.*]], align 4
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: @test13( ; USE_ASSUME-LABEL: @test13(
; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; USE_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]]) ; USE_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]])
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR:%.*]], i64 4), "nonnull"(i32* [[PTR]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR:%.*]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ]
; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
call void @llvm.assume(i1 %cmp) call void @llvm.assume(i1 %cmp)
store i32 100, i32* %ptr store i32 100, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 200, i32* %ptr store i32 200, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 300, i32* %ptr store i32 300, i32* %ptr
call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ] call void (i1, ...) @llvm.experimental.guard(i1 %cmp) [ "deopt"() ]
store i32 400, i32* %ptr store i32 400, i32* %ptr
ret void ret void
} }
define void @test14(i32 %a, i32 %b, i1 %c, i32* %ptr) { define void @test14(i32 %a, i32 %b, i1 %c, i32* %ptr) {
; Similar to test13, but with more control flow. ; Similar to test13, but with more control flow.
; TODO: Can we get rid of the store in the end of entry given that it is ; TODO: Can we get rid of the store in the end of entry given that it is
; post-dominated by other stores? ; post-dominated by other stores?
; NO_ASSUME-LABEL: @test14( ; NO_ASSUME-LABEL: @test14(
; NO_ASSUME-NEXT: entry: ; NO_ASSUME-NEXT: entry:
; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; NO_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; NO_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]]) ; NO_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]])
; NO_ASSUME-NEXT: store i32 400, i32* [[PTR:%.*]] ; NO_ASSUME-NEXT: store i32 400, i32* [[PTR:%.*]], align 4
; NO_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; NO_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; NO_ASSUME: if.true: ; NO_ASSUME: if.true:
; NO_ASSUME-NEXT: store i32 500, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 500, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: br label [[MERGE:%.*]] ; NO_ASSUME-NEXT: br label [[MERGE:%.*]]
; NO_ASSUME: if.false: ; NO_ASSUME: if.false:
; NO_ASSUME-NEXT: store i32 600, i32* [[PTR]] ; NO_ASSUME-NEXT: store i32 600, i32* [[PTR]], align 4
; NO_ASSUME-NEXT: br label [[MERGE]] ; NO_ASSUME-NEXT: br label [[MERGE]]
; NO_ASSUME: merge: ; NO_ASSUME: merge:
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: @test14( ; USE_ASSUME-LABEL: @test14(
; USE_ASSUME-NEXT: entry: ; USE_ASSUME-NEXT: entry:
; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; USE_ASSUME-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; USE_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]]) ; USE_ASSUME-NEXT: call void @llvm.assume(i1 [[CMP]])
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR:%.*]], i64 4), "nonnull"(i32* [[PTR]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[PTR:%.*]], i64 4), "nonnull"(i32* [[PTR]]), "align"(i32* [[PTR]], i64 4) ]
; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 400, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; USE_ASSUME-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; USE_ASSUME: if.true: ; USE_ASSUME: if.true:
; USE_ASSUME-NEXT: store i32 500, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 500, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br label [[MERGE:%.*]] ; USE_ASSUME-NEXT: br label [[MERGE:%.*]]
; USE_ASSUME: if.false: ; USE_ASSUME: if.false:
; USE_ASSUME-NEXT: store i32 600, i32* [[PTR]] ; USE_ASSUME-NEXT: store i32 600, i32* [[PTR]], align 4
; USE_ASSUME-NEXT: br label [[MERGE]] ; USE_ASSUME-NEXT: br label [[MERGE]]
; USE_ASSUME: merge: ; USE_ASSUME: merge:
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
call void @llvm.assume(i1 %cmp) call void @llvm.assume(i1 %cmp)
Show All 23 Lines
define void @test15(i32 %a, i32 %b, i1 %c, i32* %ptr) { define void @test15(i32 %a, i32 %b, i1 %c, i32* %ptr) {
; Make sure that non-dominating assumes do not cause guards removal. ; Make sure that non-dominating assumes do not cause guards removal.
; CHECK-LABEL: @test15( ; CHECK-LABEL: @test15(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK: if.true: ; CHECK: if.true:
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: store i32 100, i32* [[PTR:%.*]] ; CHECK-NEXT: store i32 100, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[MERGE:%.*]] ; CHECK-NEXT: br label [[MERGE:%.*]]
; CHECK: if.false: ; CHECK: if.false:
; CHECK-NEXT: store i32 200, i32* [[PTR]] ; CHECK-NEXT: store i32 200, i32* [[PTR]], align 4
; CHECK-NEXT: br label [[MERGE]] ; CHECK-NEXT: br label [[MERGE]]
; CHECK: merge: ; CHECK: merge:
; CHECK-NEXT: store i32 300, i32* [[PTR]] ; CHECK-NEXT: store i32 300, i32* [[PTR]], align 4
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) [ "deopt"() ]
; CHECK-NEXT: store i32 400, i32* [[PTR]] ; CHECK-NEXT: store i32 400, i32* [[PTR]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
br i1 %c, label %if.true, label %if.false br i1 %c, label %if.true, label %if.false
if.true: if.true:
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/Transforms/EarlyCSE/invariant-loads.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; NO_ASSUME-LABEL: @test_dse1( ; NO_ASSUME-LABEL: @test_dse1(
; NO_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0 ; NO_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0
; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[V1]]) ; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[V1]])
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: @test_dse1( ; USE_ASSUME-LABEL: @test_dse1(
; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0 ; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0
; USE_ASSUME-NEXT: call void @clobber_and_use(i32 [[V1]]) ; USE_ASSUME-NEXT: call void @clobber_and_use(i32 [[V1]])
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]), "align"(i32* [[P]], i64 4) ]
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
%v1 = load i32, i32* %p, !invariant.load !{} %v1 = load i32, i32* %p, !invariant.load !{}
call void @clobber_and_use(i32 %v1) call void @clobber_and_use(i32 %v1)
store i32 %v1, i32* %p store i32 %v1, i32* %p
ret void ret void
} }
; By assumption, v1 must equal v2 (TODO) ; By assumption, v1 must equal v2 (TODO)
define void @test_false_negative_dse2(i32* %p, i32 %v2) { define void @test_false_negative_dse2(i32* %p, i32 %v2) {
; CHECK-LABEL: @test_false_negative_dse2( ; CHECK-LABEL: @test_false_negative_dse2(
; CHECK-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0 ; CHECK-NEXT: [[V1:%.*]] = load i32, i32* [[P:%.*]], align 4, !invariant.load !0
; CHECK-NEXT: call void @clobber_and_use(i32 [[V1]]) ; CHECK-NEXT: call void @clobber_and_use(i32 [[V1]])
; CHECK-NEXT: store i32 [[V2:%.*]], i32* [[P]] ; CHECK-NEXT: store i32 [[V2:%.*]], i32* [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%v1 = load i32, i32* %p, !invariant.load !{} %v1 = load i32, i32* %p, !invariant.load !{}
call void @clobber_and_use(i32 %v1) call void @clobber_and_use(i32 %v1)
store i32 %v2, i32* %p store i32 %v2, i32* %p
ret void ret void
} }
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/Transforms/EarlyCSE/invariant.start.ll

Show All 29 Lines;
ret i8 %Diff ret i8 %Diff
} }
; Trivial Store->load forwarding over invariant.start ; Trivial Store->load forwarding over invariant.start
define i8 @test_bypass2(i8 *%P) { define i8 @test_bypass2(i8 *%P) {
; NO_ASSUME-LABEL: define {{[^@]+}}@test_bypass2 ; NO_ASSUME-LABEL: define {{[^@]+}}@test_bypass2
; NO_ASSUME-SAME: (i8* [[P:%.*]]) ; NO_ASSUME-SAME: (i8* [[P:%.*]])
; NO_ASSUME-NEXT: store i8 42, i8* [[P]] ; NO_ASSUME-NEXT: store i8 42, i8* [[P]], align 1
; NO_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]]) ; NO_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]])
; NO_ASSUME-NEXT: ret i8 42 ; NO_ASSUME-NEXT: ret i8 42
; ;
; USE_ASSUME-LABEL: define {{[^@]+}}@test_bypass2 ; USE_ASSUME-LABEL: define {{[^@]+}}@test_bypass2
; USE_ASSUME-SAME: (i8* [[P:%.*]]) ; USE_ASSUME-SAME: (i8* [[P:%.*]])
; USE_ASSUME-NEXT: store i8 42, i8* [[P]] ; USE_ASSUME-NEXT: store i8 42, i8* [[P]], align 1
; USE_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]]) ; USE_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]])
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[P]], i64 1), "nonnull"(i8* [[P]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[P]], i64 1), "nonnull"(i8* [[P]]) ]
; USE_ASSUME-NEXT: ret i8 42 ; USE_ASSUME-NEXT: ret i8 42
; ;
store i8 42, i8* %P store i8 42, i8* %P
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P) %i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P)
%V1 = load i8, i8* %P %V1 = load i8, i8* %P
ret i8 %V1 ret i8 %V1
} }
; We can DSE over invariant.start calls, since the first store to ; We can DSE over invariant.start calls, since the first store to
; %P is valid, and the second store is actually unreachable based on semantics ; %P is valid, and the second store is actually unreachable based on semantics
; of invariant.start. ; of invariant.start.
define void @test_bypass3(i8* %P) { define void @test_bypass3(i8* %P) {
; NO_ASSUME-LABEL: define {{[^@]+}}@test_bypass3 ; NO_ASSUME-LABEL: define {{[^@]+}}@test_bypass3
; NO_ASSUME-SAME: (i8* [[P:%.*]]) ; NO_ASSUME-SAME: (i8* [[P:%.*]])
; NO_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]]) ; NO_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]])
; NO_ASSUME-NEXT: store i8 60, i8* [[P]] ; NO_ASSUME-NEXT: store i8 60, i8* [[P]], align 1
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: define {{[^@]+}}@test_bypass3 ; USE_ASSUME-LABEL: define {{[^@]+}}@test_bypass3
; USE_ASSUME-SAME: (i8* [[P:%.*]]) ; USE_ASSUME-SAME: (i8* [[P:%.*]])
; USE_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]]) ; USE_ASSUME-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]])
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[P]], i64 1), "nonnull"(i8* [[P]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[P]], i64 1), "nonnull"(i8* [[P]]) ]
; USE_ASSUME-NEXT: store i8 60, i8* [[P]] ; USE_ASSUME-NEXT: store i8 60, i8* [[P]], align 1
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
store i8 50, i8* %P store i8 50, i8* %P
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P) %i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P)
store i8 60, i8* %P store i8 60, i8* %P
ret void ret void
} }
; FIXME: Now the first store can actually be eliminated, since there is no read within ; FIXME: Now the first store can actually be eliminated, since there is no read within
; the invariant region, between start and end. ; the invariant region, between start and end.
define void @test_bypass4(i8* %P) { define void @test_bypass4(i8* %P) {
; CHECK-LABEL: define {{[^@]+}}@test_bypass4 ; CHECK-LABEL: define {{[^@]+}}@test_bypass4
; CHECK-SAME: (i8* [[P:%.*]]) ; CHECK-SAME: (i8* [[P:%.*]])
; CHECK-NEXT: store i8 50, i8* [[P]] ; CHECK-NEXT: store i8 50, i8* [[P]], align 1
; CHECK-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]]) ; CHECK-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* [[P]])
; CHECK-NEXT: call void @llvm.invariant.end.p0i8({}* [[I]], i64 1, i8* [[P]]) ; CHECK-NEXT: call void @llvm.invariant.end.p0i8({}* [[I]], i64 1, i8* [[P]])
; CHECK-NEXT: store i8 60, i8* [[P]] ; CHECK-NEXT: store i8 60, i8* [[P]], align 1
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
store i8 50, i8* %P store i8 50, i8* %P
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P) %i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %P)
call void @llvm.invariant.end.p0i8({}* %i, i64 1, i8* %P) call void @llvm.invariant.end.p0i8({}* %i, i64 1, i8* %P)
store i8 60, i8* %P store i8 60, i8* %P
▲ Show 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
; NO_ASSUME-NEXT: call void @clobber() ; NO_ASSUME-NEXT: call void @clobber()
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: define {{[^@]+}}@test_dse_before_load ; USE_ASSUME-LABEL: define {{[^@]+}}@test_dse_before_load
; USE_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]]) ; USE_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]])
; USE_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]]) ; USE_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]])
; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4 ; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4
; USE_ASSUME-NEXT: call void @clobber() ; USE_ASSUME-NEXT: call void @clobber()
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]), "align"(i32* [[P]], i64 4) ]
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
call {}* @llvm.invariant.start.p0i32(i64 4, i32* %p) call {}* @llvm.invariant.start.p0i32(i64 4, i32* %p)
%v1 = load i32, i32* %p %v1 = load i32, i32* %p
call void @clobber() call void @clobber()
store i32 %v1, i32* %p store i32 %v1, i32* %p
ret void ret void
} }
define void @test_dse_after_load(i32* %p, i1 %cnd) { define void @test_dse_after_load(i32* %p, i1 %cnd) {
; NO_ASSUME-LABEL: define {{[^@]+}}@test_dse_after_load ; NO_ASSUME-LABEL: define {{[^@]+}}@test_dse_after_load
; NO_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]]) ; NO_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]])
; NO_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4 ; NO_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4
; NO_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]]) ; NO_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]])
; NO_ASSUME-NEXT: call void @clobber() ; NO_ASSUME-NEXT: call void @clobber()
; NO_ASSUME-NEXT: ret void ; NO_ASSUME-NEXT: ret void
; ;
; USE_ASSUME-LABEL: define {{[^@]+}}@test_dse_after_load ; USE_ASSUME-LABEL: define {{[^@]+}}@test_dse_after_load
; USE_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]]) ; USE_ASSUME-SAME: (i32* [[P:%.*]], i1 [[CND:%.*]])
; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4 ; USE_ASSUME-NEXT: [[V1:%.*]] = load i32, i32* [[P]], align 4
; USE_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]]) ; USE_ASSUME-NEXT: [[TMP1:%.*]] = call {}* @llvm.invariant.start.p0i32(i64 4, i32* [[P]])
; USE_ASSUME-NEXT: call void @clobber() ; USE_ASSUME-NEXT: call void @clobber()
; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]) ] ; USE_ASSUME-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[P]], i64 4), "nonnull"(i32* [[P]]), "align"(i32* [[P]], i64 4) ]
; USE_ASSUME-NEXT: ret void ; USE_ASSUME-NEXT: ret void
; ;
%v1 = load i32, i32* %p %v1 = load i32, i32* %p
call {}* @llvm.invariant.start.p0i32(i64 4, i32* %p) call {}* @llvm.invariant.start.p0i32(i64 4, i32* %p)
call void @clobber() call void @clobber()
store i32 %v1, i32* %p store i32 %v1, i32* %p
ret void ret void
} }
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llvm/test/Transforms/GVN/invariant.group.ll

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines; CHECK: call void @bar(i8 42)
%newPtr = call i8* @getPointer(i8* %ptr) %newPtr = call i8* @getPointer(i8* %ptr)
%c = load i8, i8* %newPtr, !invariant.group !0 ; Can't assume anything, because we only have information about %ptr %c = load i8, i8* %newPtr, !invariant.group !0 ; Can't assume anything, because we only have information about %ptr
; CHECK: call void @bar(i8 %c) ; CHECK: call void @bar(i8 %c)
call void @bar(i8 %c) call void @bar(i8 %c)
%unknownValue = load i8, i8* @unknownPtr %unknownValue = load i8, i8* @unknownPtr
; FIXME: Can assume that %unknownValue == 42 ; FIXME: Can assume that %unknownValue == 42
; CHECK: store i8 %unknownValue, i8* %ptr, !invariant.group !0 ; CHECK: store i8 %unknownValue, i8* %ptr, align 1, !invariant.group !0
store i8 %unknownValue, i8* %ptr, !invariant.group !0 store i8 %unknownValue, i8* %ptr, !invariant.group !0
%newPtr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr) %newPtr2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %ptr)
; CHECK-NOT: load ; CHECK-NOT: load
%d = load i8, i8* %newPtr2, !invariant.group !0 %d = load i8, i8* %newPtr2, !invariant.group !0
; CHECK: ret i8 %unknownValue ; CHECK: ret i8 %unknownValue
ret i8 %d ret i8 %d
} }
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llvm/test/Transforms/GVN/non-integral-pointers.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -gvn -S < %s | FileCheck %s ; RUN: opt -gvn -S < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @f0(i1 %alwaysFalse, i64 %val, i64* %loc) { define void @f0(i1 %alwaysFalse, i64 %val, i64* %loc) {
; CHECK-LABEL: @f0( ; CHECK-LABEL: @f0(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i64 [[VAL:%.*]], i64* [[LOC:%.*]] ; CHECK-NEXT: store i64 [[VAL:%.*]], i64* [[LOC:%.*]], align 8
; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]] ; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
; CHECK: neverTaken: ; CHECK: neverTaken:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i64* [[LOC]] to i8 addrspace(4)** ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i64* [[LOC]] to i8 addrspace(4)**
; CHECK-NEXT: [[PTR:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[LOC_BC]] ; CHECK-NEXT: [[PTR:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[LOC_BC]], align 8
; CHECK-NEXT: store i8 5, i8 addrspace(4)* [[PTR]] ; CHECK-NEXT: store i8 5, i8 addrspace(4)* [[PTR]], align 1
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: alwaysTaken: ; CHECK: alwaysTaken:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store i64 %val, i64* %loc store i64 %val, i64* %loc
br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
neverTaken: neverTaken:
%loc.bc = bitcast i64* %loc to i8 addrspace(4)** %loc.bc = bitcast i64* %loc to i8 addrspace(4)**
%ptr = load i8 addrspace(4)*, i8 addrspace(4)** %loc.bc %ptr = load i8 addrspace(4)*, i8 addrspace(4)** %loc.bc
store i8 5, i8 addrspace(4)* %ptr store i8 5, i8 addrspace(4)* %ptr
ret void ret void
alwaysTaken: alwaysTaken:
ret void ret void
} }
define i64 @f1(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) { define i64 @f1(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) {
; CHECK-LABEL: @f1( ; CHECK-LABEL: @f1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store i8 addrspace(4)* [[VAL:%.*]], i8 addrspace(4)** [[LOC:%.*]] ; CHECK-NEXT: store i8 addrspace(4)* [[VAL:%.*]], i8 addrspace(4)** [[LOC:%.*]], align 8
; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]] ; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
; CHECK: neverTaken: ; CHECK: neverTaken:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)** [[LOC]] to i64* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)** [[LOC]] to i64*
; CHECK-NEXT: [[INT:%.*]] = load i64, i64* [[LOC_BC]] ; CHECK-NEXT: [[INT:%.*]] = load i64, i64* [[LOC_BC]], align 8
; CHECK-NEXT: ret i64 [[INT]] ; CHECK-NEXT: ret i64 [[INT]]
; CHECK: alwaysTaken: ; CHECK: alwaysTaken:
; CHECK-NEXT: ret i64 42 ; CHECK-NEXT: ret i64 42
; ;
entry: entry:
store i8 addrspace(4)* %val, i8 addrspace(4)** %loc store i8 addrspace(4)* %val, i8 addrspace(4)** %loc
br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
Show All 12 Lines
declare void @llvm.memset.p4i8.i64(i8 addrspace(4)* nocapture, i8, i64, i1) nounwind declare void @llvm.memset.p4i8.i64(i8 addrspace(4)* nocapture, i8, i64, i1) nounwind
; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.) ; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.)
define i8 addrspace(4)* @neg_forward_memset(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @neg_forward_memset(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_memset( ; CHECK-LABEL: @neg_forward_memset(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
; CHECK-NEXT: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false)
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false) call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false)
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
define <1 x i8 addrspace(4)*> @neg_forward_memset_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) { define <1 x i8 addrspace(4)*> @neg_forward_memset_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_memset_vload( ; CHECK-LABEL: @neg_forward_memset_vload(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
; CHECK-NEXT: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false)
; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]] ; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]]
; ;
entry: entry:
%loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)* %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false) call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false)
%ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
ret <1 x i8 addrspace(4)*> %ref ret <1 x i8 addrspace(4)*> %ref
} }
Show All 14 Lines;
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.) ; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.)
define i8 addrspace(4)* @neg_forward_store(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @neg_forward_store(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_store( ; CHECK-LABEL: @neg_forward_store(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
; CHECK-NEXT: store i64 5, i64 addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store i64 5, i64 addrspace(4)* [[LOC_BC]], align 8
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)*
store i64 5, i64 addrspace(4)* %loc.bc store i64 5, i64 addrspace(4)* %loc.bc
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
define <1 x i8 addrspace(4)*> @neg_forward_store_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) { define <1 x i8 addrspace(4)*> @neg_forward_store_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_store_vload( ; CHECK-LABEL: @neg_forward_store_vload(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
; CHECK-NEXT: store i64 5, i64 addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store i64 5, i64 addrspace(4)* [[LOC_BC]], align 8
; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]] ; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]]
; ;
entry: entry:
%loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i64 addrspace(4)* %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i64 addrspace(4)*
store i64 5, i64 addrspace(4)* %loc.bc store i64 5, i64 addrspace(4)* %loc.bc
%ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
ret <1 x i8 addrspace(4)*> %ref ret <1 x i8 addrspace(4)*> %ref
} }
; Nulls have known bit patterns, so we can forward ; Nulls have known bit patterns, so we can forward
define i8 addrspace(4)* @forward_store_zero(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @forward_store_zero(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @forward_store_zero( ; CHECK-LABEL: @forward_store_zero(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
; CHECK-NEXT: store i64 0, i64 addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store i64 0, i64 addrspace(4)* [[LOC_BC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* null ; CHECK-NEXT: ret i8 addrspace(4)* null
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)*
store i64 0, i64 addrspace(4)* %loc.bc store i64 0, i64 addrspace(4)* %loc.bc
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
; Nulls have known bit patterns, so we can forward ; Nulls have known bit patterns, so we can forward
define i8 addrspace(4)* @forward_store_zero2(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @forward_store_zero2(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @forward_store_zero2( ; CHECK-LABEL: @forward_store_zero2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i32> addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i32> addrspace(4)*
; CHECK-NEXT: store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* [[LOC_BC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* null ; CHECK-NEXT: ret i8 addrspace(4)* null
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i32> addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i32> addrspace(4)*
store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %loc.bc store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %loc.bc
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
@NonZeroConstant = constant <4 x i64> <i64 3, i64 3, i64 3, i64 3> @NonZeroConstant = constant <4 x i64> <i64 3, i64 3, i64 3, i64 3>
@ZeroConstant = constant <4 x i64> zeroinitializer @ZeroConstant = constant <4 x i64> zeroinitializer
; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.) ; Can't forward as the load might be dead. (Pretend we wrote out the alwaysfalse idiom above.)
define i8 addrspace(4)* @neg_forward_memcopy(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @neg_forward_memcopy(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_memcopy( ; CHECK-LABEL: @neg_forward_memcopy(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false)
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
%src.bc = bitcast <4 x i64>* @NonZeroConstant to i8* %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
define <1 x i8 addrspace(4)*> @neg_forward_memcpy_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) { define <1 x i8 addrspace(4)*> @neg_forward_memcpy_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
; CHECK-LABEL: @neg_forward_memcpy_vload( ; CHECK-LABEL: @neg_forward_memcpy_vload(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false)
; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]] ; CHECK-NEXT: ret <1 x i8 addrspace(4)*> [[REF]]
; ;
entry: entry:
%loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)* %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
%src.bc = bitcast <4 x i64>* @NonZeroConstant to i8* %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
%ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
ret <1 x i8 addrspace(4)*> %ref ret <1 x i8 addrspace(4)*> %ref
} }
; Can forward since we can do so w/o breaking types ; Can forward since we can do so w/o breaking types
; TODO: missed optimization ; TODO: missed optimization
define i8 addrspace(4)* @forward_memcpy_zero(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @forward_memcpy_zero(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @forward_memcpy_zero( ; CHECK-LABEL: @forward_memcpy_zero(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @ZeroConstant to i8*), i64 8, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @ZeroConstant to i8*), i64 8, i1 false)
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
%src.bc = bitcast <4 x i64>* @ZeroConstant to i8* %src.bc = bitcast <4 x i64>* @ZeroConstant to i8*
call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
declare void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* nocapture, i8* nocapture, i64, i1) nounwind
; Same as the neg_forward_store cases, but for non defs. ; Same as the neg_forward_store cases, but for non defs.
; (Pretend we wrote out the alwaysfalse idiom above.) ; (Pretend we wrote out the alwaysfalse idiom above.)
define i8 addrspace(4)* @neg_store_clobber(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @neg_store_clobber(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @neg_store_clobber( ; CHECK-LABEL: @neg_store_clobber(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
; CHECK-NEXT: store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1 ; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* %loc.bc store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* %loc.bc
%loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1 %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
declare void @use(<2 x i64>) inaccessiblememonly declare void @use(<2 x i64>) inaccessiblememonly
; Same as the neg_forward_store cases, but for non defs. ; Same as the neg_forward_store cases, but for non defs.
; (Pretend we wrote out the alwaysfalse idiom above.) ; (Pretend we wrote out the alwaysfalse idiom above.)
define i8 addrspace(4)* @neg_load_clobber(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @neg_load_clobber(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @neg_load_clobber( ; CHECK-LABEL: @neg_load_clobber(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
; CHECK-NEXT: [[V:%.*]] = load <2 x i64>, <2 x i64> addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: [[V:%.*]] = load <2 x i64>, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
; CHECK-NEXT: call void @use(<2 x i64> [[V]]) ; CHECK-NEXT: call void @use(<2 x i64> [[V]])
; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1 ; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]] ; CHECK-NEXT: [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]], align 8
; CHECK-NEXT: ret i8 addrspace(4)* [[REF]] ; CHECK-NEXT: ret i8 addrspace(4)* [[REF]]
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
%v = load <2 x i64>, <2 x i64> addrspace(4)* %loc.bc %v = load <2 x i64>, <2 x i64> addrspace(4)* %loc.bc
call void @use(<2 x i64> %v) call void @use(<2 x i64> %v)
%loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1 %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }
define i8 addrspace(4)* @store_clobber_zero(i8 addrspace(4)* addrspace(4)* %loc) { define i8 addrspace(4)* @store_clobber_zero(i8 addrspace(4)* addrspace(4)* %loc) {
; CHECK-LABEL: @store_clobber_zero( ; CHECK-LABEL: @store_clobber_zero(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)* ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* [[LOC_BC]] ; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1 ; CHECK-NEXT: [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
; CHECK-NEXT: ret i8 addrspace(4)* null ; CHECK-NEXT: ret i8 addrspace(4)* null
; ;
entry: entry:
%loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)* %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* %loc.bc store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* %loc.bc
%loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1 %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
%ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
ret i8 addrspace(4)* %ref ret i8 addrspace(4)* %ref
} }

llvm/test/Transforms/GVN/vscale.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S < %s -basicaa -gvn -dce | FileCheck %s ; RUN: opt -S < %s -basicaa -gvn -dce | FileCheck %s
; Analyze Load from clobbering Load. ; Analyze Load from clobbering Load.
define <vscale x 4 x i32> @load_store_clobber_load(<vscale x 4 x i32> *%p) { define <vscale x 4 x i32> @load_store_clobber_load(<vscale x 4 x i32> *%p) {
; CHECK-LABEL: @load_store_clobber_load( ; CHECK-LABEL: @load_store_clobber_load(
; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* undef ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* undef, align 16
; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD1]] ; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD1]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]]
; ;
%load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* undef store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* undef
%load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p ; <- load to be eliminated %load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p ; <- load to be eliminated
%add = add <vscale x 4 x i32> %load1, %load2 %add = add <vscale x 4 x i32> %load1, %load2
ret <vscale x 4 x i32> %add ret <vscale x 4 x i32> %add
} }
define <vscale x 4 x i32> @load_store_clobber_load_mayalias(<vscale x 4 x i32>* %p, <vscale x 4 x i32>* %p2) { define <vscale x 4 x i32> @load_store_clobber_load_mayalias(<vscale x 4 x i32>* %p, <vscale x 4 x i32>* %p2) {
; CHECK-LABEL: @load_store_clobber_load_mayalias( ; CHECK-LABEL: @load_store_clobber_load_mayalias(
; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P2:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P2:%.*]], align 16
; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]] ; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], align 16
; CHECK-NEXT: [[SUB:%.*]] = sub <vscale x 4 x i32> [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[SUB:%.*]] = sub <vscale x 4 x i32> [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[SUB]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[SUB]]
; ;
%load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p2 store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p2
%load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
%sub = sub <vscale x 4 x i32> %load1, %load2 %sub = sub <vscale x 4 x i32> %load1, %load2
ret <vscale x 4 x i32> %sub ret <vscale x 4 x i32> %sub
} }
define <vscale x 4 x i32> @load_store_clobber_load_noalias(<vscale x 4 x i32>* noalias %p, <vscale x 4 x i32>* noalias %p2) { define <vscale x 4 x i32> @load_store_clobber_load_noalias(<vscale x 4 x i32>* noalias %p, <vscale x 4 x i32>* noalias %p2) {
; CHECK-LABEL: @load_store_clobber_load_noalias( ; CHECK-LABEL: @load_store_clobber_load_noalias(
; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P2:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P2:%.*]], align 16
; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD1]] ; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD1]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]]
; ;
%load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p2 store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p2
%load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p ; <- load to be eliminated %load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p ; <- load to be eliminated
%add = add <vscale x 4 x i32> %load1, %load2 %add = add <vscale x 4 x i32> %load1, %load2
ret <vscale x 4 x i32> %add ret <vscale x 4 x i32> %add
} }
; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as MustAlias. ; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as MustAlias.
define i32 @load_clobber_load_gep1(<vscale x 4 x i32>* %p) { define i32 @load_clobber_load_gep1(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @load_clobber_load_gep1( ; CHECK-LABEL: @load_clobber_load_gep1(
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 0, i64 1 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 0, i64 1
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]] ; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to i32* ; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to i32*
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i32, i32* [[P2]], i64 1 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i32, i32* [[P2]], i64 1
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[GEP2]] ; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[GEP2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret i32 [[ADD]] ; CHECK-NEXT: ret i32 [[ADD]]
; ;
%gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 0, i64 1 %gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 0, i64 1
%load1 = load i32, i32* %gep1 %load1 = load i32, i32* %gep1
%p2 = bitcast <vscale x 4 x i32>* %p to i32* %p2 = bitcast <vscale x 4 x i32>* %p to i32*
%gep2 = getelementptr i32, i32* %p2, i64 1 %gep2 = getelementptr i32, i32* %p2, i64 1
%load2 = load i32, i32* %gep2 ; <- load could be eliminated %load2 = load i32, i32* %gep2 ; <- load could be eliminated
%add = add i32 %load1, %load2 %add = add i32 %load1, %load2
ret i32 %add ret i32 %add
} }
define i32 @load_clobber_load_gep2(<vscale x 4 x i32>* %p) { define i32 @load_clobber_load_gep2(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @load_clobber_load_gep2( ; CHECK-LABEL: @load_clobber_load_gep2(
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 0 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 0
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]] ; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to i32* ; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to i32*
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i32, i32* [[P2]], i64 4 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i32, i32* [[P2]], i64 4
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[GEP2]] ; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[GEP2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret i32 [[ADD]] ; CHECK-NEXT: ret i32 [[ADD]]
; ;
%gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0 %gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0
%load1 = load i32, i32* %gep1 %load1 = load i32, i32* %gep1
%p2 = bitcast <vscale x 4 x i32>* %p to i32* %p2 = bitcast <vscale x 4 x i32>* %p to i32*
%gep2 = getelementptr i32, i32* %p2, i64 4 %gep2 = getelementptr i32, i32* %p2, i64 4
%load2 = load i32, i32* %gep2 ; <- can not determine at compile-time if %load1 and %load2 are same addr %load2 = load i32, i32* %gep2 ; <- can not determine at compile-time if %load1 and %load2 are same addr
%add = add i32 %load1, %load2 %add = add i32 %load1, %load2
ret i32 %add ret i32 %add
} }
; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as MustAlias. ; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as MustAlias.
define i32 @load_clobber_load_gep3(<vscale x 4 x i32>* %p) { define i32 @load_clobber_load_gep3(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @load_clobber_load_gep3( ; CHECK-LABEL: @load_clobber_load_gep3(
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 0 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 0
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]] ; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP1]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to <vscale x 4 x float>* ; CHECK-NEXT: [[P2:%.*]] = bitcast <vscale x 4 x i32>* [[P]] to <vscale x 4 x float>*
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* [[P2]], i64 1, i64 0 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* [[P2]], i64 1, i64 0
; CHECK-NEXT: [[LOAD2:%.*]] = load float, float* [[GEP2]] ; CHECK-NEXT: [[LOAD2:%.*]] = load float, float* [[GEP2]], align 4
; CHECK-NEXT: [[CAST:%.*]] = bitcast float [[LOAD2]] to i32 ; CHECK-NEXT: [[CAST:%.*]] = bitcast float [[LOAD2]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[CAST]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[CAST]]
; CHECK-NEXT: ret i32 [[ADD]] ; CHECK-NEXT: ret i32 [[ADD]]
; ;
%gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0 %gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0
%load1 = load i32, i32* %gep1 %load1 = load i32, i32* %gep1
%p2 = bitcast <vscale x 4 x i32>* %p to <vscale x 4 x float>* %p2 = bitcast <vscale x 4 x i32>* %p to <vscale x 4 x float>*
%gep2 = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %p2, i64 1, i64 0 %gep2 = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %p2, i64 1, i64 0
%load2 = load float, float* %gep2 ; <- load could be eliminated %load2 = load float, float* %gep2 ; <- load could be eliminated
%cast = bitcast float %load2 to i32 %cast = bitcast float %load2 to i32
%add = add i32 %load1, %cast %add = add i32 %load1, %cast
ret i32 %add ret i32 %add
} }
define <vscale x 4 x i32> @load_clobber_load_fence(<vscale x 4 x i32>* %p) { define <vscale x 4 x i32> @load_clobber_load_fence(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @load_clobber_load_fence( ; CHECK-LABEL: @load_clobber_load_fence(
; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: call void asm "", "~{memory}"() ; CHECK-NEXT: call void asm "", "~{memory}"()
; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]] ; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], align 16
; CHECK-NEXT: [[SUB:%.*]] = sub <vscale x 4 x i32> [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[SUB:%.*]] = sub <vscale x 4 x i32> [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[SUB]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[SUB]]
; ;
%load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
call void asm "", "~{memory}"() call void asm "", "~{memory}"()
%load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
%sub = sub <vscale x 4 x i32> %load1, %load2 %sub = sub <vscale x 4 x i32> %load1, %load2
ret <vscale x 4 x i32> %sub ret <vscale x 4 x i32> %sub
} }
define <vscale x 4 x i32> @load_clobber_load_sideeffect(<vscale x 4 x i32>* %p) { define <vscale x 4 x i32> @load_clobber_load_sideeffect(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @load_clobber_load_sideeffect( ; CHECK-LABEL: @load_clobber_load_sideeffect(
; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: [[LOAD1:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: call void asm sideeffect "", ""() ; CHECK-NEXT: call void asm sideeffect "", ""()
; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]] ; CHECK-NEXT: [[LOAD2:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], align 16
; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]]
; ;
%load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load1 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
%load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
%add = add <vscale x 4 x i32> %load1, %load2 %add = add <vscale x 4 x i32> %load1, %load2
ret <vscale x 4 x i32> %add ret <vscale x 4 x i32> %add
} }
; Analyze Load from clobbering Store. ; Analyze Load from clobbering Store.
define <vscale x 4 x i32> @store_forward_to_load(<vscale x 4 x i32>* %p) { define <vscale x 4 x i32> @store_forward_to_load(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @store_forward_to_load( ; CHECK-LABEL: @store_forward_to_load(
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: ret <vscale x 4 x i32> zeroinitializer ; CHECK-NEXT: ret <vscale x 4 x i32> zeroinitializer
; ;
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p
%load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
ret <vscale x 4 x i32> %load ret <vscale x 4 x i32> %load
} }
define <vscale x 4 x i32> @store_forward_to_load_sideeffect(<vscale x 4 x i32>* %p) { define <vscale x 4 x i32> @store_forward_to_load_sideeffect(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @store_forward_to_load_sideeffect( ; CHECK-LABEL: @store_forward_to_load_sideeffect(
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: call void asm sideeffect "", ""() ; CHECK-NEXT: call void asm sideeffect "", ""()
; CHECK-NEXT: [[LOAD:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]] ; CHECK-NEXT: [[LOAD:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], align 16
; CHECK-NEXT: ret <vscale x 4 x i32> [[LOAD]] ; CHECK-NEXT: ret <vscale x 4 x i32> [[LOAD]]
; ;
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p
call void asm sideeffect "", ""() call void asm sideeffect "", ""()
%load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p %load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %p
ret <vscale x 4 x i32> %load ret <vscale x 4 x i32> %load
} }
define i32 @store_clobber_load() { define i32 @store_clobber_load() {
; CHECK-LABEL: @store_clobber_load( ; CHECK-LABEL: @store_clobber_load(
; CHECK-NEXT: [[ALLOC:%.*]] = alloca <vscale x 4 x i32> ; CHECK-NEXT: [[ALLOC:%.*]] = alloca <vscale x 4 x i32>
; CHECK-NEXT: store <vscale x 4 x i32> undef, <vscale x 4 x i32>* [[ALLOC]] ; CHECK-NEXT: store <vscale x 4 x i32> undef, <vscale x 4 x i32>* [[ALLOC]], align 16
; CHECK-NEXT: [[PTR:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[ALLOC]], i32 0, i32 1 ; CHECK-NEXT: [[PTR:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[ALLOC]], i32 0, i32 1
; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[PTR]] ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[PTR]], align 4
; CHECK-NEXT: ret i32 [[LOAD]] ; CHECK-NEXT: ret i32 [[LOAD]]
; ;
%alloc = alloca <vscale x 4 x i32> %alloc = alloca <vscale x 4 x i32>
store <vscale x 4 x i32> undef, <vscale x 4 x i32>* %alloc store <vscale x 4 x i32> undef, <vscale x 4 x i32>* %alloc
%ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %alloc, i32 0, i32 1 %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %alloc, i32 0, i32 1
%load = load i32, i32* %ptr %load = load i32, i32* %ptr
ret i32 %load ret i32 %load
} }
Show All 15 Lines;
ret i32 %load ret i32 %load
} }
define i32 @memset_clobber_load_vscaled_base(<vscale x 4 x i32> *%p) { define i32 @memset_clobber_load_vscaled_base(<vscale x 4 x i32> *%p) {
; CHECK-LABEL: @memset_clobber_load_vscaled_base( ; CHECK-LABEL: @memset_clobber_load_vscaled_base(
; CHECK-NEXT: [[CONV:%.*]] = bitcast <vscale x 4 x i32>* [[P:%.*]] to i8* ; CHECK-NEXT: [[CONV:%.*]] = bitcast <vscale x 4 x i32>* [[P:%.*]] to i8*
; CHECK-NEXT: tail call void @llvm.memset.p0i8.i64(i8* [[CONV]], i8 1, i64 200, i1 false) ; CHECK-NEXT: tail call void @llvm.memset.p0i8.i64(i8* [[CONV]], i8 1, i64 200, i1 false)
; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1, i64 1 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1, i64 1
; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[GEP]] ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[GEP]], align 4
; CHECK-NEXT: ret i32 [[LOAD]] ; CHECK-NEXT: ret i32 [[LOAD]]
; ;
%conv = bitcast <vscale x 4 x i32>* %p to i8* %conv = bitcast <vscale x 4 x i32>* %p to i8*
tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i1 false)
%gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 1 %gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 1
%load = load i32, i32* %gep %load = load i32, i32* %gep
ret i32 %load ret i32 %load
} }
define i32 @memset_clobber_load_nonconst_index(<vscale x 4 x i32> *%p, i64 %idx1, i64 %idx2) { define i32 @memset_clobber_load_nonconst_index(<vscale x 4 x i32> *%p, i64 %idx1, i64 %idx2) {
; CHECK-LABEL: @memset_clobber_load_nonconst_index( ; CHECK-LABEL: @memset_clobber_load_nonconst_index(
; CHECK-NEXT: [[CONV:%.*]] = bitcast <vscale x 4 x i32>* [[P:%.*]] to i8* ; CHECK-NEXT: [[CONV:%.*]] = bitcast <vscale x 4 x i32>* [[P:%.*]] to i8*
; CHECK-NEXT: tail call void @llvm.memset.p0i8.i64(i8* [[CONV]], i8 1, i64 200, i1 false) ; CHECK-NEXT: tail call void @llvm.memset.p0i8.i64(i8* [[CONV]], i8 1, i64 200, i1 false)
; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 [[IDX1:%.*]], i64 [[IDX2:%.*]] ; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 [[IDX1:%.*]], i64 [[IDX2:%.*]]
; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[GEP]] ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[GEP]], align 4
; CHECK-NEXT: ret i32 [[LOAD]] ; CHECK-NEXT: ret i32 [[LOAD]]
; ;
%conv = bitcast <vscale x 4 x i32>* %p to i8* %conv = bitcast <vscale x 4 x i32>* %p to i8*
tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i1 false)
%gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 %idx1, i64 %idx2 %gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 %idx1, i64 %idx2
%load = load i32, i32* %gep %load = load i32, i32* %gep
ret i32 %load ret i32 %load
} }
; Load elimination across BBs ; Load elimination across BBs
define <vscale x 4 x i32>* @load_from_alloc_replaced_with_undef() { define <vscale x 4 x i32>* @load_from_alloc_replaced_with_undef() {
; CHECK-LABEL: @load_from_alloc_replaced_with_undef( ; CHECK-LABEL: @load_from_alloc_replaced_with_undef(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca <vscale x 4 x i32> ; CHECK-NEXT: [[A:%.*]] = alloca <vscale x 4 x i32>
; CHECK-NEXT: br i1 undef, label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; CHECK-NEXT: br i1 undef, label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[A]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[A]], align 16
; CHECK-NEXT: br label [[IF_END]] ; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end: ; CHECK: if.end:
; CHECK-NEXT: ret <vscale x 4 x i32>* [[A]] ; CHECK-NEXT: ret <vscale x 4 x i32>* [[A]]
; ;
entry: entry:
%a = alloca <vscale x 4 x i32> %a = alloca <vscale x 4 x i32>
%gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 0, i64 1 %gep = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 0, i64 1
%load = load i32, i32* %gep ; <- load to be eliminated %load = load i32, i32* %gep ; <- load to be eliminated
%tobool = icmp eq i32 %load, 0 ; <- icmp to be eliminated %tobool = icmp eq i32 %load, 0 ; <- icmp to be eliminated
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
if.then: if.then:
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %a store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %a
br label %if.end br label %if.end
if.end: if.end:
ret <vscale x 4 x i32>* %a ret <vscale x 4 x i32>* %a
} }
define i32 @redundant_load_elimination_1(<vscale x 4 x i32>* %p) { define i32 @redundant_load_elimination_1(<vscale x 4 x i32>* %p) {
; CHECK-LABEL: @redundant_load_elimination_1( ; CHECK-LABEL: @redundant_load_elimination_1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 1 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 1
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP]] ; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[LOAD1]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[LOAD1]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: br label [[IF_END]] ; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end: ; CHECK: if.end:
; CHECK-NEXT: ret i32 [[LOAD1]] ; CHECK-NEXT: ret i32 [[LOAD1]]
; ;
entry: entry:
Show All 12 Linesif.end:
ret i32 %result ret i32 %result
} }
; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as NoAlias. ; TODO: BasicAA return MayAlias for %gep1,%gep2, could improve as NoAlias.
define void @redundant_load_elimination_2(i1 %c, <vscale x 4 x i32>* %p, i32* %q, <vscale x 4 x i32> %v) { define void @redundant_load_elimination_2(i1 %c, <vscale x 4 x i32>* %p, i32* %q, <vscale x 4 x i32> %v) {
; CHECK-LABEL: @redundant_load_elimination_2( ; CHECK-LABEL: @redundant_load_elimination_2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 1 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P:%.*]], i64 1, i64 1
; CHECK-NEXT: store i32 0, i32* [[GEP1]] ; CHECK-NEXT: store i32 0, i32* [[GEP1]], align 4
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1, i64 0 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1, i64 0
; CHECK-NEXT: store i32 1, i32* [[GEP2]] ; CHECK-NEXT: store i32 1, i32* [[GEP2]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: [[T:%.*]] = load i32, i32* [[GEP1]] ; CHECK-NEXT: [[T:%.*]] = load i32, i32* [[GEP1]], align 4
; CHECK-NEXT: store i32 [[T]], i32* [[Q:%.*]] ; CHECK-NEXT: store i32 [[T]], i32* [[Q:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: if.else: ; CHECK: if.else:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 1 %gep1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 1
store i32 0, i32* %gep1 store i32 0, i32* %gep1
%gep2 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0 %gep2 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1, i64 0
store i32 1, i32* %gep2 store i32 1, i32* %gep2
br i1 %c, label %if.else, label %if.then br i1 %c, label %if.else, label %if.then
if.then: if.then:
%t = load i32, i32* %gep1 ; <- load could be eliminated %t = load i32, i32* %gep1 ; <- load could be eliminated
store i32 %t, i32* %q store i32 %t, i32* %q
ret void ret void
if.else: if.else:
ret void ret void
} }
; TODO: load in if.then could have been eliminated ; TODO: load in if.then could have been eliminated
define void @missing_load_elimination(i1 %c, <vscale x 4 x i32>* %p, <vscale x 4 x i32>* %q, <vscale x 4 x i32> %v) { define void @missing_load_elimination(i1 %c, <vscale x 4 x i32>* %p, <vscale x 4 x i32>* %q, <vscale x 4 x i32> %v) {
; CHECK-LABEL: @missing_load_elimination( ; CHECK-LABEL: @missing_load_elimination(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* [[P:%.*]], align 16
; CHECK-NEXT: [[P1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1 ; CHECK-NEXT: [[P1:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], i64 1
; CHECK-NEXT: store <vscale x 4 x i32> [[V:%.*]], <vscale x 4 x i32>* [[P1]] ; CHECK-NEXT: store <vscale x 4 x i32> [[V:%.*]], <vscale x 4 x i32>* [[P1]], align 16
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: [[T:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]] ; CHECK-NEXT: [[T:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* [[P]], align 16
; CHECK-NEXT: store <vscale x 4 x i32> [[T]], <vscale x 4 x i32>* [[Q:%.*]] ; CHECK-NEXT: store <vscale x 4 x i32> [[T]], <vscale x 4 x i32>* [[Q:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: if.else: ; CHECK: if.else:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p store <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32>* %p
%p1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1 %p1 = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %p, i64 1
store <vscale x 4 x i32> %v, <vscale x 4 x i32>* %p1 store <vscale x 4 x i32> %v, <vscale x 4 x i32>* %p1
Show All 10 Lines

llvm/test/Transforms/InstCombine/store.ll

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define i32 @test3(i1 %C) { define i32 @test3(i1 %C) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[COND2:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[COND2:%.*]]
; CHECK: Cond: ; CHECK: Cond:
; CHECK-NEXT: br label [[CONT:%.*]] ; CHECK-NEXT: br label [[CONT:%.*]]
; CHECK: Cond2: ; CHECK: Cond2:
; CHECK-NEXT: br label [[CONT]] ; CHECK-NEXT: br label [[CONT]]
; CHECK: Cont: ; CHECK: Cont:
; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[COND2]] ] ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 47, [[COND2]] ], [ -987654321, [[COND]] ]
; CHECK-NEXT: ret i32 [[STOREMERGE]] ; CHECK-NEXT: ret i32 [[STOREMERGE]]
; ;
%A = alloca i32 %A = alloca i32
br i1 %C, label %Cond, label %Cond2 br i1 %C, label %Cond, label %Cond2
Cond: Cond:
store i32 -987654321, i32* %A store i32 -987654321, i32* %A
br label %Cont br label %Cont
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llvm/test/Transforms/InstCombine/storemerge-dbg.ll

Show All 11 Lineslhs:
store i32 1, i32* %baz store i32 1, i32* %baz
br label %cleanup br label %cleanup
rhs: rhs:
store i32 2, i32* %baz store i32 2, i32* %baz
br label %cleanup br label %cleanup
cleanup: cleanup:
; CHECK: %storemerge = phi i32 [ 1, %lhs ], [ 2, %rhs ], !dbg [[merge_loc:![0-9]+]] ; CHECK: %storemerge = phi i32 [ 2, %rhs ], [ 1, %lhs ], !dbg [[merge_loc:![0-9]+]]
%baz.val = load i32, i32* %baz %baz.val = load i32, i32* %baz
%ret.val = call i32 @escape(i32 %baz.val) %ret.val = call i32 @escape(i32 %baz.val)
ret i32 %ret.val ret i32 %ret.val
} }
; CHECK: [[merge_loc]] = !DILocation(line: 0 ; CHECK: [[merge_loc]] = !DILocation(line: 0

llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll

Show First 20 Lines • Show All 583 Lines • ▼ Show 20 Lines;
ret void ret void
} }
define void @store_address_space(<4 x i32> addrspace(1)* %ptr, <2 x i32> %v0, <2 x i32> %v1) { define void @store_address_space(<4 x i32> addrspace(1)* %ptr, <2 x i32> %v0, <2 x i32> %v1) {
; CHECK-NEON-LABEL: @store_address_space( ; CHECK-NEON-LABEL: @store_address_space(
; CHECK-NEON-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> <i32 0, i32 1> ; CHECK-NEON-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> <i32 0, i32 1>
; CHECK-NEON-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> <i32 2, i32 3> ; CHECK-NEON-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[V0]], <2 x i32> [[V1]], <2 x i32> <i32 2, i32 3>
; CHECK-NEON-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)* ; CHECK-NEON-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
; CHECK-NEON-NEXT: call void @llvm.arm.neon.vst2.p1i8.v2i32(i8 addrspace(1)* [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], i32 0) ; CHECK-NEON-NEXT: call void @llvm.arm.neon.vst2.p1i8.v2i32(i8 addrspace(1)* [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], i32 8)
; CHECK-NEON-NEXT: ret void ; CHECK-NEON-NEXT: ret void
; ;
; CHECK-MVE-LABEL: @store_address_space( ; CHECK-MVE-LABEL: @store_address_space(
; CHECK-MVE-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-MVE-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-MVE-NEXT: store <4 x i32> [[INTERLEAVED_VEC]], <4 x i32> addrspace(1)* [[PTR:%.*]] ; CHECK-MVE-NEXT: store <4 x i32> [[INTERLEAVED_VEC]], <4 x i32> addrspace(1)* [[PTR:%.*]], align 8
; CHECK-MVE-NEXT: ret void ; CHECK-MVE-NEXT: ret void
; ;
; CHECK-NONE-LABEL: @store_address_space( ; CHECK-NONE-LABEL: @store_address_space(
; CHECK-NONE-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-NONE-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NONE-NEXT: store <4 x i32> [[INTERLEAVED_VEC]], <4 x i32> addrspace(1)* [[PTR:%.*]] ; CHECK-NONE-NEXT: store <4 x i32> [[INTERLEAVED_VEC]], <4 x i32> addrspace(1)* [[PTR:%.*]], align 8
; CHECK-NONE-NEXT: ret void ; CHECK-NONE-NEXT: ret void
; ;
%interleaved.vec = shufflevector <2 x i32> %v0, <2 x i32> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %interleaved.vec = shufflevector <2 x i32> %v0, <2 x i32> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
store <4 x i32> %interleaved.vec, <4 x i32> addrspace(1)* %ptr store <4 x i32> %interleaved.vec, <4 x i32> addrspace(1)* %ptr
ret void ret void
} }
define void @load_f16_factor2(<8 x half>* %ptr) { define void @load_f16_factor2(<8 x half>* %ptr) {
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llvm/test/Transforms/LoopIdiom/X86/unordered-atomic-memcpy.ll

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for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
;; memcpy.atomic formation rejection (normal store w/ no align, atomic load) ;; memcpy.atomic formation rejection (normal store w/ no align, atomic load)
define void @test3b(i64 %Size) nounwind ssp { define void @test3b(i64 %Size) nounwind ssp {
; CHECK-LABEL: @test3b( ; CHECK-LABEL: @test3b(
; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1)
; CHECK: store ; CHECK-NOT: store
; CHECK: ret void ; CHECK: ret void
bb.nph: bb.nph:
%Base = alloca i8, i32 10000 %Base = alloca i8, i32 10000
%Dest = alloca i8, i32 10000 %Dest = alloca i8, i32 10000
br label %for.body br label %for.body
for.body: ; preds = %bb.nph, %for.body for.body: ; preds = %bb.nph, %for.body
%indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ] %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
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llvm/test/Transforms/LoopUnroll/complete_unroll_profitability_with_assume.ll

Show All 16 Lines
define i32 @foo(i32* %a) { define i32 @foo(i32* %a) {
; ANALYZE-FULL-LABEL: @foo( ; ANALYZE-FULL-LABEL: @foo(
; ANALYZE-FULL-NEXT: entry: ; ANALYZE-FULL-NEXT: entry:
; ANALYZE-FULL-NEXT: br label [[FOR_BODY:%.*]] ; ANALYZE-FULL-NEXT: br label [[FOR_BODY:%.*]]
; ANALYZE-FULL: for.body: ; ANALYZE-FULL: for.body:
; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE:%.*]], label [[FOR_NEXT:%.*]] ; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE:%.*]], label [[FOR_NEXT:%.*]]
; ANALYZE-FULL: do_store: ; ANALYZE-FULL: do_store:
; ANALYZE-FULL-NEXT: store i32 0, i32* [[A:%.*]] ; ANALYZE-FULL-NEXT: store i32 0, i32* [[A:%.*]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT]]
; ANALYZE-FULL: for.next: ; ANALYZE-FULL: for.next:
; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_1:%.*]], label [[FOR_NEXT_1:%.*]] ; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_1:%.*]], label [[FOR_NEXT_1:%.*]]
; ANALYZE-FULL: do_store.1: ; ANALYZE-FULL: do_store.1:
; ANALYZE-FULL-NEXT: [[GEP_1:%.*]] = getelementptr i32, i32* [[A]], i32 1 ; ANALYZE-FULL-NEXT: [[GEP_1:%.*]] = getelementptr i32, i32* [[A]], i32 1
; ANALYZE-FULL-NEXT: store i32 1, i32* [[GEP_1]] ; ANALYZE-FULL-NEXT: store i32 1, i32* [[GEP_1]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_1]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_1]]
; ANALYZE-FULL: for.next.1: ; ANALYZE-FULL: for.next.1:
; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_2:%.*]], label [[FOR_NEXT_2:%.*]] ; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_2:%.*]], label [[FOR_NEXT_2:%.*]]
; ANALYZE-FULL: do_store.2: ; ANALYZE-FULL: do_store.2:
; ANALYZE-FULL-NEXT: [[GEP_2:%.*]] = getelementptr i32, i32* [[A]], i32 2 ; ANALYZE-FULL-NEXT: [[GEP_2:%.*]] = getelementptr i32, i32* [[A]], i32 2
; ANALYZE-FULL-NEXT: store i32 2, i32* [[GEP_2]] ; ANALYZE-FULL-NEXT: store i32 2, i32* [[GEP_2]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_2]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_2]]
; ANALYZE-FULL: for.next.2: ; ANALYZE-FULL: for.next.2:
; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_3:%.*]], label [[FOR_NEXT_3:%.*]] ; ANALYZE-FULL-NEXT: br i1 true, label [[DO_STORE_3:%.*]], label [[FOR_NEXT_3:%.*]]
; ANALYZE-FULL: do_store.3: ; ANALYZE-FULL: do_store.3:
; ANALYZE-FULL-NEXT: [[GEP_3:%.*]] = getelementptr i32, i32* [[A]], i32 3 ; ANALYZE-FULL-NEXT: [[GEP_3:%.*]] = getelementptr i32, i32* [[A]], i32 3
; ANALYZE-FULL-NEXT: store i32 3, i32* [[GEP_3]] ; ANALYZE-FULL-NEXT: store i32 3, i32* [[GEP_3]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_3]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_3]]
; ANALYZE-FULL: for.next.3: ; ANALYZE-FULL: for.next.3:
; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_4:%.*]], label [[FOR_NEXT_4:%.*]] ; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_4:%.*]], label [[FOR_NEXT_4:%.*]]
; ANALYZE-FULL: do_store.4: ; ANALYZE-FULL: do_store.4:
; ANALYZE-FULL-NEXT: [[GEP_4:%.*]] = getelementptr i32, i32* [[A]], i32 4 ; ANALYZE-FULL-NEXT: [[GEP_4:%.*]] = getelementptr i32, i32* [[A]], i32 4
; ANALYZE-FULL-NEXT: store i32 4, i32* [[GEP_4]] ; ANALYZE-FULL-NEXT: store i32 4, i32* [[GEP_4]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_4]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_4]]
; ANALYZE-FULL: for.next.4: ; ANALYZE-FULL: for.next.4:
; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_5:%.*]], label [[FOR_NEXT_5:%.*]] ; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_5:%.*]], label [[FOR_NEXT_5:%.*]]
; ANALYZE-FULL: do_store.5: ; ANALYZE-FULL: do_store.5:
; ANALYZE-FULL-NEXT: [[GEP_5:%.*]] = getelementptr i32, i32* [[A]], i32 5 ; ANALYZE-FULL-NEXT: [[GEP_5:%.*]] = getelementptr i32, i32* [[A]], i32 5
; ANALYZE-FULL-NEXT: store i32 5, i32* [[GEP_5]] ; ANALYZE-FULL-NEXT: store i32 5, i32* [[GEP_5]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_5]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_5]]
; ANALYZE-FULL: for.next.5: ; ANALYZE-FULL: for.next.5:
; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_6:%.*]], label [[FOR_NEXT_6:%.*]] ; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_6:%.*]], label [[FOR_NEXT_6:%.*]]
; ANALYZE-FULL: do_store.6: ; ANALYZE-FULL: do_store.6:
; ANALYZE-FULL-NEXT: [[GEP_6:%.*]] = getelementptr i32, i32* [[A]], i32 6 ; ANALYZE-FULL-NEXT: [[GEP_6:%.*]] = getelementptr i32, i32* [[A]], i32 6
; ANALYZE-FULL-NEXT: store i32 6, i32* [[GEP_6]] ; ANALYZE-FULL-NEXT: store i32 6, i32* [[GEP_6]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_6]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_6]]
; ANALYZE-FULL: for.next.6: ; ANALYZE-FULL: for.next.6:
; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_7:%.*]], label [[FOR_NEXT_7:%.*]] ; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_7:%.*]], label [[FOR_NEXT_7:%.*]]
; ANALYZE-FULL: do_store.7: ; ANALYZE-FULL: do_store.7:
; ANALYZE-FULL-NEXT: [[GEP_7:%.*]] = getelementptr i32, i32* [[A]], i32 7 ; ANALYZE-FULL-NEXT: [[GEP_7:%.*]] = getelementptr i32, i32* [[A]], i32 7
; ANALYZE-FULL-NEXT: store i32 7, i32* [[GEP_7]] ; ANALYZE-FULL-NEXT: store i32 7, i32* [[GEP_7]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_7]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_7]]
; ANALYZE-FULL: for.next.7: ; ANALYZE-FULL: for.next.7:
; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_8:%.*]], label [[FOR_NEXT_8:%.*]] ; ANALYZE-FULL-NEXT: br i1 false, label [[DO_STORE_8:%.*]], label [[FOR_NEXT_8:%.*]]
; ANALYZE-FULL: do_store.8: ; ANALYZE-FULL: do_store.8:
; ANALYZE-FULL-NEXT: [[GEP_8:%.*]] = getelementptr i32, i32* [[A]], i32 8 ; ANALYZE-FULL-NEXT: [[GEP_8:%.*]] = getelementptr i32, i32* [[A]], i32 8
; ANALYZE-FULL-NEXT: store i32 8, i32* [[GEP_8]] ; ANALYZE-FULL-NEXT: store i32 8, i32* [[GEP_8]], align 4
; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_8]] ; ANALYZE-FULL-NEXT: br label [[FOR_NEXT_8]]
; ANALYZE-FULL: for.next.8: ; ANALYZE-FULL: for.next.8:
; ANALYZE-FULL-NEXT: ret i32 9 ; ANALYZE-FULL-NEXT: ret i32 9
; ;
; DONT-ANALYZE-FULL-LABEL: @foo( ; DONT-ANALYZE-FULL-LABEL: @foo(
; DONT-ANALYZE-FULL-NEXT: entry: ; DONT-ANALYZE-FULL-NEXT: entry:
; DONT-ANALYZE-FULL-NEXT: br label [[FOR_BODY:%.*]] ; DONT-ANALYZE-FULL-NEXT: br label [[FOR_BODY:%.*]]
; DONT-ANALYZE-FULL: for.body: ; DONT-ANALYZE-FULL: for.body:
; DONT-ANALYZE-FULL-NEXT: [[INDVAR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_NEXT:%.*]] ] ; DONT-ANALYZE-FULL-NEXT: [[INDVAR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_NEXT:%.*]] ]
; DONT-ANALYZE-FULL-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1 ; DONT-ANALYZE-FULL-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
; DONT-ANALYZE-FULL-NEXT: [[CMP:%.*]] = icmp ule i32 [[INDVAR]], 20 ; DONT-ANALYZE-FULL-NEXT: [[CMP:%.*]] = icmp ule i32 [[INDVAR]], 20
; DONT-ANALYZE-FULL-NEXT: tail call void @llvm.assume(i1 [[CMP]]) ; DONT-ANALYZE-FULL-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; DONT-ANALYZE-FULL-NEXT: [[CMP2:%.*]] = icmp ule i32 [[INDVAR]], 3 ; DONT-ANALYZE-FULL-NEXT: [[CMP2:%.*]] = icmp ule i32 [[INDVAR]], 3
; DONT-ANALYZE-FULL-NEXT: br i1 [[CMP2]], label [[DO_STORE:%.*]], label [[FOR_NEXT]] ; DONT-ANALYZE-FULL-NEXT: br i1 [[CMP2]], label [[DO_STORE:%.*]], label [[FOR_NEXT]]
; DONT-ANALYZE-FULL: do_store: ; DONT-ANALYZE-FULL: do_store:
; DONT-ANALYZE-FULL-NEXT: [[GEP:%.*]] = getelementptr i32, i32* [[A:%.*]], i32 [[INDVAR]] ; DONT-ANALYZE-FULL-NEXT: [[GEP:%.*]] = getelementptr i32, i32* [[A:%.*]], i32 [[INDVAR]]
; DONT-ANALYZE-FULL-NEXT: store i32 [[INDVAR]], i32* [[GEP]] ; DONT-ANALYZE-FULL-NEXT: store i32 [[INDVAR]], i32* [[GEP]], align 4
; DONT-ANALYZE-FULL-NEXT: br label [[FOR_NEXT]] ; DONT-ANALYZE-FULL-NEXT: br label [[FOR_NEXT]]
; DONT-ANALYZE-FULL: for.next: ; DONT-ANALYZE-FULL: for.next:
; DONT-ANALYZE-FULL-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INDVAR_NEXT]], 9 ; DONT-ANALYZE-FULL-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INDVAR_NEXT]], 9
; DONT-ANALYZE-FULL-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[LOOPEXIT:%.*]] ; DONT-ANALYZE-FULL-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[LOOPEXIT:%.*]]
; DONT-ANALYZE-FULL: loopexit: ; DONT-ANALYZE-FULL: loopexit:
; DONT-ANALYZE-FULL-NEXT: [[INDVAR_NEXT_LCSSA:%.*]] = phi i32 [ [[INDVAR_NEXT]], [[FOR_NEXT]] ] ; DONT-ANALYZE-FULL-NEXT: [[INDVAR_NEXT_LCSSA:%.*]] = phi i32 [ [[INDVAR_NEXT]], [[FOR_NEXT]] ]
; DONT-ANALYZE-FULL-NEXT: ret i32 [[INDVAR_NEXT_LCSSA]] ; DONT-ANALYZE-FULL-NEXT: ret i32 [[INDVAR_NEXT_LCSSA]]
; ;
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llvm/test/Transforms/NewGVN/pr31594.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bb: ; CHECK-NEXT: bb:
; CHECK-NEXT: br label [[BB1:%.*]] ; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: [[TMP:%.*]] = phi i8* [ [[ARG:%.*]], [[BB:%.*]] ], [ null, [[BB2:%.*]] ] ; CHECK-NEXT: [[TMP:%.*]] = phi i8* [ [[ARG:%.*]], [[BB:%.*]] ], [ null, [[BB2:%.*]] ]
; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB2]] ; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB2]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: br label [[BB1]] ; CHECK-NEXT: br label [[BB1]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: store i8 0, i8* [[TMP]], !g !0 ; CHECK-NEXT: store i8 0, i8* [[TMP]], align 1, !g !0
; CHECK-NEXT: br label [[BB4:%.*]] ; CHECK-NEXT: br label [[BB4:%.*]]
; CHECK: bb4: ; CHECK: bb4:
; CHECK-NEXT: br label [[BB6:%.*]] ; CHECK-NEXT: br label [[BB6:%.*]]
; CHECK: bb6: ; CHECK: bb6:
; CHECK-NEXT: br i1 undef, label [[BB9:%.*]], label [[BB7:%.*]] ; CHECK-NEXT: br i1 undef, label [[BB9:%.*]], label [[BB7:%.*]]
; CHECK: bb7: ; CHECK: bb7:
; CHECK-NEXT: switch i8 0, label [[BB6]] [ ; CHECK-NEXT: switch i8 0, label [[BB6]] [
; CHECK-NEXT: i8 6, label [[BB8:%.*]] ; CHECK-NEXT: i8 6, label [[BB8:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: bb8: ; CHECK: bb8:
; CHECK-NEXT: store i8 undef, i8* null ; CHECK-NEXT: store i8 undef, i8* null, align 1
; CHECK-NEXT: br label [[BB4]] ; CHECK-NEXT: br label [[BB4]]
; CHECK: bb9: ; CHECK: bb9:
; CHECK-NEXT: store i8 0, i8* [[ARG]], !g !0 ; CHECK-NEXT: store i8 0, i8* [[ARG]], align 1, !g !0
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; ;
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb2, %bb bb1: ; preds = %bb2, %bb
%tmp = phi i8* [ %arg, %bb ], [ null, %bb2 ] %tmp = phi i8* [ %arg, %bb ], [ null, %bb2 ]
br i1 undef, label %bb3, label %bb2 br i1 undef, label %bb3, label %bb2
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llvm/test/Transforms/NewGVN/pr31613.ll

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%struct.a = type {} %struct.a = type {}
%struct.b = type {} %struct.b = type {}
declare void @c.d.p(i64, i8*) declare void @c.d.p(i64, i8*)
define void @e(i32 %a0, i32 %a1, %struct.a** %p2) { define void @e(i32 %a0, i32 %a1, %struct.a** %p2) {
; CHECK-LABEL: @e( ; CHECK-LABEL: @e(
; CHECK-NEXT: [[F:%.*]] = alloca i32 ; CHECK-NEXT: [[F:%.*]] = alloca i32
; CHECK-NEXT: store i32 [[A0:%.*]], i32* [[F]], !g !0 ; CHECK-NEXT: store i32 [[A0:%.*]], i32* [[F]], align 4, !g !0
; CHECK-NEXT: br label [[H:%.*]] ; CHECK-NEXT: br label [[H:%.*]]
; CHECK: h: ; CHECK: h:
; CHECK-NEXT: call void @c.d.p(i64 8, i8* undef) ; CHECK-NEXT: call void @c.d.p(i64 8, i8* undef)
; CHECK-NEXT: [[I:%.*]] = load i32, i32* [[F]] ; CHECK-NEXT: [[I:%.*]] = load i32, i32* [[F]], align 4
; CHECK-NEXT: [[J:%.*]] = load i32, i32* null ; CHECK-NEXT: [[J:%.*]] = load i32, i32* null, align 4
; CHECK-NEXT: [[K:%.*]] = icmp eq i32 [[I]], [[J]] ; CHECK-NEXT: [[K:%.*]] = icmp eq i32 [[I]], [[J]]
; CHECK-NEXT: br i1 [[K]], label [[L:%.*]], label [[Q:%.*]] ; CHECK-NEXT: br i1 [[K]], label [[L:%.*]], label [[Q:%.*]]
; CHECK: l: ; CHECK: l:
; CHECK-NEXT: br label [[R:%.*]] ; CHECK-NEXT: br label [[R:%.*]]
; CHECK: q: ; CHECK: q:
; CHECK-NEXT: [[M:%.*]] = load %struct.a*, %struct.a** null ; CHECK-NEXT: [[M:%.*]] = load %struct.a*, %struct.a** null, align 8
; CHECK-NEXT: br label [[R]] ; CHECK-NEXT: br label [[R]]
; CHECK: r: ; CHECK: r:
; CHECK-NEXT: switch i32 undef, label [[N:%.*]] [ ; CHECK-NEXT: switch i32 undef, label [[N:%.*]] [
; CHECK-NEXT: i32 0, label [[S:%.*]] ; CHECK-NEXT: i32 0, label [[S:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: s: ; CHECK: s:
; CHECK-NEXT: store i32 [[A1:%.*]], i32* [[F]], !g !0 ; CHECK-NEXT: store i32 [[A1:%.*]], i32* [[F]], align 4, !g !0
; CHECK-NEXT: br label [[H]] ; CHECK-NEXT: br label [[H]]
; CHECK: n: ; CHECK: n:
; CHECK-NEXT: [[O:%.*]] = load %struct.a*, %struct.a** [[P2:%.*]] ; CHECK-NEXT: [[O:%.*]] = load %struct.a*, %struct.a** [[P2:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%f = alloca i32 %f = alloca i32
store i32 %a0, i32* %f, !g !0 store i32 %a0, i32* %f, !g !0
br label %h br label %h
h: ; preds = %s, %0 h: ; preds = %s, %0
call void @c.d.p(i64 8, i8* undef) call void @c.d.p(i64 8, i8* undef)
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llvm/test/Transforms/NewGVN/pr33204.ll

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; CHECK-NEXT: br label [[BB2]] ; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[ARG:%.*]], [[BB:%.*]] ] ; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[ARG:%.*]], [[BB:%.*]] ]
; CHECK-NEXT: br label [[BB6:%.*]] ; CHECK-NEXT: br label [[BB6:%.*]]
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !h !0 ; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !h !0
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: bb6: ; CHECK: bb6:
; CHECK-NEXT: store i32 [[TMP]], i32* @global.1, !h !0 ; CHECK-NEXT: store i32 [[TMP]], i32* @global.1, align 4, !h !0
; CHECK-NEXT: br i1 undef, label [[BB7:%.*]], label [[BB1]] ; CHECK-NEXT: br i1 undef, label [[BB7:%.*]], label [[BB1]]
; CHECK: bb7: ; CHECK: bb7:
; CHECK-NEXT: br i1 undef, label [[BB10:%.*]], label [[BB8:%.*]] ; CHECK-NEXT: br i1 undef, label [[BB10:%.*]], label [[BB8:%.*]]
; CHECK: bb8: ; CHECK: bb8:
; CHECK-NEXT: br i1 false, label [[BB9:%.*]], label [[BB3:%.*]] ; CHECK-NEXT: br i1 false, label [[BB9:%.*]], label [[BB3:%.*]]
; CHECK: bb9: ; CHECK: bb9:
; CHECK-NEXT: store i8 undef, i8* null ; CHECK-NEXT: store i8 undef, i8* null, align 1
; CHECK-NEXT: br label [[BB3]] ; CHECK-NEXT: br label [[BB3]]
; CHECK: bb10: ; CHECK: bb10:
; CHECK-NEXT: store i32 0, i32* @global, !h !0 ; CHECK-NEXT: store i32 0, i32* @global, align 4, !h !0
; CHECK-NEXT: br label [[BB7]] ; CHECK-NEXT: br label [[BB7]]
; ;
bb: bb:
br label %bb2 br label %bb2
bb1: ; preds = %bb6 bb1: ; preds = %bb6
br label %bb2 br label %bb2
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llvm/test/Transforms/NewGVN/pr33720.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -newgvn -S %s | FileCheck %s ; RUN: opt -newgvn -S %s | FileCheck %s
@f = external local_unnamed_addr global i64 @f = external local_unnamed_addr global i64
@b = external local_unnamed_addr global i64 @b = external local_unnamed_addr global i64
@e = external local_unnamed_addr global i64 @e = external local_unnamed_addr global i64
define void @patatino() { define void @patatino() {
; CHECK-LABEL: @patatino( ; CHECK-LABEL: @patatino(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 undef, label [[IF_END24:%.*]], label [[FOR_COND16:%.*]] ; CHECK-NEXT: br i1 undef, label [[IF_END24:%.*]], label [[FOR_COND16:%.*]]
; CHECK: for.cond2thread-pre-split: ; CHECK: for.cond2thread-pre-split:
; CHECK-NEXT: br i1 false, label [[FOR_BODY:%.*]], label [[FOR_COND8_PREHEADER:%.*]] ; CHECK-NEXT: br i1 false, label [[FOR_BODY:%.*]], label [[FOR_COND8_PREHEADER:%.*]]
; CHECK: for.cond8.preheader: ; CHECK: for.cond8.preheader:
; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label %for.cond11thread-pre-split.lr.ph ; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[FOR_COND11THREAD_PRE_SPLIT_LR_PH:%.*]]
; CHECK: for.cond11thread-pre-split.lr.ph: ; CHECK: for.cond11thread-pre-split.lr.ph:
; CHECK-NEXT: br label [[L1]] ; CHECK-NEXT: br label [[L1]]
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i64 [[K_2:%.*]], 3 ; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i64 [[K_2:%.*]], 3
; CHECK-NEXT: [[CONV4:%.*]] = zext i1 [[CMP3]] to i64 ; CHECK-NEXT: [[CONV4:%.*]] = zext i1 [[CMP3]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @f ; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @f, align 4
; CHECK-NEXT: [[OR:%.*]] = or i64 [[TMP0]], [[CONV4]] ; CHECK-NEXT: [[OR:%.*]] = or i64 [[TMP0]], [[CONV4]]
; CHECK-NEXT: store i64 [[OR]], i64* @f ; CHECK-NEXT: store i64 [[OR]], i64* @f, align 4
; CHECK-NEXT: [[TOBOOL7:%.*]] = icmp ne i64 [[K_2]], 0 ; CHECK-NEXT: [[TOBOOL7:%.*]] = icmp ne i64 [[K_2]], 0
; CHECK-NEXT: br i1 [[TOBOOL7]], label %for.cond2thread-pre-split, label [[LOR_RHS:%.*]] ; CHECK-NEXT: br i1 [[TOBOOL7]], label [[FOR_COND2THREAD_PRE_SPLIT:%.*]], label [[LOR_RHS:%.*]]
; CHECK: lor.rhs: ; CHECK: lor.rhs:
; CHECK-NEXT: store i64 1, i64* @b, align 8 ; CHECK-NEXT: store i64 1, i64* @b, align 8
; CHECK-NEXT: br label %for.cond2thread-pre-split ; CHECK-NEXT: br label [[FOR_COND2THREAD_PRE_SPLIT]]
; CHECK: l1: ; CHECK: l1:
; CHECK-NEXT: [[K_2]] = phi i64 [ undef, [[L1_PREHEADER:%.*]] ], [ 15, [[FOR_COND8_PREHEADER]] ], [ 5, %for.cond11thread-pre-split.lr.ph ] ; CHECK-NEXT: [[K_2]] = phi i64 [ undef, [[L1_PREHEADER:%.*]] ], [ 15, [[FOR_COND8_PREHEADER]] ], [ 5, [[FOR_COND11THREAD_PRE_SPLIT_LR_PH]] ]
; CHECK-NEXT: store i64 7, i64* [[J_3:%.*]] ; CHECK-NEXT: store i64 7, i64* [[J_3:%.*]], align 4
; CHECK-NEXT: br label [[FOR_BODY]] ; CHECK-NEXT: br label [[FOR_BODY]]
; CHECK: for.cond16: ; CHECK: for.cond16:
; CHECK-NEXT: [[J_0:%.*]] = phi i64* [ @f, [[ENTRY:%.*]] ], [ undef, [[FOR_COND20:%.*]] ], [ @e, [[FOR_COND16]] ] ; CHECK-NEXT: [[J_0:%.*]] = phi i64* [ @f, [[ENTRY:%.*]] ], [ undef, [[FOR_COND20:%.*]] ], [ @e, [[FOR_COND16]] ]
; CHECK-NEXT: br i1 undef, label [[FOR_COND20]], label [[FOR_COND16]] ; CHECK-NEXT: br i1 undef, label [[FOR_COND20]], label [[FOR_COND16]]
; CHECK: for.cond20: ; CHECK: for.cond20:
; CHECK-NEXT: [[J_2:%.*]] = phi i64* [ [[J_0]], [[FOR_COND16]] ], [ undef, [[IF_END24]] ] ; CHECK-NEXT: [[J_2:%.*]] = phi i64* [ [[J_0]], [[FOR_COND16]] ], [ undef, [[IF_END24]] ]
; CHECK-NEXT: br i1 true, label [[IF_END24]], label [[FOR_COND16]] ; CHECK-NEXT: br i1 true, label [[IF_END24]], label [[FOR_COND16]]
; CHECK: if.end24: ; CHECK: if.end24:
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llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: call void @unknown() ; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: store float [[L0]], float* [[B:%.*]] ; CHECK-NEXT: store float [[L0]], float* [[B:%.*]], align 4
; CHECK-NEXT: [[B1:%.*]] = getelementptr inbounds float, float* [[B]], i64 1 ; CHECK-NEXT: [[B1:%.*]] = getelementptr inbounds float, float* [[B]], i64 1
; CHECK-NEXT: store float [[L1]], float* [[B1]] ; CHECK-NEXT: store float [[L1]], float* [[B1]], align 4
; CHECK-NEXT: [[B2:%.*]] = getelementptr inbounds float, float* [[B]], i64 2 ; CHECK-NEXT: [[B2:%.*]] = getelementptr inbounds float, float* [[B]], i64 2
; CHECK-NEXT: store float [[L2]], float* [[B2]] ; CHECK-NEXT: store float [[L2]], float* [[B2]], align 4
; CHECK-NEXT: [[B3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3 ; CHECK-NEXT: [[B3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3
; CHECK-NEXT: store float [[L3]], float* [[B3]] ; CHECK-NEXT: store float [[L3]], float* [[B3]], align 4
; CHECK-NEXT: [[C1:%.*]] = getelementptr inbounds float, float* [[C:%.*]], i64 1 ; CHECK-NEXT: [[C1:%.*]] = getelementptr inbounds float, float* [[C:%.*]], i64 1
; CHECK-NEXT: [[C2:%.*]] = getelementptr inbounds float, float* [[C]], i64 2 ; CHECK-NEXT: [[C2:%.*]] = getelementptr inbounds float, float* [[C]], i64 2
; CHECK-NEXT: [[C3:%.*]] = getelementptr inbounds float, float* [[C]], i64 3 ; CHECK-NEXT: [[C3:%.*]] = getelementptr inbounds float, float* [[C]], i64 3
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[C]] to <4 x float>* ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[C]] to <4 x float>*
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
; CHECK-NEXT: [[D1:%.*]] = getelementptr inbounds float, float* [[D:%.*]], i64 1 ; CHECK-NEXT: [[D1:%.*]] = getelementptr inbounds float, float* [[D:%.*]], i64 1
; CHECK-NEXT: [[D2:%.*]] = getelementptr inbounds float, float* [[D]], i64 2 ; CHECK-NEXT: [[D2:%.*]] = getelementptr inbounds float, float* [[D]], i64 2
; CHECK-NEXT: [[D3:%.*]] = getelementptr inbounds float, float* [[D]], i64 3 ; CHECK-NEXT: [[D3:%.*]] = getelementptr inbounds float, float* [[D]], i64 3
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llvm/test/Transforms/Util/assume-builder.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; BASIC-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8 ; BASIC-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8
; BASIC-NEXT: [[TMP5:%.*]] = alloca i32*, align 8 ; BASIC-NEXT: [[TMP5:%.*]] = alloca i32*, align 8
; BASIC-NEXT: [[TMP6:%.*]] = alloca i8*, align 8 ; BASIC-NEXT: [[TMP6:%.*]] = alloca i8*, align 8
; BASIC-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; BASIC-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ]
; BASIC-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8 ; BASIC-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; BASIC-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8 ; BASIC-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; BASIC-NEXT: store i8* [[TMP2]], i8** [[TMP6]] ; BASIC-NEXT: store i8* [[TMP2]], i8** [[TMP6]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; BASIC-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8 ; BASIC-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ]
; BASIC-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 ; BASIC-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
; BASIC-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8 ; BASIC-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; BASIC-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8 ; BASIC-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8
; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ] ; BASIC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ]
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; ALL-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8 ; ALL-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8
; ALL-NEXT: [[TMP5:%.*]] = alloca i32*, align 8 ; ALL-NEXT: [[TMP5:%.*]] = alloca i32*, align 8
; ALL-NEXT: [[TMP6:%.*]] = alloca i8*, align 8 ; ALL-NEXT: [[TMP6:%.*]] = alloca i8*, align 8
; ALL-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; ALL-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ]
; ALL-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8 ; ALL-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; ALL-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8 ; ALL-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; ALL-NEXT: store i8* [[TMP2]], i8** [[TMP6]] ; ALL-NEXT: store i8* [[TMP2]], i8** [[TMP6]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; ALL-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8 ; ALL-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ]
; ALL-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 ; ALL-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
; ALL-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8 ; ALL-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; ALL-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8 ; ALL-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8
; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ] ; ALL-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ]
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; WITH-AC-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8 ; WITH-AC-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8
; WITH-AC-NEXT: [[TMP5:%.*]] = alloca i32*, align 8 ; WITH-AC-NEXT: [[TMP5:%.*]] = alloca i32*, align 8
; WITH-AC-NEXT: [[TMP6:%.*]] = alloca i8*, align 8 ; WITH-AC-NEXT: [[TMP6:%.*]] = alloca i8*, align 8
; WITH-AC-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; WITH-AC-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ] ; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ]
; WITH-AC-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8 ; WITH-AC-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; WITH-AC-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8 ; WITH-AC-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]) ] ; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; WITH-AC-NEXT: store i8* [[TMP2]], i8** [[TMP6]] ; WITH-AC-NEXT: store i8* [[TMP2]], i8** [[TMP6]], align 8
; WITH-AC-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8 ; WITH-AC-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ] ; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ]
; WITH-AC-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 ; WITH-AC-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
; WITH-AC-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8 ; WITH-AC-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "align"(i8** [[TMP6]], i64 8) ]
; WITH-AC-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8 ; WITH-AC-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8
; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ] ; WITH-AC-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ]
; WITH-AC-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1 ; WITH-AC-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1
; WITH-AC-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; WITH-AC-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; WITH-AC-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; WITH-AC-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; WITH-AC-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8* ; WITH-AC-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8*
; WITH-AC-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; WITH-AC-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; WITH-AC-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; WITH-AC-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
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; CROSS-BLOCK-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8 ; CROSS-BLOCK-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8
; CROSS-BLOCK-NEXT: [[TMP5:%.*]] = alloca i32*, align 8 ; CROSS-BLOCK-NEXT: [[TMP5:%.*]] = alloca i32*, align 8
; CROSS-BLOCK-NEXT: [[TMP6:%.*]] = alloca i8*, align 8 ; CROSS-BLOCK-NEXT: [[TMP6:%.*]] = alloca i8*, align 8
; CROSS-BLOCK-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; CROSS-BLOCK-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ] ; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8) ]
; CROSS-BLOCK-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8 ; CROSS-BLOCK-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ] ; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8) ]
; CROSS-BLOCK-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8 ; CROSS-BLOCK-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]) ] ; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8) ]
; CROSS-BLOCK-NEXT: store i8* [[TMP2]], i8** [[TMP6]] ; CROSS-BLOCK-NEXT: store i8* [[TMP2]], i8** [[TMP6]], align 8
; CROSS-BLOCK-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8 ; CROSS-BLOCK-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ] ; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4) ]
; CROSS-BLOCK-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 ; CROSS-BLOCK-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
; CROSS-BLOCK-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8 ; CROSS-BLOCK-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8** [[TMP6]], i64 8) ]
; CROSS-BLOCK-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8 ; CROSS-BLOCK-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8
; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ] ; CROSS-BLOCK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]) ]
; CROSS-BLOCK-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1 ; CROSS-BLOCK-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1
; CROSS-BLOCK-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; CROSS-BLOCK-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; CROSS-BLOCK-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; CROSS-BLOCK-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; CROSS-BLOCK-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8* ; CROSS-BLOCK-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8*
; CROSS-BLOCK-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; CROSS-BLOCK-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; CROSS-BLOCK-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; CROSS-BLOCK-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
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; FULL-SIMPLIFY-LABEL: define {{[^@]+}}@test2 ; FULL-SIMPLIFY-LABEL: define {{[^@]+}}@test2
; FULL-SIMPLIFY-SAME: (%struct.S* [[TMP0:%.*]], i32* [[TMP1:%.*]], i8* [[TMP2:%.*]]) ; FULL-SIMPLIFY-SAME: (%struct.S* [[TMP0:%.*]], i32* [[TMP1:%.*]], i8* [[TMP2:%.*]])
; FULL-SIMPLIFY-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8 ; FULL-SIMPLIFY-NEXT: [[TMP4:%.*]] = alloca %struct.S*, align 8
; FULL-SIMPLIFY-NEXT: [[TMP5:%.*]] = alloca i32*, align 8 ; FULL-SIMPLIFY-NEXT: [[TMP5:%.*]] = alloca i32*, align 8
; FULL-SIMPLIFY-NEXT: [[TMP6:%.*]] = alloca i8*, align 8 ; FULL-SIMPLIFY-NEXT: [[TMP6:%.*]] = alloca i8*, align 8
; FULL-SIMPLIFY-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_S:%.*]], align 8
; FULL-SIMPLIFY-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8 ; FULL-SIMPLIFY-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP4]], align 8
; FULL-SIMPLIFY-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8 ; FULL-SIMPLIFY-NEXT: store i32* [[TMP1]], i32** [[TMP5]], align 8
; FULL-SIMPLIFY-NEXT: store i8* [[TMP2]], i8** [[TMP6]] ; FULL-SIMPLIFY-NEXT: store i8* [[TMP2]], i8** [[TMP6]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP5]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 ; FULL-SIMPLIFY-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
; FULL-SIMPLIFY-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8 ; FULL-SIMPLIFY-NEXT: [[TMP10:%.*]] = trunc i32 [[TMP9]] to i8
; FULL-SIMPLIFY-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP6]], align 8
; FULL-SIMPLIFY-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1 ; FULL-SIMPLIFY-NEXT: store i8 [[TMP10]], i8* [[TMP11]], align 1
; FULL-SIMPLIFY-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; FULL-SIMPLIFY-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; FULL-SIMPLIFY-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8* ; FULL-SIMPLIFY-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[TMP13]] to i8*
; FULL-SIMPLIFY-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8* ; FULL-SIMPLIFY-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP7]] to i8*
; FULL-SIMPLIFY-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP16]], i32 0, i32 0 ; FULL-SIMPLIFY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP16]], i32 0, i32 0
; FULL-SIMPLIFY-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP19:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP19:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 1 ; FULL-SIMPLIFY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 1
; FULL-SIMPLIFY-NEXT: [[TMP21:%.*]] = load i8, i8* [[TMP20]], align 4 ; FULL-SIMPLIFY-NEXT: [[TMP21:%.*]] = load i8, i8* [[TMP20]], align 4
; FULL-SIMPLIFY-NEXT: [[TMP22:%.*]] = sext i8 [[TMP21]] to i32 ; FULL-SIMPLIFY-NEXT: [[TMP22:%.*]] = sext i8 [[TMP21]] to i32
; FULL-SIMPLIFY-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP18]], [[TMP22]] ; FULL-SIMPLIFY-NEXT: [[TMP23:%.*]] = add nsw i32 [[TMP18]], [[TMP22]]
; FULL-SIMPLIFY-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[TMP4]], align 8
; FULL-SIMPLIFY-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP24]], i32 0, i32 2 ; FULL-SIMPLIFY-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP24]], i32 0, i32 2
; FULL-SIMPLIFY-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP25]], align 8 ; FULL-SIMPLIFY-NEXT: [[TMP26:%.*]] = load i32*, i32** [[TMP25]], align 8
; FULL-SIMPLIFY-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8), "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8), "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4), "align"(i8** [[TMP6]], i64 8), "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]), "dereferenceable"(i32* [[TMP17]], i64 4), "nonnull"(i32* [[TMP17]]), "align"(i32* [[TMP17]], i64 8), "dereferenceable"(i8* [[TMP20]], i64 1), "nonnull"(i8* [[TMP20]]), "align"(i8* [[TMP20]], i64 4), "dereferenceable"(i32** [[TMP25]], i64 8), "nonnull"(i32** [[TMP25]]), "align"(i32** [[TMP25]], i64 8), "dereferenceable"(i32* [[TMP26]], i64 4), "nonnull"(i32* [[TMP26]]), "align"(i32* [[TMP26]], i64 4) ] ; FULL-SIMPLIFY-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(%struct.S** [[TMP4]], i64 8), "nonnull"(%struct.S** [[TMP4]]), "align"(%struct.S** [[TMP4]], i64 8), "dereferenceable"(i32** [[TMP5]], i64 8), "nonnull"(i32** [[TMP5]]), "align"(i32** [[TMP5]], i64 8), "dereferenceable"(i8** [[TMP6]], i64 8), "nonnull"(i8** [[TMP6]]), "align"(i8** [[TMP6]], i64 8), "dereferenceable"(i32* [[TMP8]], i64 4), "nonnull"(i32* [[TMP8]]), "align"(i32* [[TMP8]], i64 4), "dereferenceable"(i8* [[TMP11]], i64 1), "nonnull"(i8* [[TMP11]]), "dereferenceable"(i32* [[TMP17]], i64 4), "nonnull"(i32* [[TMP17]]), "align"(i32* [[TMP17]], i64 8), "dereferenceable"(i8* [[TMP20]], i64 1), "nonnull"(i8* [[TMP20]]), "align"(i8* [[TMP20]], i64 4), "dereferenceable"(i32** [[TMP25]], i64 8), "nonnull"(i32** [[TMP25]]), "align"(i32** [[TMP25]], i64 8), "dereferenceable"(i32* [[TMP26]], i64 4), "nonnull"(i32* [[TMP26]]), "align"(i32* [[TMP26]], i64 4) ]
; FULL-SIMPLIFY-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 ; FULL-SIMPLIFY-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
; FULL-SIMPLIFY-NEXT: [[TMP28:%.*]] = add nsw i32 [[TMP23]], [[TMP27]] ; FULL-SIMPLIFY-NEXT: [[TMP28:%.*]] = add nsw i32 [[TMP23]], [[TMP27]]
; FULL-SIMPLIFY-NEXT: ret i32 [[TMP28]] ; FULL-SIMPLIFY-NEXT: ret i32 [[TMP28]]
; ;
%4 = alloca %struct.S*, align 8 %4 = alloca %struct.S*, align 8
%5 = alloca i32*, align 8 %5 = alloca i32*, align 8
%6 = alloca i8*, align 8 %6 = alloca i8*, align 8
%7 = alloca %struct.S, align 8 %7 = alloca %struct.S, align 8
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llvm/test/Verifier/tbaa.ll

; RUN: not llvm-as < %s 2>&1 | FileCheck %s ; RUN: not llvm-as < %s 2>&1 | FileCheck %s
; RUN: llvm-as -disable-verify < %s | opt -verify -S | FileCheck %s --check-prefix=STRIP ; RUN: llvm-as -disable-verify < %s | opt -verify -S | FileCheck %s --check-prefix=STRIP
; STRIP-NOT: tbaa ; STRIP-NOT: tbaa
; STRIP: @f_0 ; STRIP: @f_0
; STRIP: Do no strip this ; STRIP: Do no strip this
define void @f_0(i32* %ptr) { define void @f_0(i32* %ptr) {
; This part checks for the easy syntactic verifier rules. ; This part checks for the easy syntactic verifier rules.
; CHECK: Struct tag metadata must have either 3 or 4 operands ; CHECK: Struct tag metadata must have either 3 or 4 operands
; CHECK-NEXT: store i32 0, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 0, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Immutability tag on struct tag metadata must be a constant ; CHECK: Immutability tag on struct tag metadata must be a constant
; CHECK-NEXT: store i32 1, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 1, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Immutability part of the struct tag metadata must be either 0 or 1 ; CHECK: Immutability part of the struct tag metadata must be either 0 or 1
; CHECK-NEXT: store i32 2, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 2, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Offset must be constant integer ; CHECK: Offset must be constant integer
; CHECK-NEXT: store i32 3, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 3, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Malformed struct tag metadata: base and access-type should be non-null and point to Metadata nodes ; CHECK: Malformed struct tag metadata: base and access-type should be non-null and point to Metadata nodes
; CHECK-NEXT: store i32 4, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 4, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 5, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 5, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access bit-width not the same as description bit-width ; CHECK: Access bit-width not the same as description bit-width
; CHECK-NEXT: store i32 6, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 6, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 7, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 7, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Struct tag nodes have a string as their first operand ; CHECK: Struct tag nodes have a string as their first operand
; CHECK-NEXT: !{{[0-9]+}} = !{!{{[0-9]+}}, !{{[0-9]+}}, i64 0} ; CHECK-NEXT: !{{[0-9]+}} = !{!{{[0-9]+}}, !{{[0-9]+}}, i64 0}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 9, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 9, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
store i32 0, i32* %ptr, !tbaa !{!3, !2, i64 40, i64 0, i64 1, i64 2} store i32 0, i32* %ptr, !tbaa !{!3, !2, i64 40, i64 0, i64 1, i64 2}
store i32 1, i32* %ptr, !tbaa !{!3, !2, i64 40, !"immutable"} store i32 1, i32* %ptr, !tbaa !{!3, !2, i64 40, !"immutable"}
store i32 2, i32* %ptr, !tbaa !{!3, !2, i64 40, i64 4} store i32 2, i32* %ptr, !tbaa !{!3, !2, i64 40, i64 4}
store i32 3, i32* %ptr, !tbaa !{!3, !2, !"40", i64 0} store i32 3, i32* %ptr, !tbaa !{!3, !2, !"40", i64 0}
store i32 4, i32* %ptr, !tbaa !{!3, null, !"40", i64 0} store i32 4, i32* %ptr, !tbaa !{!3, null, !"40", i64 0}
store i32 5, i32* %ptr, !tbaa !{!3, !3, !"40", i64 0} store i32 5, i32* %ptr, !tbaa !{!3, !3, !"40", i64 0}
store i32 6, i32* %ptr, !tbaa !{!3, !2, i32 40, i64 0} store i32 6, i32* %ptr, !tbaa !{!3, !2, i32 40, i64 0}
store i32 7, i32* %ptr, !tbaa !{!3, !12, i32 40, i64 0}, !metadata !42 store i32 7, i32* %ptr, !tbaa !{!3, !12, i32 40, i64 0}, !metadata !42
store i32 8, i32* %ptr, !tbaa !{!13, !1, i64 0} store i32 8, i32* %ptr, !tbaa !{!13, !1, i64 0}
store i32 9, i32* %ptr, !tbaa !{!14, !14, i64 0} store i32 9, i32* %ptr, !tbaa !{!14, !14, i64 0}
ret void ret void
} }
!42 = !{!"Do no strip this!"} !42 = !{!"Do no strip this!"}
define void @f_1(i32* %ptr) { define void @f_1(i32* %ptr) {
; This part checks for more semantic verifier rules. ; This part checks for more semantic verifier rules.
; CHECK: Cycle detected in struct path ; CHECK: Cycle detected in struct path
; CHECK-NEXT: store i32 0, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 0, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Offset not zero at the point of scalar access ; CHECK: Offset not zero at the point of scalar access
; CHECK-NEXT: store i32 1, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 1, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Offset not zero at the point of scalar access ; CHECK: Offset not zero at the point of scalar access
; CHECK-NEXT: store i32 2, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 2, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Could not find TBAA parent in struct type node ; CHECK: Could not find TBAA parent in struct type node
; CHECK-NEXT: store i32 3, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 3, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Did not see access type in access path! ; CHECK: Did not see access type in access path!
; CHECK-NEXT: store i32 3, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 3, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 4, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 4, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 5, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 5, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Access type node must be a valid scalar type ; CHECK: Access type node must be a valid scalar type
; CHECK-NEXT: store i32 6, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 6, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Struct tag nodes must have an odd number of operands! ; CHECK: Struct tag nodes must have an odd number of operands!
; CHECK-NEXT:!{{[0-9]+}} = !{!"bad-struct-type-0", !{{[0-9]+}}, i64 40, !{{[0-9]+}}} ; CHECK-NEXT:!{{[0-9]+}} = !{!"bad-struct-type-0", !{{[0-9]+}}, i64 40, !{{[0-9]+}}}
; CHECK: Incorrect field entry in struct type node! ; CHECK: Incorrect field entry in struct type node!
; CHECK-NEXT: store i32 8, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 8, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Bitwidth between the offsets and struct type entries must match ; CHECK: Bitwidth between the offsets and struct type entries must match
; CHECK-NEXT: store i32 9, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 9, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
; CHECK: Offsets must be increasing! ; CHECK: Offsets must be increasing!
; CHECK-NEXT: store i32 10, i32* %ptr, !tbaa !{{[0-9]+}} ; CHECK-NEXT: store i32 10, i32* %ptr, align 4, !tbaa !{{[0-9]+}}
store i32 0, i32* %ptr, !tbaa !{!4, !2, i64 40} store i32 0, i32* %ptr, !tbaa !{!4, !2, i64 40}
store i32 1, i32* %ptr, !tbaa !{!3, !2, i64 45} store i32 1, i32* %ptr, !tbaa !{!3, !2, i64 45}
store i32 2, i32* %ptr, !tbaa !{!3, !2, i64 45} store i32 2, i32* %ptr, !tbaa !{!3, !2, i64 45}
store i32 3, i32* %ptr, !tbaa !{!3, !2, i64 10} store i32 3, i32* %ptr, !tbaa !{!3, !2, i64 10}
store i32 4, i32* %ptr, !tbaa !{!5, !5, i64 0} store i32 4, i32* %ptr, !tbaa !{!5, !5, i64 0}
store i32 5, i32* %ptr, !tbaa !{!6, !6, i64 0} store i32 5, i32* %ptr, !tbaa !{!6, !6, i64 0}
store i32 6, i32* %ptr, !tbaa !{!7, !7, i64 0} store i32 6, i32* %ptr, !tbaa !{!7, !7, i64 0}
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