Add ptrace register access for AArch64 SVE registers

[omjavaid]

Summary

This patch adds NativeRegisterContext_arm64 ptrace routines to access AArch64 SVE registers. This patch also adds a test-case to test AArch64 SVE registers dynamic configuration and read/write.

This patch is part from previously submitted AArch64 SVE register access support.

[omjavaid]

This new updated patch overrides GetRegisterInfoAtIndex in NativeRegisterContextLinux_arm64 to reduce the impacts of register numbering conversion on the generic LLGS code.

[omjavaid]

This update remove skipping over register infos requirement by overlapping sve register numbers with debug register numbers which are not required by Linux register context.

[omjavaid]

This update remove dependence over generic interfaces by calling ConfigureRegisterContext on every call to ReadRegister/WriteRegister.

[omjavaid]

This update incorporates suggestion from last iteration and also rebases after merger of register sets and register infos in RegisterInfosPOSIX_arm64.
Also I have posted a separate patch D83541 to make lldb/source/Plugins/Process/Linux/LinuxPTraceDefines_arm64sve.h platform independent in order to use them with elf-core.

@labath what do you think ?

[omjavaid]

This update makes changes to avoid dependence on lldb-arm64-register-enums.h. Also provides rebased version after update of parent patches.

[omjavaid]

Updated and re-based after changes in core file patch

[omjavaid]

This revision updates SVE ptrace support to reflect changes we made in SVE core file support specially around handling of FPSR and FPCR.

[labath]

I haven't looked at all the sve details, but they seem very similar to the core file stuff, so I think they should be fine. I have some other comments though...

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

240

What's the relationship of this function and the InvalidateAllRegisters function we added (for arm64 benefit) a couple of reviews back? Can we just have one of them?

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

At this point, that header is sufficiently different from the asm/ptrace.h implementation (names of all structs and fields are different) that I don't think it makes sense to use it as an optional replacement. It makes it very likely things will not build in one of the modes.

This should either use the system version (and then only build when the system has the appropriate headers), or we should use the in-house version unconditionally (which may require renaming/namespacing the rest of the file so that it does not conflict with the real asm/ptrace.h).

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

22

It would be better to have this actually detect the availability of the feature. A skip-always test is not very convincing.

IIRC, some of the tests for fancy x86 registers have the inferior detect the availability of the feature (via the cpuid instruction or something), and then exit with a predefined exit code. Then the test can check for that and skip itself if the feature is not available. Would something like that work here?

75

you don't need to set this twice

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

2–4

In our newer register tests we use the pattern where the debugger sets the register values, which are then read back through the inferior (and vice versa). I thing this is a good thing as it avoids the possibility of making symmetrical bugs in the read/write code, which will then appear to modify the register successfully, but they won't actually change the value observed by the inferior process.

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

240

Both InvalidateAllRegisters and ConfigureRegisterContext are inter related.

The idea is to maintain a cache of SVE register configurations created after thread stop on first call to ReadRegister/WriteRegister, using ConfigureRegisterContext. This configuration cache is maintained unless we do register write or we issue a step or resume.

InvalidateAllRegisters is called before resume and it will invalidate all cached register data including SVE configuration thus forcing us to do ConfigureRegisterContext on stop.

There is also a case where we need to reconfigure register context when we write vector granule register and need to update register sizes and offsets and sync them up between LLDB client and server. That case is handled by the child revisions of this patch.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

Ack.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

2–4

In this test we are also doing the same please have a look at TestSVERegisters.py:140-142.

The code in main.c is used to make sure we enable SVE mode. AArch64 SVE mode is enabled by Linux kernel on first execution of SVE code.

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

asm/ptrace.h also describes legacy structs for fpsimd access, hardware breakpoint structs and other related ptrace access. Newer versions of ptrace only append SVE specific structs and macros. In house LLDB's SVE macros file only include SVE specific register names. I dont see any conflict since I have also added a guard for multiple definitions in LinuxPTraceDefines_arm64sve.h as it protects against builds of AArch64/Linux where ThreadElfCore also includes sigcontext and ptrace.h for accessing elf-core related struct definitions.

[omjavaid]

This update fixes issues highlighted in last review iteration.

@labath any further action on this?

[labath]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

240

Right, it's that inter-relatedness that worries me. Back when we were talking about InvalidateAllRegisters we (I) decided that it was simpler to call it before a thread resumes. I'm wondering if that wasn't a mistake.

Like, if we called InvalidateAllRegisters when a thread stops, then you could use this opportunity to initialize the SVE configuration, right? And that would avoid the need to call ConfigureRegisterContext on every register read operation? Obviously there'd still need to be some reconfiguration/invalidation of the SVE context after some register writes, but that would be similar to us invalidating the GPR cache when the GPR registers get written.

Basically, it seems to me that would make things more homogeneous.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

I'm not saying we shouldn't include asm/ptrace.h at all. It obviously contains a lot of useful stuff, and we wouldn't want to duplicate all of that.

What I am saying is that for the stuff that we already have duplicated, we just be using that unconditionally. Doing otherwise just needlessly forks the build matrix and creates opportunities for things to not work in one mode or the other. We're already committed to ensuring things work with the in-house definitions so why bothering to ensure that things work both with them _and_ with the system ones.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

2–4

I have a feeling we're misunderstanding each other. I am talking about the tests in test/Shell/Register (e.g. x86-64-xmm16-read.test, x86-64-xmm16-write.test). This test definitely doesn't to that. The code in 140-142 is just reading back what was written by lines 135-137, not values set by the inferior.

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

240

Agreed. I can give that a shot that probably was the original idea behind InvalidateAllRegisters.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

Right now SVE in-house macros and the ones in asm/ptrace.h are identical. If we include asm/ptrace.h and it already has SVE macros we cannot avoid that inclusion so in case we want to force use of in-house macros we ll have to rename the in-house macros and headers with LLVM_ or LLDB_ prefix to make sure we avoid duplication. If you have strong opinion in favor of renaming i can go ahead and do that.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

2–4

The problem in case of SVE is that size of vector is unknown untill we run therefore we cannot hard write value that will be written and read back.
Also this API based test actually verifies that vector granule register value and Z/P register sizes make sense. It then prepares a value to be written to Z, P or FFr registers based on currently configured vector length and the read that same value back. I could not find a way to do that using shell based tests.

[omjavaid]

In this update I have moved ConfigureRegisterContext insider InvalidateAllRegisters in light of D84501 where we move InvalidateAllRegisters on every stop rather than doing so before step/resume

[labath]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

22

I do, actually. Given that this code is also used for the core files, which can be used from any host, and the fact that we have already started making changes to it because of that (_uNN vs uintNN_t, the msvc compatibility patch, etc), I think we just just treating this as a part of our codebase and not some asm/ptrace addon.

I wouldn't tack an additional LLDB_ onto the names though. What I'd do is replace all of these macros with regular C(++) symbols. Parameter-less macros can be constants and function-like macros can just be functions. They can keep the original all-caps spelling to make it clear where they are coming from, but in order to distinguish them from the system symbols we can make a tiny modification -- instead of naming everyting SVE_FOO, we name the thing just FOO, but put it inside a lldb_private::SVE namespace -- that way the symbols can be referred to as SVE::FOO.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

2–4

Right. While it would definitely be nice if this test was next to the other ones, rewriting this as a lit test is not what I was going for. I think these are sufficiently special to handle them this way.

What I was referring to is the general principle of setting the registers in the inferior (via asm or something) and then reading them from the test. That principle applies no matter which style is the test written in.

[omjavaid]

This patch fixes review items from last review cycles. Now we do not use LinuxPTraceDefines_arm64sve.h for NativeProcessLinux_arm64 as these defs are already back ported into libc ptrace.h available on most distros. LLDB arm64 build bot and release builders should already have the header included.

We have updated LinuxPTraceDefines_arm64sve.h in D85641 where macros are converted into c++ consts and inlines.

Also test case now include ASM writing of by all SVE registers and they are read back and verified by the test case. I have also retained the writing test that was already there previously.

[omjavaid]

@labath Any further action needed on this change? I have updated test main.c for doing asm write to SVE regs and then reading them back during testing. Also i have removed NativeProcessLinux_arm64 dependence on LinuxPTraceDefines_arm64sve.h. We are using sys root's ptrace.h as SVE marcros are back ported in most versions of ptrace.h.

[labath]

In D79699#2215216, @omjavaid wrote:

@labath Any further action needed on this change? I have updated test main.c for doing asm write to SVE regs and then reading them back during testing. Also i have removed NativeProcessLinux_arm64 dependence on LinuxPTraceDefines_arm64sve.h. We are using sys root's ptrace.h as SVE marcros are back ported in most versions of ptrace.h.

Almost. I have two more questions/requests inline.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

101–107

Are you sure this will work if the system does not support SVE? I would expect the test application to die from SIGILL (or something) long before we reach this part.

Even if it does work, it will mean that the test will be skipped (instead of failing) if the lldb-server stops reporting the sve registers (or even if it just slightly changes the register set name). That's why I was originally suggesting to check for SVE support from within the inferior process.

Is there a simple way to do that? I'm assuming there must be, otherwise the application could not detect whether it can use sve...

135

So, the program sets all p registers to the same value (0xffff..) right? Would it be possible to introduce some variance there (like you did for the z registers), to ensure that the registers are actually read from the right place?

[omjavaid]

This update adds check for SVE support using /proc/cpuinfo in SVE testcases. Also tests case to read predicate registers with 5 different values instead of 0xff.

@labath this seems reasonable now?

[labath]

Looks good, just the cpuinfo detection function could use a bit of improvement.

Thanks for your patience.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

23

This will put the file into the CWD, which is in the source tree. This should be self.getBuildArtifact(cpuinfo), and then you don't need the tear down hook.

Also, "platform get-file" (or SBPlatform::Get) should also work on local setups.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #if defined(__arm64__) || defined(__aarch64__)
 
 #ifndef lldb_NativeRegisterContextLinux_arm64_h
 #define lldb_NativeRegisterContextLinux_arm64_h
 
 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
 
+#include <asm/ptrace.h>
+
+// If asm/ptrace.h included above does not contain SVE PTrace macros
+#ifndef SVE_PT_REGS_SVE
+#define INCLUDE_LINUX_PTRACE_DEFINITIONS_FOR_SVE_ARM64
+#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
+#endif
+
 namespace lldb_private {
 namespace process_linux {
 
 class NativeProcessLinux;
 
 class NativeRegisterContextLinux_arm64 : public NativeRegisterContextLinux {
 public:
   NativeRegisterContextLinux_arm64(const ArchSpec &target_arch,
protected:
 
   void *GetFPRBuffer() override { return &m_fpr; }
 
   size_t GetFPRSize() override { return sizeof(m_fpr); }
 
 private:
   bool m_gpr_is_valid;
   bool m_fpu_is_valid;
+  bool m_sve_buffer_is_valid;
+
+  bool m_sve_header_is_valid;
 
   RegisterInfoPOSIX_arm64::GPR m_gpr_arm64; // 64-bit general purpose registers.
 
   RegisterInfoPOSIX_arm64::FPU
       m_fpr; // floating-point registers including extended register sets.
+
+  SVEState m_sve_state;
+  struct user_sve_header m_sve_header;
+  std::vector<uint8_t> m_sve_ptrace_payload;
+
   // Debug register info for hardware breakpoints and watchpoints management.
   struct DREG {
     lldb::addr_t address;  // Breakpoint/watchpoint address value.
     lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception
                            // occurred.
     lldb::addr_t real_addr; // Address value that should cause target to stop.
     uint32_t control;       // Breakpoint/watchpoint control value.
     uint32_t refcount;      // Serves as enable/disable and reference counter.
   };
 
   struct DREG m_hbr_regs[16]; // Arm native linux hardware breakpoints
   struct DREG m_hwp_regs[16]; // Arm native linux hardware watchpoints
 
   uint32_t m_max_hwp_supported;
   uint32_t m_max_hbp_supported;
   bool m_refresh_hwdebug_info;
 
   bool IsGPR(unsigned reg) const;
 
   bool IsFPR(unsigned reg) const;
 
+  Status ReadAllSVE();
+
+  Status WriteAllSVE();
+
+  Status ReadSVEHeader();
+
+  Status WriteSVEHeader();
+
+  bool IsSVE(unsigned reg) const;
+
+  uint64_t GetSVERegVG() { return m_sve_header.vl / 8; }
+
+  void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; }
+
+  void *GetSVEHeader() { return &m_sve_header; }
+
+  void *GetSVEBuffer();
+
+  size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
+
+  size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); }
+
   Status ReadHardwareDebugInfo();
 
   Status WriteHardwareDebugRegs(int hwbType);
 
   uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
 
   RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;
+
+  void ConfigureRegisterContext();
+
+  uint32_t CalculateSVEOffset(const RegisterInfo *reg_info) const;
 };
 
 } // namespace process_linux
 } // namespace lldb_private
 
 #endif // #ifndef lldb_NativeRegisterContextLinux_arm64_h
 
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 #include "lldb/Utility/DataBufferHeap.h"
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/RegisterValue.h"
 #include "lldb/Utility/Status.h"
 
 #include "Plugins/Process/Linux/NativeProcessLinux.h"
 #include "Plugins/Process/Linux/Procfs.h"
 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
 
 // System includes - They have to be included after framework includes because
 // they define some macros which collide with variable names in other modules
 #include <sys/socket.h>
 // NT_PRSTATUS and NT_FPREGSET definition
 #include <elf.h>
-// user_hwdebug_state definition
-#include <asm/ptrace.h>
+
+#ifndef NT_ARM_SVE
+#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension */
+#endif
 
 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
 
 using namespace lldb;
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
 std::unique_ptr<NativeRegisterContextLinux>

 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
     const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
     : NativeRegisterContextLinux(native_thread,
                                  new RegisterInfoPOSIX_arm64(target_arch)) {
   ::memset(&m_fpr, 0, sizeof(m_fpr));
   ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64));
   ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
   ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
+  ::memset(&m_sve_header, 0, sizeof(m_sve_header));
 
   // 16 is just a maximum value, query hardware for actual watchpoint count
   m_max_hwp_supported = 16;
   m_max_hbp_supported = 16;
+
   m_refresh_hwdebug_info = true;
 
   m_gpr_is_valid = false;
   m_fpu_is_valid = false;
+  m_sve_buffer_is_valid = false;
+  m_sve_header_is_valid = false;
+
+  // SVE is not enabled until we query user_sve_header
+  m_sve_state = SVEState::Unknown;
 }
 
 RegisterInfoPOSIX_arm64 &
 NativeRegisterContextLinux_arm64::GetRegisterInfo() const {
   return static_cast<RegisterInfoPOSIX_arm64 &>(*m_register_info_interface_up);
 }
 
 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const {
NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info,
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
 
   if (reg == LLDB_INVALID_REGNUM)
     return Status("no lldb regnum for %s", reg_info && reg_info->name
                                                ? reg_info->name
                                                : "<unknown register>");
 
+  // Update SVE registers in case there is change in configuration
+  ConfigureRegisterContext();
+
   uint8_t *src;
   uint32_t offset;
+  uint64_t sve_vg;
+  std::vector<uint8_t> sve_reg_non_live;
 
   if (IsGPR(reg)) {
-    if (!m_gpr_is_valid) {
-      error = ReadGPR();
-      if (error.Fail())
-        return error;
-    }
 
     offset = reg_info->byte_offset;
     assert(offset < GetGPRSize());
     src = (uint8_t *)GetGPRBuffer() + offset;
 
   } else if (IsFPR(reg)) {
-    if (!m_fpu_is_valid) {
-
+    if (m_sve_state == SVEState::Disabled) {
+      // SVE is disabled take legacy route for FPU register access
       error = ReadFPR();
       if (error.Fail())
         return error;
-    }
+
       offset = CalculateFprOffset(reg_info);
       assert(offset < GetFPRSize());
       src = (uint8_t *)GetFPRBuffer() + offset;
+    } else {
+      // SVE enabled, we will read and cache SVE ptrace data
+      error = ReadAllSVE();
+      if (error.Fail())
+        return error;
+
+      // FPSR and FPCR will be located right after Z registers in
+      // SVEState::FPSIMD while in SVEState::Full they will be located at the
+      // end of register data after an alignment correction based on currently
+      // selected vector length.
+      uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
+      if (reg == GetRegisterInfo().GetRegNumFPSR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16);
+      } else if (reg == GetRegisterInfo().GetRegNumFPCR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4;
+      } else {
+        // Extract SVE Z register value register number for this reg_info
+        if (reg_info->value_regs &&
+            reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
+          sve_reg_num = reg_info->value_regs[0];
+        offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
+      }
+
+      offset = CalculateSVEOffset(reg_info);
+      assert(offset < GetSVEBufferSize());
+      src = (uint8_t *)GetSVEBuffer() + offset;
+    }
+  } else if (IsSVE(reg)) {
+
+    if (m_sve_state == SVEState::Disabled || m_sve_state == SVEState::Unknown)
+      return Status("SVE disabled or not supported");
+
+    if (GetRegisterInfo().IsSVERegVG(reg)) {
+      sve_vg = GetSVERegVG();
+      src = (uint8_t *)&sve_vg;
+    } else {
+      // SVE enabled, we will read and cache SVE ptrace data
+      error = ReadAllSVE();
+      if (error.Fail())
+        return error;
+
+      if (m_sve_state == SVEState::FPSIMD) {
+        // In FPSIMD state SVE payload mirrors legacy fpsimd struct and so
+        // just copy 16 bytes of v register to the start of z register. All
+        // other SVE register will be set to zero.
+        sve_reg_non_live.resize(reg_info->byte_size, 0);
+        src = sve_reg_non_live.data();
+
+        if (GetRegisterInfo().IsSVEZReg(reg)) {
+          offset = CalculateSVEOffset(reg_info);
+          assert(offset < GetSVEBufferSize());
+          ::memcpy(sve_reg_non_live.data(), (uint8_t *)GetSVEBuffer() + offset,
+                   16);
+        }
+      } else {
+        offset = CalculateSVEOffset(reg_info);
+        assert(offset < GetSVEBufferSize());
+        src = (uint8_t *)GetSVEBuffer() + offset;
+      }
+    }
   } else
     return Status("failed - register wasn't recognized to be a GPR or an FPR, "
                   "write strategy unknown");
 
   reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
                               eByteOrderLittle, error);
 
   return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteRegister(
     const RegisterInfo *reg_info, const RegisterValue &reg_value) {
   Status error;
 
   if (!reg_info)
     return Status("reg_info NULL");
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
 
   if (reg == LLDB_INVALID_REGNUM)
     return Status("no lldb regnum for %s", reg_info && reg_info->name
                                                ? reg_info->name
                                                : "<unknown register>");
 
+  // Update SVE registers in case there is change in configuration.
+  ConfigureRegisterContext();
+
   uint8_t *dst;
   uint32_t offset;
+  std::vector<uint8_t> sve_reg_non_live;
 
   if (IsGPR(reg)) {
-    if (!m_gpr_is_valid) {
-      error = ReadGPR();
-      if (error.Fail())
-        return error;
-    }
-
-    offset = reg_info->byte_offset;
-    assert(offset < GetGPRSize());
-    dst = (uint8_t *)GetGPRBuffer() + offset;
 
+    assert(reg_info->byte_offset < GetGPRSize());
+    dst = (uint8_t *)GetGPRBuffer() + reg_info->byte_offset;
     ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
 
     return WriteGPR();
   } else if (IsFPR(reg)) {
-    if (!m_fpu_is_valid) {
+    if (m_sve_state == SVEState::Disabled) {
+      // SVE is disabled take legacy route for FPU register access
       error = ReadFPR();
       if (error.Fail())
         return error;
-    }
+
       offset = CalculateFprOffset(reg_info);
       assert(offset < GetFPRSize());
       dst = (uint8_t *)GetFPRBuffer() + offset;
-
       ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
 
       return WriteFPR();
+    } else {
+      // SVE enabled, we will read and cache SVE ptrace data
+      error = ReadAllSVE();
+      if (error.Fail())
+        return error;
+
+      // FPSR and FPCR will be located right after Z registers in
+      // SVEState::FPSIMD while in SVEState::Full they will be located at the
+      // end of register data after an alignment correction based on currently
+      // selected vector length.
+      uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
+      if (reg == GetRegisterInfo().GetRegNumFPSR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16);
+      } else if (reg == GetRegisterInfo().GetRegNumFPCR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_header.vl));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4;
+      } else {
+        // Extract SVE Z register value register number for this reg_info
+        if (reg_info->value_regs &&
+            reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
+          sve_reg_num = reg_info->value_regs[0];
+        offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
       }
 
+      offset = CalculateSVEOffset(reg_info);
+      assert(offset < GetSVEBufferSize());
+      dst = (uint8_t *)GetSVEBuffer() + offset;
+      ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+      return WriteAllSVE();
+    }
+  } else if (IsSVE(reg)) {
+    if (m_sve_state == SVEState::Disabled || m_sve_state == SVEState::Unknown)
+      return Status("SVE disabled or not supported");
+    else {
+      if (GetRegisterInfo().IsSVERegVG(reg))
+        return Status("SVE state change operation not supported");
+
+      // Target has SVE enabled, we will read and cache SVE ptrace data
+      error = ReadAllSVE();
+      if (error.Fail())
         return error;
+
+      // If target supports SVE but currently in FPSIMD mode.
+      if (m_sve_state == SVEState::FPSIMD) {
+        // Here we will check if writing this SVE register enables
+        // SVEState::Full
+        bool set_sve_state_full = false;
+        const uint8_t *reg_bytes = (const uint8_t *)reg_value.GetBytes();
+        if (GetRegisterInfo().IsSVEZReg(reg)) {
+          for (uint32_t i = 16; i < reg_info->byte_size; i++) {
+            if (reg_bytes[i]) {
+              set_sve_state_full = true;
+              break;
+            }
+          }
+        } else if (GetRegisterInfo().IsSVEPReg(reg) ||
+                   reg == GetRegisterInfo().GetRegNumSVEFFR()) {
+          for (uint32_t i = 0; i < reg_info->byte_size; i++) {
+            if (reg_bytes[i]) {
+              set_sve_state_full = true;
+              break;
+            }
+          }
+        }
+
+        if (!set_sve_state_full && GetRegisterInfo().IsSVEZReg(reg)) {
+          // We are writing a Z register which is zero beyond 16 bytes so copy
+          // first 16 bytes only as SVE payload mirrors legacy fpsimd structure
+          offset = CalculateSVEOffset(reg_info);
+          assert(offset < GetSVEBufferSize());
+          dst = (uint8_t *)GetSVEBuffer() + offset;
+          ::memcpy(dst, reg_value.GetBytes(), 16);
+
+          return WriteAllSVE();
+        } else
+          return Status("SVE state change operation not supported");
+      } else {
+        offset = CalculateSVEOffset(reg_info);
+        assert(offset < GetSVEBufferSize());
+        dst = (uint8_t *)GetSVEBuffer() + offset;
+        ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+        return WriteAllSVE();
+      }
+    }
+  }
+
+  return Status("Failed to write register value");
 }
 
 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {
   Status error;
 
   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
-  if (!m_gpr_is_valid) {
-    error = ReadGPR();
-    if (error.Fail())
-      return error;
-  }
+
 
-  if (!m_fpu_is_valid) {
-    error = ReadFPR();
-    if (error.Fail())
-      return error;
-  }
+
   uint8_t *dst = data_sp->GetBytes();
   ::memcpy(dst, GetGPRBuffer(), GetGPRSize());
   dst += GetGPRSize();
   ::memcpy(dst, GetFPRBuffer(), GetFPRSize());
 
   return error;
 }
 

 
 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const {
   if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
       RegisterInfoPOSIX_arm64::FPRegSet)
     return true;
   return false;
 }
 
+bool NativeRegisterContextLinux_arm64::IsSVE(unsigned reg) const {
+  if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+      RegisterInfoPOSIX_arm64::SVERegSet)
+    return true;
+  return false;
+}
+
 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() {
   Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS));
 
   LLDB_LOGF(log, "NativeRegisterContextLinux_arm64::%s()", __FUNCTION__);
 
   Status error;
 
   // Read hardware breakpoint and watchpoint information.
Status NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) {
 
   return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(),
                                            &hwbType, &ioVec, ioVec.iov_len);
 }
 
 Status NativeRegisterContextLinux_arm64::ReadGPR() {
   Status error;
 
-  struct iovec ioVec;
+  if (m_gpr_is_valid)
+    return error;
 
+  struct iovec ioVec;
   ioVec.iov_base = GetGPRBuffer();
   ioVec.iov_len = GetGPRSize();
 
   error = ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 
   if (error.Success())
     m_gpr_is_valid = true;
 
   return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteGPR() {
-  struct iovec ioVec;
-
-  m_gpr_is_valid = false;
+  Status error = ReadGPR();
+  if (error.Fail())
+    return error;
 
+  struct iovec ioVec;
   ioVec.iov_base = GetGPRBuffer();
   ioVec.iov_len = GetGPRSize();
 
+  m_gpr_is_valid = false;
+
   return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 }
 
 Status NativeRegisterContextLinux_arm64::ReadFPR() {
   Status error;
 
-  struct iovec ioVec;
+  if (m_fpu_is_valid)
+    return error;
 
+  struct iovec ioVec;
   ioVec.iov_base = GetFPRBuffer();
   ioVec.iov_len = GetFPRSize();
 
   error = ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
 
   if (error.Success())
     m_fpu_is_valid = true;
 
   return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteFPR() {
-  struct iovec ioVec;
-
-  m_fpu_is_valid = false;
+  Status error = ReadFPR();
+  if (error.Fail())
+    return error;
 
+  struct iovec ioVec;
   ioVec.iov_base = GetFPRBuffer();
   ioVec.iov_len = GetFPRSize();
 
+  m_fpu_is_valid = false;
+
   return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
 }
 
 void NativeRegisterContextLinux_arm64::InvalidateAllRegisters() {
   m_gpr_is_valid = false;
   m_fpu_is_valid = false;
+  m_sve_buffer_is_valid = false;
+  m_sve_header_is_valid = false;
+}
+
+Status NativeRegisterContextLinux_arm64::ReadSVEHeader() {
+  Status error;
+
+  if (m_sve_header_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetSVEHeader();
+  ioVec.iov_len = GetSVEHeaderSize();
+
+  error = ReadRegisterSet(&ioVec, GetSVEHeaderSize(), NT_ARM_SVE);
+
+  m_sve_header_is_valid = true;
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_arm64::WriteSVEHeader() {
+  Status error;
+
+  error = ReadSVEHeader();
+  if (error.Fail())
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetSVEHeader();
+  ioVec.iov_len = GetSVEHeaderSize();
+
+  m_sve_buffer_is_valid = false;
+  m_sve_header_is_valid = false;
+  m_fpu_is_valid = false;
+
+  return WriteRegisterSet(&ioVec, GetSVEHeaderSize(), NT_ARM_SVE);
+}
+
+Status NativeRegisterContextLinux_arm64::ReadAllSVE() {
+  Status error;
+
+  if (m_sve_buffer_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetSVEBuffer();
+  ioVec.iov_len = GetSVEBufferSize();
+
+  error = ReadRegisterSet(&ioVec, GetSVEBufferSize(), NT_ARM_SVE);
+
+  if (error.Success())
+    m_sve_buffer_is_valid = true;
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_arm64::WriteAllSVE() {
+  Status error;
+
+  error = ReadAllSVE();
+  if (error.Fail())
+    return error;
+
+  struct iovec ioVec;
+
+  ioVec.iov_base = GetSVEBuffer();
+  ioVec.iov_len = GetSVEBufferSize();
+
+  m_sve_buffer_is_valid = false;
+  m_sve_header_is_valid = false;
+  m_fpu_is_valid = false;
+
+  return WriteRegisterSet(&ioVec, GetSVEBufferSize(), NT_ARM_SVE);
+}
+
+void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
+  // Read SVE configuration data and configure register infos.
+  if (!m_sve_header_is_valid && m_sve_state != SVEState::Disabled) {
+    Status error = ReadSVEHeader();
+    if (!error.Success() && m_sve_state == SVEState::Unknown) {
+      m_sve_state = SVEState::Disabled;
+      GetRegisterInfo().ConfigureVectorRegisterInfos(
+          RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64);
+    } else {
+      if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)
+        m_sve_state = SVEState::FPSIMD;
+      else if ((m_sve_header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE)
+        m_sve_state = SVEState::Full;
+
+      uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE;
+      if (sve_vl_valid(m_sve_header.vl))
+        vq = sve_vq_from_vl(m_sve_header.vl);
+      GetRegisterInfo().ConfigureVectorRegisterInfos(vq);
+      m_sve_ptrace_payload.resize(SVE_PT_SIZE(vq, SVE_PT_REGS_SVE));
+    }
+  }
 }
 
 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset(
     const RegisterInfo *reg_info) const {
   return reg_info->byte_offset - GetGPRSize();
 }
 
+uint32_t NativeRegisterContextLinux_arm64::CalculateSVEOffset(
+    const RegisterInfo *reg_info) const {
+  // Start of Z0 data is after GPRs plus 8 bytes of vg register
+  uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
+  if (m_sve_state == SVEState::FPSIMD) {
+    const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+    sve_reg_offset =
+        SVE_PT_FPSIMD_OFFSET + (reg - GetRegisterInfo().GetRegNumSVEZ0()) * 16;
+  } else if (m_sve_state == SVEState::Full) {
+    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    sve_reg_offset =
+        SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
+  }
+  return sve_reg_offset;
+}
+
+void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
+  if (m_sve_state == SVEState::FPSIMD)
+    return m_sve_ptrace_payload.data() + SVE_PT_FPSIMD_OFFSET;
+
+  return m_sve_ptrace_payload.data();
+}
+
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h

protected:
   bool IsSVEP(unsigned reg) const { return m_register_info_up->IsSVEPReg(reg); }
   bool IsSVEVG(unsigned reg) const {
     return m_register_info_up->IsSVERegVG(reg);
   }
 
   uint32_t GetRegNumSVEZ0() const {
     return m_register_info_up->GetRegNumSVEZ0();
   }
-
+  uint32_t GetRegNumSVEFFR() const {
+    return m_register_info_up->GetRegNumSVEFFR();
+  }
   uint32_t GetRegNumFPCR() const { return m_register_info_up->GetRegNumFPCR(); }
   uint32_t GetRegNumFPSR() const { return m_register_info_up->GetRegNumFPSR(); }
 
   virtual bool ReadGPR() = 0;
   virtual bool ReadFPR() = 0;
   virtual bool WriteGPR() = 0;
   virtual bool WriteFPR() = 0;
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

public:
 
   bool IsSVEEnabled() const { return m_vector_reg_vq > eVectorQuadwordAArch64; }
 
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
+  uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
 
 private:
   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
       per_vq_register_infos;
 
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
 
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

 }
 
 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
   return sve_vg == reg;
 }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
 
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
+
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/Makefile

+C_SOURCES := main.c
+
+CFLAGS_EXTRAS := -march=armv8-a+sve
+
+include Makefile.rules

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

+"""
+Test the AArch64 SVE registers.
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+    def check_sve_register_size(self, set, name, expected):
+        reg_value = set.GetChildMemberWithName(name)
+        self.assertTrue(reg_value.IsValid(),
+                        'Verify we have a register named "%s"' % (name))
+        self.assertEqual(reg_value.GetByteSize(), expected,
+                         'Verify "%s" == %i' % (name, expected))
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    @skipIf
+    def test_sve_registers_configuration(self):
+        """Test AArch64 SVE registers size configuration."""
+        self.build()
+        self.line = line_number('main.c', '// Set a break point here.')
+
+        exe = self.getBuildArtifact("a.out")
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        lldbutil.run_break_set_by_file_and_line(
+            self, "main.c", self.line, num_expected_locations=1)
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
+                    substrs=["stop reason = breakpoint 1."])
+
+        target = self.dbg.GetSelectedTarget()
+        process = target.GetProcess()
+        thread = process.GetThreadAtIndex(0)
+        currentFrame = thread.GetFrameAtIndex(0)
+
+        has_sve = False
+        for registerSet in currentFrame.GetRegisters():
+            if 'Scalable Vector Extension Registers' in registerSet.GetName():
+                has_sve = True
+
+        if not has_sve:
+            self.skipTest('SVE registers must be supported.')
+
+        registerSets = process.GetThreadAtIndex(
+            0).GetFrameAtIndex(0).GetRegisters()
+
+        sve_registers = registerSets.GetValueAtIndex(2)
+
+        vg_reg = sve_registers.GetChildMemberWithName("vg")
+
+        vg_reg_value = sve_registers.GetChildMemberWithName(
+            "vg").GetValueAsUnsigned()
+
+        z_reg_size = vg_reg_value * 8
+
+        p_reg_size = z_reg_size / 8
+
+        for i in range(32):
+            self.check_sve_register_size(
+                sve_registers, 'z%i' % (i), z_reg_size)
+
+        for i in range(16):
+            self.check_sve_register_size(
+                sve_registers, 'p%i' % (i), p_reg_size)
+
+        self.check_sve_register_size(sve_registers, 'ffr', p_reg_size)
+
+    mydir = TestBase.compute_mydir(__file__)
+    @no_debug_info_test
+    @skipIf
+    def test_sve_registers_read_write(self):
+        """Test AArch64 SVE registers read and write."""
+        self.build()
+        self.line = line_number('main.c', '// Set a break point here.')
+
+        exe = self.getBuildArtifact("a.out")
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        lldbutil.run_break_set_by_file_and_line(
+            self, "main.c", self.line, num_expected_locations=1)
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
+                    substrs=["stop reason = breakpoint 1."])
+
+        target = self.dbg.GetSelectedTarget()
+        process = target.GetProcess()
+        thread = process.GetThreadAtIndex(0)
+        currentFrame = thread.GetFrameAtIndex(0)
+
+        has_sve = False
+        for registerSet in currentFrame.GetRegisters():
+            if 'Scalable Vector Extension Registers' in registerSet.GetName():
+                has_sve = True
+
+        if not has_sve:
+            self.skipTest('SVE registers must be supported.')
+
+        registerSets = process.GetThreadAtIndex(
+            0).GetFrameAtIndex(0).GetRegisters()
+
+        sve_registers = registerSets.GetValueAtIndex(2)
+
+        vg_reg = sve_registers.GetChildMemberWithName("vg")
+
+        vg_reg_value = sve_registers.GetChildMemberWithName(
+            "vg").GetValueAsUnsigned()
+
+        z_reg_size = vg_reg_value * 8
+
+        p_reg_size = int(z_reg_size / 8)
+
+        z_regs_value = '{' + \
+            ' '.join(('0x9d' for _ in range(z_reg_size))) + '}'
+
+        p_regs_value = '{' + \
+            ' '.join(('0xee' for _ in range(p_reg_size))) + '}'
+
+        for i in range(32):
+            self.runCmd('register write ' + 'z%i' %
+                        (i) + " '" + z_regs_value + "'")
+
+        for i in range(32):
+            self.expect("register read " + 'z%i' % (i), substrs=[z_regs_value])
+
+        for i in range(16):
+            self.runCmd('register write ' + 'p%i' %
+                        (i) + " '" + p_regs_value + "'")
+
+        for i in range(16):
+            self.expect("register read " + 'p%i' % (i), substrs=[p_regs_value])
+
+        self.runCmd('register write ' + 'ffr ' + "'" + p_regs_value + "'")
+
+        self.expect("register read " + 'ffr', substrs=[p_regs_value])

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c

+int main() {
+  asm volatile("ptrue p0.s\n\t");
+  asm volatile("fcpy  z0.s, p0/m, #5.00000000\n\t");
+  return 0; // Set a break point here.
+}
 No newline at end of file