AArch64 SVE register infos and core file support

[omjavaid]

Summary

This patch adds support for AArch64 SVE register infos description and register access via ptrace.

AArch64 SVE is a an optional extension of Arm v8.3-a architecture which introduces 32 vector registers Z, 16 predicate P registers and FFR predicate register. These registers have fixed names but can dynamically be configured to different size based on underlying OS configuration.

This patch adds register info struct that describes SVE register infos. Also provides native register context routines to access SVE registers. It introduces a mechanism to configure SVE register size and offsets at startup before exchanging register information across gdb-remote process.

It makes use of linux kernel definitions copied into lldb/source/Plugins/Process/Linux/LinuxPTraceDefines_arm64sve.h for backward compatibility with sysroots which might yet not support SVE definitions.

There are two test cases added to the testsuite one of them checks register size configuration based on vg (vector granule register). Also a test is added which verifies registers can be read and written.

There is no physical hardware currently available to test SVE and we make use of QEMU for the purpose of testing this feature.

[labath]

There is no physical hardware currently available to test SVE and we make use of QEMU for the purpose of testing this feature.

Are these registers presented in core files in any way? Would it be possible to at least test the RegisterInfoPOSIX_arm64.h changes that way?

[omjavaid]

Posting full diff.

[omjavaid]

In D77047#1954696, @labath wrote:

There is no physical hardware currently available to test SVE and we make use of QEMU for the purpose of testing this feature.

Are these registers presented in core files in any way? Would it be possible to at least test the RegisterInfoPOSIX_arm64.h changes that way?

Yes. Core file section is added for SVE registers but i have not tried to get that working with LLDB. I will get back to you on this.

[omjavaid]

In D77047#1956774, @omjavaid wrote:

In D77047#1954696, @labath wrote:

There is no physical hardware currently available to test SVE and we make use of QEMU for the purpose of testing this feature.

Are these registers presented in core files in any way? Would it be possible to at least test the RegisterInfoPOSIX_arm64.h changes that way?

Yes. Core file section is added for SVE registers but i have not tried to get that working with LLDB. I will get back to you on this.

@labath Core file FP register access is not supported on AArch64. I am working on a follow up patch to fix it. This patch only has linux changes so can we get this through?

[labath]

In D77047#1966539, @omjavaid wrote:

@labath Core file FP register access is not supported on AArch64. I am working on a follow up patch to fix it. This patch only has linux changes so can we get this through?

This patch is a bit big and basically untested (an unconditionally skipped test hardly counts), so I am looking for ways to split it up and add some test coverage. I'm also worried about copying what appear to be chunks of linux header files...

lldb/source/Plugins/Process/Linux/NativeThreadLinux.h

42–43 ↗

(On Diff #254454)

Why can't this work be done in the register context constructor? I believe we are always creating a Thread (and its reg context) while it is stopped...

lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h

38–40 ↗

(On Diff #254454)

I can't find any callers of this function. Who is calling it?

[omjavaid]

In D77047#1971454, @labath wrote:

In D77047#1966539, @omjavaid wrote:

@labath Core file FP register access is not supported on AArch64. I am working on a follow up patch to fix it. This patch only has linux changes so can we get this through?

This patch is a bit big and basically untested (an unconditionally skipped test hardly counts), so I am looking for ways to split it up and add some test coverage. I'm also worried about copying what appear to be chunks of linux header files...

I also considered licensing issues around copying this chunk but found GDB also copied this chunk of linux defines into its sources. I think its part of linux headers with license to freely use these headers in client programs. Do you know any licensing expert who can give us feedback on this patch? The only reason we have to include these headers here is that on older sysroots AArch64 compiler we wont be able to compile this code as they dont have these headers included so far but newer version do include these headers by default.

As for the test coverage I am working on a follow up to this patch that will include corefile support I hope we ll be able to test major portion of this patch with that support.

[labath]

In D77047#1980248, @omjavaid wrote:

In D77047#1971454, @labath wrote:

In D77047#1966539, @omjavaid wrote:

@labath Core file FP register access is not supported on AArch64. I am working on a follow up patch to fix it. This patch only has linux changes so can we get this through?

This patch is a bit big and basically untested (an unconditionally skipped test hardly counts), so I am looking for ways to split it up and add some test coverage. I'm also worried about copying what appear to be chunks of linux header files...

I also considered licensing issues around copying this chunk but found GDB also copied this chunk of linux defines into its sources. I think its part of linux headers with license to freely use these headers in client programs. Do you know any licensing expert who can give us feedback on this patch? The only reason we have to include these headers here is that on older sysroots AArch64 compiler we wont be able to compile this code as they dont have these headers included so far but newer version do include these headers by default.

The situation might be different for gdb since they're both GPL-ish. For licensing questions you could try mailing llvm foundation.

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1191 ↗

(On Diff #254454)

SetRegisterInfoMode(vq); is getting called over here.

lldb/source/Plugins/Process/Linux/NativeThreadLinux.h

42–43 ↗

(On Diff #254454)

ConfigureRegisterContext makes sure that sve register offsets and sizes are correctly updated and synced from ptrace on every stop. If SVE registers reconfigure themselves we ll have to update that information into our dynamic register infos array. Although for the context of this patch it assumes it will never change its register size during execution. But I will follow up patch that implements that behaviour.

[omjavaid]

This update includes core file register access for SVE registers. Register descriptions can now be tested with core dump.

@labath Should I post QEMU SVE setup instructions somewhere if you want to have a go at running included test cases.?

[omjavaid]

Also about licensing issues of included macros I am in contact with original authors from ARM and I hope they will be able to help sign off this patch for LLVM submission.

[labath]

In D77047#1996198, @omjavaid wrote:

This update includes core file register access for SVE registers. Register descriptions can now be tested with core dump.

Cool. Could you please split off the stuff necessary for making core files work into a separate patch, and have the "native" patch be on top of that. I want to get an idea of how much of new code is included in the second patch.

@labath Should I post QEMU SVE setup instructions somewhere if you want to have a go at running included test cases.?

I think that would be very valuable. Not really much for this patch (I probably wont get around to running it), but for any future contributors (inlcuding myself) whose patches break some arm stuff (be it SVE-related or not).

In D77047#1996202, @omjavaid wrote:

Also about licensing issues of included macros I am in contact with original authors from ARM and I hope they will be able to help sign off this patch for LLVM submission.

Awesome.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1191 ↗

(On Diff #254454)

Ok, I see. That makes sense. The part that seems pretty unfortunate here is that you've needed to add a fairly strange function to the generic (RegisterInfoInterface) interface even though the caller and callee are in arm64-specific code. Let's see if we can avoid that.

What if, instead of remangling the register infos in RegisterInfoPOSIX_arm64 every time that SetRegisterInfoMode is called, the "mode" was a argument to the class constructor, and changing of the mode was implemented by creating a new "info" object? I.e., this code would instead of calling SetRegisterInfoMode(vq);, do something like m_register_info_interface_up = std::make_unique<RegisterInfoPOSIX_arm64>(vq);

Would that work?

lldb/source/Plugins/Process/Linux/NativeThreadLinux.h

42–43 ↗

(On Diff #254454)

Ok, that makes sense now. The thing on my mind in that case is that this functionality overlaps a lot with InvalidateAllRegisters we've added a couple of patches back. I think it would be nice to have just one function which "reinitializes" a register context. InvalidateAllRegisters wouldn't work right now, because it's called before a resume, but if we changed it to be called after a stop, it would be able to do both things.

Would it be possible to change it so that this InvalidateAllRegisters is called after a stop, e.g. in NativeThreadLinux::SetStopped. I am sorry for the churn, I know it was my idea to call it before a resume -- it seemed like a reasonable thing to do at the time, but not any more.. :(

[omjavaid]

This patch now contains AArch64 SVE register infos description and support for core dump SVE register access. Linux ptrace support will be submitted in a follow up patch while linux ptrace headers are being submitted by Arm under license agreement separately.

[labath]

(sorry about all the editing -- I'm trying to figure out the order of these patches)

[omjavaid]

New update contains minor update needed to accommodate SVE PTrace macros header from ARM.

[omjavaid]

This update remove skipping over register infos requirement by overlapping sve register numbers with debug register numbers which are not required by Linux register context.

[labath]

I'm worried about the confusing relationship between RegisterInfos_arm64_sve.h and RegisterInfos_arm64.h and the overlap in the register numbers it enforces. when we discussed this last time, my understanding was that the sve registers could be inserted _before_ the debug registers (similar to what happened with D24255). Now I see that may not be possible because some of these registers are used in the darwin arm64 register context. However, that makes the whole idea much less appealing.

Would it be possible to organize these headers like this:

• create a new header which holds common register definitions: this would be register numbers for the gpr and fpr registers (and their respective _contains arrays).
• have RegisterInfos_arm64_sve.h include this header and provide additional register definitions, and define its RegisterInfo array to match
• have RegisterInfos_arm64.h to the same

What I am hoping to achieve this way is to remove the DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT condition macro (dragons (ODR violations) lie there), and the duplicate enum values associated with it.

[omjavaid]

In this updated I have removed overlapping parts of RegisterInfos_arm64.h and RegisterInfos_arm64_sve.h which in turn removes any possibility of duplicate definitions.

Both register infos define separate static register info arrays namely g_register_infos_arm64_le and g_register_infos_arm64_sve_le. Definition of FPR registers is also different and their invalidate/contains reg lists are also different. For the context of all native register context which do not yet support SVE g_register_infos_arm64_le will be used as they only include RegisterInfos_arm64.h.

@labath do you think there is still chance of any ODR violations?

[labath]

There's always a chance for ODR violations, particularly with header files defining static objects. This looks better though what I really wanted was to keep the non-sve register info array (g_register_infos_arm64_le) completely out of the path of the sve header. Like, by using three headers, one defining g_register_infos_arm64_le (and stuff specific to that like the exception registers), one defining the sve array, and the third one which would contain the things common to both. Nonetheless, I think we can now move on to aspects of this patch. Please see my inline comments.

lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h

38–40 ↗

(On Diff #254454)

It still seems to me that this function is not used (in this patch at least).

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp

96

http://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return

lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h

64–68 ↗

(On Diff #274390)

I don't believe these functions should be present on the generic interface. The only caller and the only implementation of them is already arm64-specific, so it should be possible to arrange it such that they don't need to go through the base class interface. For instance the RegisterContextCorePOSIX_arm64 constructor could accept an RegisterInfoPOSIX_arm64 instance to indicate what it needs to work with, and then downcast m_register_info_up (via a helper function?) when it needs to call these. Solutions without downcasting are possible too, though may require a bit more refactoring.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

73–90

no else after return

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

41–43

Do these need to be public? If so, why?

56

Why is this mutable?

[omjavaid]

In D77047#2125220, @labath wrote:

There's always a chance for ODR violations, particularly with header files defining static objects. This looks better though what I really wanted was to keep the non-sve register info array (g_register_infos_arm64_le) completely out of the path of the sve header. Like, by using three headers, one defining g_register_infos_arm64_le (and stuff specific to that like the exception registers), one defining the sve array, and the third one which would contain the things common to both. Nonetheless, I think we can now move on to aspects of this patch. Please see my inline comments.

I am working to fix this with D80105 by defining dynamic register infos array based on register sets which will be requirement for Pointer Authentication and MTE. But I wanted to first get done with SVE and come back to register infos refactoring later.

lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h

38–40 ↗

(On Diff #254454)

Ack. This function is used by chiild revisions which adds ptrace support. I ll move it there.

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp

96

Ack.

lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h

64–68 ↗

(On Diff #274390)

Agreed. I ll make an arrangement for this in updated rev.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

73–90

Ack.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

41–43

These should be private. I ll update this in updated rev.

56

It was pulled in from NativeRegisterContextLinux_arm64 and got set mutable by mistake I ll correct in updated rev.

[omjavaid]

@labath I have updated diff after resolving issues highlighted. Also I have removed dependence on generic interfaces.

[labath]

Thanks. This looks is starting to look good now. I didn't get a chance to review all of the changes, but here's a few more things that I noticed.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

79–83

Now that this is arm-specific, I am wondering if there isn't a better name for this than "register info 'mode'". Maybe it could be just "enable/disable SVE" ? Specifically, if the validity of the "mode" is checked by the caller, then we can avoid this RegisterInfoModeIsValid business...

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

21

It would be also nice if this constructor accepted a RegisterInfoPOSIX_arm64 instead of plain RegisterInfoInterface. That would make it much harder to misuse this class. For that we'd need to slightly refactor the construction code in ThreadElfCore. For example, we could swap the order of the "os" and "machine" switches and then join the two "machine" switches that construct RegisterInfoInterfaces and RegisterContexts.

Maybe you could do that as a separate patch?

73–90

Well.. that's one way of handing that.. :) It's not necessarily bad, but I was imagining you would just delete all the "else"s...

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

19–24

This is including platform-specific headers, but elf cores should be readable from any host. I guess you should just re-define the relevant constants somewhere. (I'm not sure what they are.)

lldb/source/Utility/ARM64_DWARF_Registers.h

54–146 ↗

(On Diff #275037)

All of these numbers are from the official spec, right? Maybe you could just commit this straight away so it does not clutter this review.

[omjavaid]

This update incorporates suggestion from last iteration and also rebases after merger to registersets and register infos in RegisterInfosPOSIX_arm64.
Also I have posted a separate patch D83541 to make lldb/source/Plugins/Process/Linux/LinuxPTraceDefines_arm64sve.h platform independent in order to use them with elf-core.

@labath what do you think ?

[labath]

I didn't notice this before, but I see now that there's more register number overlap in lldb-arm64-register-enums.h. Having one overlapping enum is bad enough, but two seems really too much? Can we avoid the second enum somehow, at least? Perhaps by switching RegisterContextCorePOSIX_arm64 to use the other enum definitions for its work?

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

256–257

This comment looks outdated.

280

IIUC, m_sve_enabled is only true if m_vector_reg_vq is not zero. Could we delete this variable and just make a function to make that comparison?

288–291

It doesn't look like m_dynamic_register_infos is needed -- you could just make m_register_info_p point directly into the map.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

86

The offset argument is not set anywhere.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

19

I guess this does not make sense now that the header is standalone

[omjavaid]

This update addresses issues raised in last iteration. Also have removed dependence on lldb-arm64-register-enums.h.

[labath]

Some more comments (and questions) from me. Sorry about the back-and-forth. It's taking me a while to wrap my head around this, and as I start to understand things, new questions arise...

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

282–290

I'd probably try relying on the fact that operator[] constructs an empty vector, and that the empty vector is not a valid register info value. Something like:

std::vector<RegisterInfo> &new_reg_info = m_per_vq_reg_infos[sve_vq];
if (new_reg_info.empty()) {
  new_reg_info = llvm::makeArrayRef(g_register_infos_arm64_sve_le, m_register_info_count);
  ...
}
m_register_info_p = new_reg_info.data();

That would make this less of a mouthful and also avoid looking up the same key in the map three or four times.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

17–22

If this is going to be a class enum (which I think is a good idea), then there's no need to repeat the type name in the actual enumerators. It also seems like this could/should follow the lldb naming conventions (SveState::Disabled, etc).

lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h

261 ↗

(On Diff #277701)

I guess these changes should be reverted now?

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

I'm confused by this function. If I understant the SVE_PT macros and the logic in RegisterInfoPOSIX_arm64::ConfigureVectorRegisterInfos correctly, then they both seem to encode the same information. And it seems to me that this function should just be reg_infos[reg_num].offset - some_constant, which is the same thing that we're doing for the arm FP registers when SVE is disabled, and also for most other architectures too.

Why is that not the case? Am I missing something? If they are not encoding the same thing, could they be made to encode the same thing?

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

19

Please group the header next to other Plugins/Process/Utility header

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

463–464

What's up with these?

[omjavaid]

In D77047#2125220, @labath wrote:

There's always a chance for ODR violations, particularly with header files defining static objects. This looks better though what I really wanted was to keep the non-sve register info array (g_register_infos_arm64_le) completely out of the path of the sve header. Like, by using three headers, one defining g_register_infos_arm64_le (and stuff specific to that like the exception registers), one defining the sve array, and the third one which would contain the things common to both. Nonetheless, I think we can now move on to aspects of this patch. Please see my inline comments.

I am working to fix this with D80105 by defining dynamic register infos array based on register sets which will be requirement for Pointer Authentication and MTE. But I wanted to first get done with SVE and come back to register infos refactoring later.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

282–290

ACK

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

17–22

ACK

lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h

261 ↗

(On Diff #277701)

ACK

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

This function calculates offset of a particular register in core note data. SVE data in core dump is similar to what PTrace emits and offsets into this data is not linear. SVE macros are used to access those offsets based on register numbers and currently selected vector length.
Also for the purpose of ease we have linear offsets in SVE register infos and it helps us simplify register data once it makes way to GDBRemoteRegisterContext on the client side.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

19

ACK

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

463–464

Sorry Typo

[labath]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

Could you give an example of the non-linearity of the core dump data? (Some registers, and their respective core file and gdb-remote offsets)

[omjavaid]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

In case of core file we create a buffer m_sveregset which stores SVE core note information
m_sveregset =

getRegset(notes, m_register_info_up->GetTargetArchitecture().GetTriple(),
          AARCH64_SVE_Desc);

At this point we do not know what was the vector length and at what offsets in the data our registers are located. We read top bytes of size use_sve_header and read vector length. Based on this information we configure vector length in Register infos. While the SVE payload starts with user_sve_header then there are some allignment bytes followed by vector length based Z registers followed by P and FFR, then there are some more allginment bytes followd by FPCR and FPSR. Macros provided by Linux help us jump to the desired offset by providing register number and vq into the core note or Ptrace payload.

In case of client side storage we store GPRs at linear offset followed by Vector Granule register. Then there are SVE registers Z, P, FFR, FPSR and FPCR. Offsets of V, D and S registers in FPR regset overlap with corresponding first bytes of Z registers and will be same as corresponding Z register. While both FP/SVE FPSR share same register offset, size and register number.

Here is an excerpt from https://github.com/torvalds/linux/blob/master/Documentation/arm64/sve.rst

SVE_PT_REGS_FPSIMD
SVE registers are not live (GETREGSET) or are to be made non-live (SETREGSET).
The payload is of type struct user_fpsimd_state, with the same meaning as for NT_PRFPREG, starting at offset SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.
Extra data might be appended in the future: the size of the payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).
vq should be obtained using sve_vq_from_vl(vl).

or

SVE_PT_REGS_SVE
SVE registers are live (GETREGSET) or are to be made live (SETREGSET).
The payload contains the SVE register data, starting at offset SVE_PT_SVE_OFFSET from the start of user_sve_header, and with size SVE_PT_SVE_SIZE(vq, flags);

[labath]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

Given this

SVE payload starts with ... followed by vector length based Z registers followed by P and FFR,

and this

In case of client side storage we store GPRs ... Then there are SVE registers Z, P, FFR, FPSR and FPCR

I would expect that for each of the Z, P and FFR registers, the expression offset_in_core(reg) - offset_in_gdb_remote(reg) is always the same constant (and is basically equal to SVE_PT_SVE_ZREG_OFFSET(vq, 0) - reg_info[Z0].byte_offset). So we could just add/subtract that constant to the gdb-remote byte_offset field instead of painstakingly decomposing the register number only for the linux macros to reconstruct it back again. Is that not so?

[omjavaid]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

The standard never talks about Z, P and FFR being contagious that is what I learnt by reading macros. There standard states this:

If the registers are present, the remainder of the record has a vl-dependent size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to the members.
Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the start of the register's representation in memory.
If the SVE context is too big to fit in sigcontext.reserved[], then extra space is allocated on the stack, an extra_context record is written in reserved[] referencing this space. sve_context is then written in the extra space. Refer to [1] for further details about this mechanism.

I understand what you are talking about but given the macros were specifically provided and above line about register record was vague and I thought best is to follow the macros for offset calculation although other way around is simpler but may be slightly unreliable.

I suggest to keep this as it is unless there is strong reason apart from slight performance penalty. This resembles with GDB implementation which was done by ARM and I am only following that as reference. May be we can revise this in future when the feature becomes more mainstream.

[labath]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

I'm not worried about the performance penalty (most of these abstractions can be optimized away anyway). I'm more worried about the maintainability penalty incurred by a non-standard and fairly complicated solution.

The way I see it, it doesn't really matter how exactly the specification describes these things. Having the macros is nice, but it's not their names that become a part of the ABI -- their implementation does. So they (linux, arm, whoever) cannot change the layout of the these registers without breaking all existing applications (and core files) any more than they can change the layout of the general purpose registers (which we also access by offset, without any fancy macros). In fact, even if they did change the layout, given that we have a copy of these headers, we wouldn't automatically inherit those changes anyway, but would have to take some manual action. And since we'd probably want to maintain some sort of backwards compatibility, we couldn't just replace the new macro definitions, but would have to do some sort of versioning (just today I got reminded that lldb contains versioned layouts of various internal structs used by the ObjC runtime).

So, for that reason I am more concerned about consistency with other lldb register contexts than I am with consistency with gdb.

Also, I bet gdb doesn't have an equivalent of our RegisterInfo struct. Without that, using these macros would be obviously better, but given that we have that, and we already use it to access other registers, ditching that for macros does not seem like a win to me.

Another way to look at this would be to compare this to e.g. ELF reading code in llvm. We cannot just include <linux/elf.h> as we want this to be cross-platform. However, we also don't just copy the header blindly into our code base. We don't depart from it needlessly, but we do make sure that it plays well with the rest of llvm -- #defines are changed to enums, we add templates to select between 64/32 bit versions, change some platform-specific names so that different platforms may co-exist, etc.

[omjavaid]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

82–106

I understand your point here and by referring to Linux, Arm or GDB implementation I only wanted to make sure that we are implementing the architecture and platform specific parts correctly. The choice of using Linux/SVE specific macros in elf-core context was not a blind decision. I am not advocating for following a particular implementations and I would not have pulled in these Linux specific macros into elf-core implementation if the SVE core note layout was independent of Linux platform specifics like sig_context and user_sve_header. Offset to the start of register data in NT_ARM_SVE is also calculated after doing alignment correction based on VQ and size of sig_context. Given that SVE is currently supported by Linux only, NT_ARM_SVE is Linux only core note and core dump generated makes use of these macro definitions I had no choice but to include them for extraction of data from NT_ARM_SVE section. If I had not followed these macros I still would have written something similar my self for register data extraction from NT_ARM_SVE elf core note.

I am going to post another update where I ll try to minimize use of these macros in offset calculation.

[omjavaid]

This update address issues highlighted in last iteration and also minimizes the use of SVE_PT macros by using RegisterInfo.byte_size and byte_offset where possible.

@labath What do you think ?

[omjavaid]

Minor fix removing GetRegNumP0 which is no longer needed.

[labath]

At this point, I think I (finally) have a good understanding of both how this patch works and interacts with the rest of the world. I have one more batch of comments, but hopefully none are too controversial, and I really do hope this is the last iteration.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

289

I think all uses of new_reg_info_p could just be replaced by reg_info_ref

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

63–66

What's up with this copying? We already have the data in the m_sveregset DataExtractor. What's the reason for copying it into the m_sve_note_payload vector? Also, m_sve_header seems like it could just be a reinterpret_casted pointer into that buffer instead of a copy. (Maybe not even a pointer, just a utility function which performs the cast when called).

Actually, when I think about casts and data extractors, I am reminded of endianness. This will access those fields using host endianness, which is most likely not what we want to do. So, probably the best/simplest solution would be to indeed declare a user_sve_header struct, but don't populate it via memcpy, but rather via the appropriate DataExtractor extraction methods. Since the only field of the user_sve_header used outside this function is the vl field, perhaps the struct could be a local variable and only the vector length would be persisted. That would be consistent with how the flags field is decoded and stored into the m_sve_state field.

(If the struct fields are always little-endian (if that's true, I thought arm has BE variants) then you could also stick to the reinterpret_cast idea, but change the types of the struct fields to llvm::support::ulittleXX_t to read them as LE independently of the host.)

82–106

Thanks for your patience. I think this looks better. The more I understand how these work, the more I realize that will need fairly special handling..

84–86

This is already checked by ReadRegister and the false -> uint32_t conversion is dodgy. An assertion would completely suffice here.

120

This IsFPR check is now redundant.

132–133

These two registers are special-cased both here and in the CalculateSVEOffset. Given that both functions also do a switch over the sve "states", it makes following the code quite challenging. What if we moved the handling of these registers completely up-front, and removed their handling from CalculateSVEOffset completely?
I'm thinking of something like:

if (reg == GetRegNumFPCR() && m_sve_state != SVEState::Disabled) {
  src = GetSVEBuffer() + GetFPCROffset(); // Or maybe just inline GetFPCROffset here
} else if (reg == GetRegNumFPSR() && m_sve_state != SVEState::Disabled) {
  src = ...;
} if (IsFPR(reg)) {
  // as usual, only you can assume that FP[CS]R are already handled if SVE is enabled
}

141–142

This also looks endian-incorrect. Maybe value = GetSVERegVG(); return true; ?

144

A switch over possible m_sve_state values would likely be cleaner.

154

I guess it would be better to do the cast inside GetSVEBuffer. (and please make that a c++ reinterpret_cast).

160

it seems that src should be a const pointer.

[omjavaid]

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

289

Ack.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

63–66

Agreed m_sve_note_payload is redundant. Most of the implementation was mirrored from ptrace implementation and I was lazy enough and did not remove the redundancies which are not needed in case of core dump.

About endianess of SVE data I dont think it will create any problem as the data is transferred in endian invariant format. According to the standard here:

• Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory between userspace and the kernel, the register value is encoded in memory in an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at byte offset i from the start of the memory representation. This affects for example the signal frame (struct sve_context) and ptrace interface (struct user_sve_header) and associated data.

84–86

Ack.

120

Ack,

132–133

Ok will try to update in next revision.

141–142

Endian invariant as explained above.

144

Ack.

154

Ack.

160

Ack.

[omjavaid]

In this update I have addressed issues highlighted in last review iteration.

@labath Does this now look LGTM?

[labath]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

63–66

Ok, so if I parse that correctly, this is basically saying that the register values are always little-endian. Fair enough. However, lldb will be reading these things using the host endianness, so the values will be incorrect on a big-endian host.

Also, the are you sure that this includes the metadata in the user_sve_header field? The documentation does mention the struct explicitly, but then it also very explicitly speaks about register values. The data in the struct is not a register value, and I can find no evidence of byte-swapping in the linux kernel (https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/ptrace.c#L769).

[omjavaid]

This update plugs the holes susceptible to bugs by endianity variations. I have used DataExtractor GetU16 to read flags and vl from user_sve_header. Also removed the memset and replaced it with SetFromMemoryData function.

Moreover a new test is added which tests SVE FPSIMD mode core file.

[omjavaid]

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

63–66

@labath Thanks for being great help in this review. I think you were right about the user_sve_header being susceptible to endianity problems. I have plugged the issues now.

[labath]

I think this is as good as we can get right now. Thanks for sticking through. Two quick comments inline.

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

152–153

Are there any FPR registers which we should not be able to retrieve from the SVE state? I'm wondering if this should be turned into an assert.

164–196

It looks like this is only used in the IsSVEZ(reg) block below. You could move the declarations there and avoid initializations with bogus values.

[omjavaid]

This update makes minor adjustments before merge in light of final comments.

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h

protected:
   virtual const lldb_private::RegisterInfo *GetRegisterInfo();
 
   bool IsGPR(unsigned reg);
 
   bool IsFPR(unsigned reg);
 
   size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm64::FPU); }
 
+  bool IsSVE(unsigned reg) const;
+
+  bool IsSVEZ(unsigned reg) const { return m_register_info_up->IsSVEZReg(reg); }
+  bool IsSVEP(unsigned reg) const { return m_register_info_up->IsSVEPReg(reg); }
+  bool IsSVEVG(unsigned reg) const {
+    return m_register_info_up->IsSVERegVG(reg);
+  }
+
+  uint32_t GetRegNumSVEZ0() const {
+    return m_register_info_up->GetRegNumSVEZ0();
+  }
+
+  uint32_t GetRegNumFPCR() const { return m_register_info_up->GetRegNumFPCR(); }
+  uint32_t GetRegNumFPSR() const { return m_register_info_up->GetRegNumFPSR(); }
+
   virtual bool ReadGPR() = 0;
   virtual bool ReadFPR() = 0;
   virtual bool WriteGPR() = 0;
   virtual bool WriteFPR() = 0;
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H

lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp

 
 bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) {
   if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
       RegisterInfoPOSIX_arm64::FPRegSet)
     return true;
   return false;
 }
 
+bool RegisterContextPOSIX_arm64::IsSVE(unsigned reg) const {
+  if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+      RegisterInfoPOSIX_arm64::SVERegSet)
+    return true;
+  return false;
+}
+
 RegisterContextPOSIX_arm64::RegisterContextPOSIX_arm64(
     lldb_private::Thread &thread,
     std::unique_ptr<RegisterInfoPOSIX_arm64> register_info)
     : lldb_private::RegisterContext(thread, 0),
       m_register_info_up(std::move(register_info)) {}
 
 RegisterContextPOSIX_arm64::~RegisterContextPOSIX_arm64() {}
 
RegisterContextPOSIX_arm64::GetRegisterInfo() {
   // this scope.
   return m_register_info_up->GetRegisterInfo();
 }
 
 const lldb_private::RegisterInfo *
 RegisterContextPOSIX_arm64::GetRegisterInfoAtIndex(size_t reg) {
   if (reg < GetRegisterCount())
     return &GetRegisterInfo()[reg];
-  else
-    return nullptr;
+
 }
 
 size_t RegisterContextPOSIX_arm64::GetRegisterSetCount() {
   return m_register_info_up->GetRegisterSetCount();
 }
 
 const lldb_private::RegisterSet *
 RegisterContextPOSIX_arm64::GetRegisterSet(size_t set) {
   return m_register_info_up->GetRegisterSet(set);
 }
 
 const char *RegisterContextPOSIX_arm64::GetRegisterName(unsigned reg) {
   if (reg < GetRegisterCount())
     return GetRegisterInfo()[reg].name;
   return nullptr;
 }

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
 
 #include "RegisterInfoAndSetInterface.h"
 #include "lldb/Target/RegisterContext.h"
 #include "lldb/lldb-private.h"
+#include <map>
+
+enum class SVEState { Unknown, Disabled, FPSIMD, Full };
 
 class RegisterInfoPOSIX_arm64
     : public lldb_private::RegisterInfoAndSetInterface {
 public:
-  enum { GPRegSet = 0, FPRegSet };
+  enum { GPRegSet = 0, FPRegSet, SVERegSet };
+
+  // AArch64 Register set FP/SIMD feature configuration
+  enum {
+    eVectorQuadwordAArch64,
+    eVectorQuadwordAArch64SVE,
+    eVectorQuadwordAArch64SVEMax = 256
+  };
 
   // based on RegisterContextDarwin_arm64.h
   struct GPR {
     uint64_t x[29]; // x0-x28
     uint64_t fp;    // x29
     uint64_t lr;    // x30
     uint64_t sp;    // x31
     uint64_t pc;    // pc
public:
   size_t GetGPRSize() const override;
 
   size_t GetFPRSize() const override;
 
   const lldb_private::RegisterInfo *GetRegisterInfo() const override;
 
   uint32_t GetRegisterCount() const override;
 
   const lldb_private::RegisterSet *
   GetRegisterSet(size_t reg_set) const override;
 
   size_t GetRegisterSetCount() const override;
 
   size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
 
+  uint32_t ConfigureVectorRegisterInfos(uint32_t mode);
+
+  bool VectorSizeIsValid(uint32_t vq) {
+    if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
+      return true;
+    return false;
+  }
+
+  bool IsSVEEnabled() const { return m_vector_reg_vq > eVectorQuadwordAArch64; }
+
+  bool IsSVEZReg(unsigned reg) const;
+  bool IsSVEPReg(unsigned reg) const;
+  bool IsSVERegVG(unsigned reg) const;
+
+  uint32_t GetRegNumSVEZ0() const;
+  uint32_t GetRegNumFPCR() const;
+  uint32_t GetRegNumFPSR() const;
+
 private:
-  uint32_t num_registers;
-  uint32_t num_gpr_registers;
-  uint32_t num_fpr_registers;
-
-  uint32_t last_gpr;
-  uint32_t first_fpr;
-  uint32_t last_fpr;
+  typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
+      per_vq_register_infos;
+
+  per_vq_register_infos m_per_vq_reg_infos;
+
+  uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
 
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

 #define GPR_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
 
 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
 #define FPU_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) +                \
    sizeof(RegisterInfoPOSIX_arm64::GPR))
 
+// This information is based on AArch64 with SVE architecture reference manual.
+// AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
+// (First Fault) register and a VG (Vector Granule) pseudo register.
+
+// SVE 16-byte quad word is the basic unit of expansion in vector length.
+#define SVE_QUAD_WORD_BYTES 16
+
+// Vector length is the multiplier which decides the no of quad words,
+// (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
+// is decided during execution and can change at runtime. SVE AArch64 register
+// infos have modes one for each valid value of vector length. A change in
+// vector length requires register context to update sizes of SVE Z, P and FFR.
+// Also register context needs to update byte offsets of all registers affected
+// by the change in vector length.
+#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
+
+#define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
+
 #define EXC_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) +                \
    sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
    sizeof(RegisterInfoPOSIX_arm64::FPU))
 #define DBG_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) +                \
    sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
    sizeof(RegisterInfoPOSIX_arm64::FPU) +                                      \

 #define REG_CONTEXT_SIZE                                                       \
   (sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
    sizeof(RegisterInfoPOSIX_arm64::FPU) +                                      \
    sizeof(RegisterInfoPOSIX_arm64::EXC))
 
 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
 #include "RegisterInfos_arm64.h"
+#include "RegisterInfos_arm64_sve.h"
 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
 
 static const lldb_private::RegisterInfo *
 GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
     return g_register_infos_arm64_le;
   default:
     assert(false && "Unhandled target architecture.");
     return nullptr;
   }
 }
 
 // Number of register sets provided by this context.
 enum {
   k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
   k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
-  k_num_register_sets = 2
+  k_num_sve_registers = sve_ffr - sve_vg + 1,
+  k_num_register_sets = 3
 };
 
 // ARM64 general purpose registers.
 static const uint32_t g_gpr_regnums_arm64[] = {
     gpr_x0,  gpr_x1,   gpr_x2,  gpr_x3,
     gpr_x4,  gpr_x5,   gpr_x6,  gpr_x7,
     gpr_x8,  gpr_x9,   gpr_x10, gpr_x11,
     gpr_x12, gpr_x13,  gpr_x14, gpr_x15,
static const uint32_t g_fpu_regnums_arm64[] = {
     fpu_d20,  fpu_d21,  fpu_d22,
     fpu_d23,  fpu_d24,  fpu_d25,
     fpu_d26,  fpu_d27,  fpu_d28,
     fpu_d29,  fpu_d30,  fpu_d31,
     fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
                1) == k_num_fpr_registers,
               "g_fpu_regnums_arm64 has wrong number of register infos");
-// clang-format on
+
+// ARM64 SVE registers.
+static const uint32_t g_sve_regnums_arm64[] = {
+    sve_vg,  sve_z0,  sve_z1,
+    sve_z2,  sve_z3,  sve_z4,
+    sve_z5,  sve_z6,  sve_z7,
+    sve_z8,  sve_z9,  sve_z10,
+    sve_z11, sve_z12, sve_z13,
+    sve_z14, sve_z15, sve_z16,
+    sve_z17, sve_z18, sve_z19,
+    sve_z20, sve_z21, sve_z22,
+    sve_z23, sve_z24, sve_z25,
+    sve_z26, sve_z27, sve_z28,
+    sve_z29, sve_z30, sve_z31,
+    sve_p0,  sve_p1,  sve_p2,
+    sve_p3,  sve_p4,  sve_p5,
+    sve_p6,  sve_p7,  sve_p8,
+    sve_p9,  sve_p10, sve_p11,
+    sve_p12, sve_p13, sve_p14,
+    sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
+static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
+               1) == k_num_sve_registers,
+              "g_sve_regnums_arm64 has wrong number of register infos");
+
 // Register sets for ARM64.
 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
     {"General Purpose Registers", "gpr", k_num_gpr_registers,
      g_gpr_regnums_arm64},
     {"Floating Point Registers", "fpu", k_num_fpr_registers,
-     g_fpu_regnums_arm64}};
+     g_fpu_regnums_arm64},
+    {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
+     g_sve_regnums_arm64}};
 
 static uint32_t
 GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
     return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
                                  sizeof(g_register_infos_arm64_le[0]));
   default:
     assert(false && "Unhandled target architecture.");
     return 0;
   }
 }
 
 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
     const lldb_private::ArchSpec &target_arch)
     : lldb_private::RegisterInfoAndSetInterface(target_arch),
       m_register_info_p(GetRegisterInfoPtr(target_arch)),
       m_register_info_count(GetRegisterInfoCount(target_arch)) {
-
-  switch (target_arch.GetMachine()) {
-  case llvm::Triple::aarch64:
-  case llvm::Triple::aarch64_32:
-    num_registers = k_num_gpr_registers + k_num_fpr_registers;
-    num_gpr_registers = k_num_gpr_registers;
-    num_fpr_registers = k_num_fpr_registers;
-    last_gpr = gpr_w28;
-    first_fpr = fpu_v0;
-    last_fpr = fpu_fpcr;
-    break;
-  default:
-    assert(false && "Unhandled target architecture.");
-    break;
-  }
 }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const {
-  return num_gpr_registers + num_fpr_registers;
+  if (IsSVEEnabled())
+    return k_num_gpr_registers + k_num_fpr_registers + k_num_sve_registers;
+
+  return k_num_gpr_registers + k_num_fpr_registers;
 }
 
 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const {
   return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
 }
 
 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const {
   return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
 }
 
 const lldb_private::RegisterInfo *
 RegisterInfoPOSIX_arm64::GetRegisterInfo() const {
   return m_register_info_p;
 }
 
 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const {
+  if (IsSVEEnabled())
     return k_num_register_sets;
+  return k_num_register_sets - 1;
 }
 
 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex(
     uint32_t reg_index) const {
-  if (reg_index <= last_gpr)
+  if (reg_index <= gpr_w28)
     return GPRegSet;
-  else if (reg_index <= last_fpr)
+  if (reg_index <= fpu_fpcr)
     return FPRegSet;
+  if (reg_index <= sve_ffr)
+    return SVERegSet;
   return LLDB_INVALID_REGNUM;
 }
 
 const lldb_private::RegisterSet *
 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const {
-  if (set_index < k_num_register_sets)
+  if (set_index < GetRegisterSetCount())
     return &g_reg_sets_arm64[set_index];
-
   return nullptr;
 }
+
+uint32_t
+RegisterInfoPOSIX_arm64::ConfigureVectorRegisterInfos(uint32_t sve_vq) {
+  // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
+  // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
+  // Also if an invalid or previously set vector length is passed to this
+  // function then it will exit immediately with previously set vector length.
+  if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
+    return m_vector_reg_vq;
+
+  // We cannot enable AArch64 only mode if SVE was enabled.
+  if (sve_vq == eVectorQuadwordAArch64 &&
+      m_vector_reg_vq > eVectorQuadwordAArch64)
+    sve_vq = eVectorQuadwordAArch64SVE;
+
+  m_vector_reg_vq = sve_vq;
+
+  if (sve_vq == eVectorQuadwordAArch64) {
+    m_register_info_count =
+        static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
+                              sizeof(g_register_infos_arm64_le[0]));
+    m_register_info_p = g_register_infos_arm64_le;
+
+    return m_vector_reg_vq;
+  }
+
+  m_register_info_count =
+      static_cast<uint32_t>(sizeof(g_register_infos_arm64_sve_le) /
+                            sizeof(g_register_infos_arm64_sve_le[0]));
+
+  std::vector<lldb_private::RegisterInfo> &reg_info_ref =
+      m_per_vq_reg_infos[sve_vq];
+
+  if (reg_info_ref.empty()) {
+    reg_info_ref = llvm::makeArrayRef(g_register_infos_arm64_sve_le,
+                                      m_register_info_count);
+
+    uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
+
+    reg_info_ref[sve_vg].byte_offset = offset;
+    offset += reg_info_ref[sve_vg].byte_size;
+
+    // Update Z registers size and offset
+    uint32_t s_reg_base = fpu_s0;
+    uint32_t d_reg_base = fpu_d0;
+    uint32_t v_reg_base = fpu_v0;
+    uint32_t z_reg_base = sve_z0;
+
+    for (uint32_t index = 0; index < 32; index++) {
+      reg_info_ref[s_reg_base + index].byte_offset = offset;
+      reg_info_ref[d_reg_base + index].byte_offset = offset;
+      reg_info_ref[v_reg_base + index].byte_offset = offset;
+      reg_info_ref[z_reg_base + index].byte_offset = offset;
+
+      reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
+      offset += reg_info_ref[z_reg_base + index].byte_size;
+    }
+
+    // Update P registers and FFR size and offset
+    for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
+      reg_info_ref[it].byte_offset = offset;
+      reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
+      offset += reg_info_ref[it].byte_size;
+    }
+
+    reg_info_ref[fpu_fpsr].byte_offset = offset;
+    reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+  }
+
+  m_register_info_p = reg_info_ref.data();
+  return m_vector_reg_vq;
+}
+
+bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
+  return (sve_z0 <= reg && reg <= sve_z31);
+}
+
+bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
+  return (sve_p0 <= reg && reg <= sve_p15);
+}
+
+bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
+  return sve_vg == reg;
+}
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h

+//===-- RegisterInfos_arm64_sve.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
+
+enum {
+  sve_fpsr = fpu_fpsr,
+  sve_fpcr = fpu_fpcr,
+
+  sve_vg = exc_far,
+
+  sve_z0,
+  sve_z1,
+  sve_z2,
+  sve_z3,
+  sve_z4,
+  sve_z5,
+  sve_z6,
+  sve_z7,
+  sve_z8,
+  sve_z9,
+  sve_z10,
+  sve_z11,
+  sve_z12,
+  sve_z13,
+  sve_z14,
+  sve_z15,
+  sve_z16,
+  sve_z17,
+  sve_z18,
+  sve_z19,
+  sve_z20,
+  sve_z21,
+  sve_z22,
+  sve_z23,
+  sve_z24,
+  sve_z25,
+  sve_z26,
+  sve_z27,
+  sve_z28,
+  sve_z29,
+  sve_z30,
+  sve_z31,
+
+  sve_p0,
+  sve_p1,
+  sve_p2,
+  sve_p3,
+  sve_p4,
+  sve_p5,
+  sve_p6,
+  sve_p7,
+  sve_p8,
+  sve_p9,
+  sve_p10,
+  sve_p11,
+  sve_p12,
+  sve_p13,
+  sve_p14,
+  sve_p15,
+
+  sve_ffr,
+};
+
+#ifndef SVE_OFFSET_VG
+#error SVE_OFFSET_VG must be defined before including this header file
+#endif
+
+static uint32_t g_sve_s0_invalidates[] = {sve_z0, fpu_v0, fpu_d0,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s1_invalidates[] = {sve_z1, fpu_v1, fpu_d1,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s2_invalidates[] = {sve_z2, fpu_v2, fpu_d2,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s3_invalidates[] = {sve_z3, fpu_v3, fpu_d3,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s4_invalidates[] = {sve_z4, fpu_v4, fpu_d4,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s5_invalidates[] = {sve_z5, fpu_v5, fpu_d5,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s6_invalidates[] = {sve_z6, fpu_v6, fpu_d6,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s7_invalidates[] = {sve_z7, fpu_v7, fpu_d7,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s8_invalidates[] = {sve_z8, fpu_v8, fpu_d8,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s9_invalidates[] = {sve_z9, fpu_v9, fpu_d9,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s10_invalidates[] = {sve_z10, fpu_v10, fpu_d10,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s11_invalidates[] = {sve_z11, fpu_v11, fpu_d11,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s12_invalidates[] = {sve_z12, fpu_v12, fpu_d12,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s13_invalidates[] = {sve_z13, fpu_v13, fpu_d13,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s14_invalidates[] = {sve_z14, fpu_v14, fpu_d14,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s15_invalidates[] = {sve_z15, fpu_v15, fpu_d15,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s16_invalidates[] = {sve_z16, fpu_v16, fpu_d16,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s17_invalidates[] = {sve_z17, fpu_v17, fpu_d17,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s18_invalidates[] = {sve_z18, fpu_v18, fpu_d18,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s19_invalidates[] = {sve_z19, fpu_v19, fpu_d19,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s20_invalidates[] = {sve_z20, fpu_v20, fpu_d20,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s21_invalidates[] = {sve_z21, fpu_v21, fpu_d21,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s22_invalidates[] = {sve_z22, fpu_v22, fpu_d22,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s23_invalidates[] = {sve_z23, fpu_v23, fpu_d23,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s24_invalidates[] = {sve_z24, fpu_v24, fpu_d24,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s25_invalidates[] = {sve_z25, fpu_v25, fpu_d25,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s26_invalidates[] = {sve_z26, fpu_v26, fpu_d26,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s27_invalidates[] = {sve_z27, fpu_v27, fpu_d27,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s28_invalidates[] = {sve_z28, fpu_v28, fpu_d28,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s29_invalidates[] = {sve_z29, fpu_v29, fpu_d29,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s30_invalidates[] = {sve_z30, fpu_v30, fpu_d30,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_s31_invalidates[] = {sve_z31, fpu_v31, fpu_d31,
+                                           LLDB_INVALID_REGNUM};
+
+static uint32_t g_sve_d0_invalidates[] = {sve_z0, fpu_v0, fpu_s0,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d1_invalidates[] = {sve_z1, fpu_v1, fpu_s1,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d2_invalidates[] = {sve_z2, fpu_v2, fpu_s2,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d3_invalidates[] = {sve_z3, fpu_v3, fpu_s3,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d4_invalidates[] = {sve_z4, fpu_v4, fpu_s4,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d5_invalidates[] = {sve_z5, fpu_v5, fpu_s5,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d6_invalidates[] = {sve_z6, fpu_v6, fpu_s6,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d7_invalidates[] = {sve_z7, fpu_v7, fpu_s7,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d8_invalidates[] = {sve_z8, fpu_v8, fpu_s8,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d9_invalidates[] = {sve_z9, fpu_v9, fpu_s9,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d10_invalidates[] = {sve_z10, fpu_v10, fpu_s10,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d11_invalidates[] = {sve_z11, fpu_v11, fpu_s11,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d12_invalidates[] = {sve_z12, fpu_v12, fpu_s12,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d13_invalidates[] = {sve_z13, fpu_v13, fpu_s13,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d14_invalidates[] = {sve_z14, fpu_v14, fpu_s14,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d15_invalidates[] = {sve_z15, fpu_v15, fpu_s15,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d16_invalidates[] = {sve_z16, fpu_v16, fpu_s16,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d17_invalidates[] = {sve_z17, fpu_v17, fpu_s17,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d18_invalidates[] = {sve_z18, fpu_v18, fpu_s18,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d19_invalidates[] = {sve_z19, fpu_v19, fpu_s19,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d20_invalidates[] = {sve_z20, fpu_v20, fpu_s20,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d21_invalidates[] = {sve_z21, fpu_v21, fpu_s21,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d22_invalidates[] = {sve_z22, fpu_v22, fpu_s22,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d23_invalidates[] = {sve_z23, fpu_v23, fpu_s23,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d24_invalidates[] = {sve_z24, fpu_v24, fpu_s24,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d25_invalidates[] = {sve_z25, fpu_v25, fpu_s25,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d26_invalidates[] = {sve_z26, fpu_v26, fpu_s26,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d27_invalidates[] = {sve_z27, fpu_v27, fpu_s27,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d28_invalidates[] = {sve_z28, fpu_v28, fpu_s28,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d29_invalidates[] = {sve_z29, fpu_v29, fpu_s29,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d30_invalidates[] = {sve_z30, fpu_v30, fpu_s30,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_d31_invalidates[] = {sve_z31, fpu_v31, fpu_s31,
+                                           LLDB_INVALID_REGNUM};
+
+static uint32_t g_sve_v0_invalidates[] = {sve_z0, fpu_d0, fpu_s0,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v1_invalidates[] = {sve_z1, fpu_d1, fpu_s1,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v2_invalidates[] = {sve_z2, fpu_d2, fpu_s2,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v3_invalidates[] = {sve_z3, fpu_d3, fpu_s3,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v4_invalidates[] = {sve_z4, fpu_d4, fpu_s4,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v5_invalidates[] = {sve_z5, fpu_d5, fpu_s5,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v6_invalidates[] = {sve_z6, fpu_d6, fpu_s6,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v7_invalidates[] = {sve_z7, fpu_d7, fpu_s7,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v8_invalidates[] = {sve_z8, fpu_d8, fpu_s8,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v9_invalidates[] = {sve_z9, fpu_d9, fpu_s9,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v10_invalidates[] = {sve_z10, fpu_d10, fpu_s10,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v11_invalidates[] = {sve_z11, fpu_d11, fpu_s11,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v12_invalidates[] = {sve_z12, fpu_d12, fpu_s12,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v13_invalidates[] = {sve_z13, fpu_d13, fpu_s13,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v14_invalidates[] = {sve_z14, fpu_d14, fpu_s14,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v15_invalidates[] = {sve_z15, fpu_d15, fpu_s15,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v16_invalidates[] = {sve_z16, fpu_d16, fpu_s16,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v17_invalidates[] = {sve_z17, fpu_d17, fpu_s17,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v18_invalidates[] = {sve_z18, fpu_d18, fpu_s18,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v19_invalidates[] = {sve_z19, fpu_d19, fpu_s19,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v20_invalidates[] = {sve_z20, fpu_d20, fpu_s20,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v21_invalidates[] = {sve_z21, fpu_d21, fpu_s21,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v22_invalidates[] = {sve_z22, fpu_d22, fpu_s22,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v23_invalidates[] = {sve_z23, fpu_d23, fpu_s23,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v24_invalidates[] = {sve_z24, fpu_d24, fpu_s24,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v25_invalidates[] = {sve_z25, fpu_d25, fpu_s25,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v26_invalidates[] = {sve_z26, fpu_d26, fpu_s26,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v27_invalidates[] = {sve_z27, fpu_d27, fpu_s27,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v28_invalidates[] = {sve_z28, fpu_d28, fpu_s28,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v29_invalidates[] = {sve_z29, fpu_d29, fpu_s29,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v30_invalidates[] = {sve_z30, fpu_d30, fpu_s30,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_v31_invalidates[] = {sve_z31, fpu_d31, fpu_s31,
+                                           LLDB_INVALID_REGNUM};
+
+static uint32_t g_sve_z0_invalidates[] = {fpu_v0, fpu_d0, fpu_s0,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z1_invalidates[] = {fpu_v1, fpu_d1, fpu_s1,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z2_invalidates[] = {fpu_v2, fpu_d2, fpu_s2,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z3_invalidates[] = {fpu_v3, fpu_d3, fpu_s3,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z4_invalidates[] = {fpu_v4, fpu_d4, fpu_s4,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z5_invalidates[] = {fpu_v5, fpu_d5, fpu_s5,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z6_invalidates[] = {fpu_v6, fpu_d6, fpu_s6,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z7_invalidates[] = {fpu_v7, fpu_d7, fpu_s7,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z8_invalidates[] = {fpu_v8, fpu_d8, fpu_s8,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z9_invalidates[] = {fpu_v9, fpu_d9, fpu_s9,
+                                          LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z10_invalidates[] = {fpu_v10, fpu_d10, fpu_s10,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z11_invalidates[] = {fpu_v11, fpu_d11, fpu_s11,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z12_invalidates[] = {fpu_v12, fpu_d12, fpu_s12,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z13_invalidates[] = {fpu_v13, fpu_d13, fpu_s13,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z14_invalidates[] = {fpu_v14, fpu_d14, fpu_s14,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z15_invalidates[] = {fpu_v15, fpu_d15, fpu_s15,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z16_invalidates[] = {fpu_v16, fpu_d16, fpu_s16,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z17_invalidates[] = {fpu_v17, fpu_d17, fpu_s17,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z18_invalidates[] = {fpu_v18, fpu_d18, fpu_s18,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z19_invalidates[] = {fpu_v19, fpu_d19, fpu_s19,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z20_invalidates[] = {fpu_v20, fpu_d20, fpu_s20,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z21_invalidates[] = {fpu_v21, fpu_d21, fpu_s21,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z22_invalidates[] = {fpu_v22, fpu_d22, fpu_s22,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z23_invalidates[] = {fpu_v23, fpu_d23, fpu_s23,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z24_invalidates[] = {fpu_v24, fpu_d24, fpu_s24,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z25_invalidates[] = {fpu_v25, fpu_d25, fpu_s25,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z26_invalidates[] = {fpu_v26, fpu_d26, fpu_s26,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z27_invalidates[] = {fpu_v27, fpu_d27, fpu_s27,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z28_invalidates[] = {fpu_v28, fpu_d28, fpu_s28,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z29_invalidates[] = {fpu_v29, fpu_d29, fpu_s29,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z30_invalidates[] = {fpu_v30, fpu_d30, fpu_s30,
+                                           LLDB_INVALID_REGNUM};
+static uint32_t g_sve_z31_invalidates[] = {fpu_v31, fpu_d31, fpu_s31,
+                                           LLDB_INVALID_REGNUM};
+
+static uint32_t g_contained_z0[] = {sve_z0, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z1[] = {sve_z1, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z2[] = {sve_z2, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z3[] = {sve_z3, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z4[] = {sve_z4, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z5[] = {sve_z5, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z6[] = {sve_z6, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z7[] = {sve_z7, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z8[] = {sve_z8, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z9[] = {sve_z9, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z10[] = {sve_z10, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z11[] = {sve_z11, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z12[] = {sve_z12, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z13[] = {sve_z13, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z14[] = {sve_z14, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z15[] = {sve_z15, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z16[] = {sve_z16, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z17[] = {sve_z17, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z18[] = {sve_z18, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z19[] = {sve_z19, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z20[] = {sve_z20, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z21[] = {sve_z21, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z22[] = {sve_z22, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z23[] = {sve_z23, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z24[] = {sve_z24, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z25[] = {sve_z25, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z26[] = {sve_z26, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z27[] = {sve_z27, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z28[] = {sve_z28, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z29[] = {sve_z29, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z30[] = {sve_z30, LLDB_INVALID_REGNUM};
+static uint32_t g_contained_z31[] = {sve_z31, LLDB_INVALID_REGNUM};
+
+#define VG_OFFSET_NAME(reg) SVE_OFFSET_VG
+
+#define SVE_REG_KIND(reg) MISC_KIND(reg, sve, LLDB_INVALID_REGNUM)
+#define MISC_VG_KIND(lldb_kind) MISC_KIND(vg, sve, LLDB_INVALID_REGNUM)
+
+// Default offset SVE Z registers and all corresponding pseudo registers
+// ( S, D and V registers) is zero and will be configured during execution.
+
+// Defines sve pseudo vector (V) register with 16-byte size
+#define DEFINE_VREG_SVE(vreg, zreg)                                            \
+  {                                                                            \
+    #vreg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,  \
+        VREG_KIND(vreg), g_contained_##zreg, g_sve_##vreg##_invalidates,       \
+        nullptr, 0                                                             \
+  }
+
+// Defines S and D pseudo registers mapping over corresponding vector register
+#define DEFINE_FPU_PSEUDO_SVE(reg, size, zreg)                                 \
+  {                                                                            \
+    #reg, nullptr, size, 0, lldb::eEncodingIEEE754, lldb::eFormatFloat,        \
+        LLDB_KIND(fpu_##reg), g_contained_##zreg, g_sve_##reg##_invalidates,   \
+        nullptr, 0                                                             \
+  }
+
+// Defines a Z vector register with 16-byte default size
+#define DEFINE_ZREG(reg)                                                       \
+  {                                                                            \
+    #reg, nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,   \
+        SVE_REG_KIND(reg), nullptr, g_sve_##reg##_invalidates, nullptr, 0      \
+  }
+
+// Defines a P vector register with 2-byte default size
+#define DEFINE_PREG(reg)                                                       \
+  {                                                                            \
+    #reg, nullptr, 2, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,    \
+        SVE_REG_KIND(reg), nullptr, nullptr, nullptr, 0                        \
+  }
+
+static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
+    // clang-format off
+    // DEFINE_GPR64(name, GENERIC KIND)
+    DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
+    DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
+    DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
+    DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
+    DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
+    DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
+    DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
+    DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
+    DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
+    DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
+    // DEFINE_GPR64(name, GENERIC KIND)
+    DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
+    DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
+    DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
+    DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
+
+    // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
+    DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
+
+    // DEFINE_GPR32(name, parent name)
+    DEFINE_GPR32(w0, x0),
+    DEFINE_GPR32(w1, x1),
+    DEFINE_GPR32(w2, x2),
+    DEFINE_GPR32(w3, x3),
+    DEFINE_GPR32(w4, x4),
+    DEFINE_GPR32(w5, x5),
+    DEFINE_GPR32(w6, x6),
+    DEFINE_GPR32(w7, x7),
+    DEFINE_GPR32(w8, x8),
+    DEFINE_GPR32(w9, x9),
+    DEFINE_GPR32(w10, x10),
+    DEFINE_GPR32(w11, x11),
+    DEFINE_GPR32(w12, x12),
+    DEFINE_GPR32(w13, x13),
+    DEFINE_GPR32(w14, x14),
+    DEFINE_GPR32(w15, x15),
+    DEFINE_GPR32(w16, x16),
+    DEFINE_GPR32(w17, x17),
+    DEFINE_GPR32(w18, x18),
+    DEFINE_GPR32(w19, x19),
+    DEFINE_GPR32(w20, x20),
+    DEFINE_GPR32(w21, x21),
+    DEFINE_GPR32(w22, x22),
+    DEFINE_GPR32(w23, x23),
+    DEFINE_GPR32(w24, x24),
+    DEFINE_GPR32(w25, x25),
+    DEFINE_GPR32(w26, x26),
+    DEFINE_GPR32(w27, x27),
+    DEFINE_GPR32(w28, x28),
+
+    // DEFINE_VREG_SVE(v register, z register)
+    DEFINE_VREG_SVE(v0, z0),
+    DEFINE_VREG_SVE(v1, z1),
+    DEFINE_VREG_SVE(v2, z2),
+    DEFINE_VREG_SVE(v3, z3),
+    DEFINE_VREG_SVE(v4, z4),
+    DEFINE_VREG_SVE(v5, z5),
+    DEFINE_VREG_SVE(v6, z6),
+    DEFINE_VREG_SVE(v7, z7),
+    DEFINE_VREG_SVE(v8, z8),
+    DEFINE_VREG_SVE(v9, z9),
+    DEFINE_VREG_SVE(v10, z10),
+    DEFINE_VREG_SVE(v11, z11),
+    DEFINE_VREG_SVE(v12, z12),
+    DEFINE_VREG_SVE(v13, z13),
+    DEFINE_VREG_SVE(v14, z14),
+    DEFINE_VREG_SVE(v15, z15),
+    DEFINE_VREG_SVE(v16, z16),
+    DEFINE_VREG_SVE(v17, z17),
+    DEFINE_VREG_SVE(v18, z18),
+    DEFINE_VREG_SVE(v19, z19),
+    DEFINE_VREG_SVE(v20, z20),
+    DEFINE_VREG_SVE(v21, z21),
+    DEFINE_VREG_SVE(v22, z22),
+    DEFINE_VREG_SVE(v23, z23),
+    DEFINE_VREG_SVE(v24, z24),
+    DEFINE_VREG_SVE(v25, z25),
+    DEFINE_VREG_SVE(v26, z26),
+    DEFINE_VREG_SVE(v27, z27),
+    DEFINE_VREG_SVE(v28, z28),
+    DEFINE_VREG_SVE(v29, z29),
+    DEFINE_VREG_SVE(v30, z30),
+    DEFINE_VREG_SVE(v31, z31),
+
+    // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
+    DEFINE_FPU_PSEUDO_SVE(s0, 4, z0),
+    DEFINE_FPU_PSEUDO_SVE(s1, 4, z1),
+    DEFINE_FPU_PSEUDO_SVE(s2, 4, z2),
+    DEFINE_FPU_PSEUDO_SVE(s3, 4, z3),
+    DEFINE_FPU_PSEUDO_SVE(s4, 4, z4),
+    DEFINE_FPU_PSEUDO_SVE(s5, 4, z5),
+    DEFINE_FPU_PSEUDO_SVE(s6, 4, z6),
+    DEFINE_FPU_PSEUDO_SVE(s7, 4, z7),
+    DEFINE_FPU_PSEUDO_SVE(s8, 4, z8),
+    DEFINE_FPU_PSEUDO_SVE(s9, 4, z9),
+    DEFINE_FPU_PSEUDO_SVE(s10, 4, z10),
+    DEFINE_FPU_PSEUDO_SVE(s11, 4, z11),
+    DEFINE_FPU_PSEUDO_SVE(s12, 4, z12),
+    DEFINE_FPU_PSEUDO_SVE(s13, 4, z13),
+    DEFINE_FPU_PSEUDO_SVE(s14, 4, z14),
+    DEFINE_FPU_PSEUDO_SVE(s15, 4, z15),
+    DEFINE_FPU_PSEUDO_SVE(s16, 4, z16),
+    DEFINE_FPU_PSEUDO_SVE(s17, 4, z17),
+    DEFINE_FPU_PSEUDO_SVE(s18, 4, z18),
+    DEFINE_FPU_PSEUDO_SVE(s19, 4, z19),
+    DEFINE_FPU_PSEUDO_SVE(s20, 4, z20),
+    DEFINE_FPU_PSEUDO_SVE(s21, 4, z21),
+    DEFINE_FPU_PSEUDO_SVE(s22, 4, z22),
+    DEFINE_FPU_PSEUDO_SVE(s23, 4, z23),
+    DEFINE_FPU_PSEUDO_SVE(s24, 4, z24),
+    DEFINE_FPU_PSEUDO_SVE(s25, 4, z25),
+    DEFINE_FPU_PSEUDO_SVE(s26, 4, z26),
+    DEFINE_FPU_PSEUDO_SVE(s27, 4, z27),
+    DEFINE_FPU_PSEUDO_SVE(s28, 4, z28),
+    DEFINE_FPU_PSEUDO_SVE(s29, 4, z29),
+    DEFINE_FPU_PSEUDO_SVE(s30, 4, z30),
+    DEFINE_FPU_PSEUDO_SVE(s31, 4, z31),
+
+    DEFINE_FPU_PSEUDO_SVE(d0, 8, z0),
+    DEFINE_FPU_PSEUDO_SVE(d1, 8, z1),
+    DEFINE_FPU_PSEUDO_SVE(d2, 8, z2),
+    DEFINE_FPU_PSEUDO_SVE(d3, 8, z3),
+    DEFINE_FPU_PSEUDO_SVE(d4, 8, z4),
+    DEFINE_FPU_PSEUDO_SVE(d5, 8, z5),
+    DEFINE_FPU_PSEUDO_SVE(d6, 8, z6),
+    DEFINE_FPU_PSEUDO_SVE(d7, 8, z7),
+    DEFINE_FPU_PSEUDO_SVE(d8, 8, z8),
+    DEFINE_FPU_PSEUDO_SVE(d9, 8, z9),
+    DEFINE_FPU_PSEUDO_SVE(d10, 8, z10),
+    DEFINE_FPU_PSEUDO_SVE(d11, 8, z11),
+    DEFINE_FPU_PSEUDO_SVE(d12, 8, z12),
+    DEFINE_FPU_PSEUDO_SVE(d13, 8, z13),
+    DEFINE_FPU_PSEUDO_SVE(d14, 8, z14),
+    DEFINE_FPU_PSEUDO_SVE(d15, 8, z15),
+    DEFINE_FPU_PSEUDO_SVE(d16, 8, z16),
+    DEFINE_FPU_PSEUDO_SVE(d17, 8, z17),
+    DEFINE_FPU_PSEUDO_SVE(d18, 8, z18),
+    DEFINE_FPU_PSEUDO_SVE(d19, 8, z19),
+    DEFINE_FPU_PSEUDO_SVE(d20, 8, z20),
+    DEFINE_FPU_PSEUDO_SVE(d21, 8, z21),
+    DEFINE_FPU_PSEUDO_SVE(d22, 8, z22),
+    DEFINE_FPU_PSEUDO_SVE(d23, 8, z23),
+    DEFINE_FPU_PSEUDO_SVE(d24, 8, z24),
+    DEFINE_FPU_PSEUDO_SVE(d25, 8, z25),
+    DEFINE_FPU_PSEUDO_SVE(d26, 8, z26),
+    DEFINE_FPU_PSEUDO_SVE(d27, 8, z27),
+    DEFINE_FPU_PSEUDO_SVE(d28, 8, z28),
+    DEFINE_FPU_PSEUDO_SVE(d29, 8, z29),
+    DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
+    DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
+
+    // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
+    DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
+    DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
+
+    DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
+    // DEFINE_ZREG(name)
+    DEFINE_ZREG(z0),
+    DEFINE_ZREG(z1),
+    DEFINE_ZREG(z2),
+    DEFINE_ZREG(z3),
+    DEFINE_ZREG(z4),
+    DEFINE_ZREG(z5),
+    DEFINE_ZREG(z6),
+    DEFINE_ZREG(z7),
+    DEFINE_ZREG(z8),
+    DEFINE_ZREG(z9),
+    DEFINE_ZREG(z10),
+    DEFINE_ZREG(z11),
+    DEFINE_ZREG(z12),
+    DEFINE_ZREG(z13),
+    DEFINE_ZREG(z14),
+    DEFINE_ZREG(z15),
+    DEFINE_ZREG(z16),
+    DEFINE_ZREG(z17),
+    DEFINE_ZREG(z18),
+    DEFINE_ZREG(z19),
+    DEFINE_ZREG(z20),
+    DEFINE_ZREG(z21),
+    DEFINE_ZREG(z22),
+    DEFINE_ZREG(z23),
+    DEFINE_ZREG(z24),
+    DEFINE_ZREG(z25),
+    DEFINE_ZREG(z26),
+    DEFINE_ZREG(z27),
+    DEFINE_ZREG(z28),
+    DEFINE_ZREG(z29),
+    DEFINE_ZREG(z30),
+    DEFINE_ZREG(z31),
+
+    // DEFINE_PREG(name)
+    DEFINE_PREG(p0),
+    DEFINE_PREG(p1),
+    DEFINE_PREG(p2),
+    DEFINE_PREG(p3),
+    DEFINE_PREG(p4),
+    DEFINE_PREG(p5),
+    DEFINE_PREG(p6),
+    DEFINE_PREG(p7),
+    DEFINE_PREG(p8),
+    DEFINE_PREG(p9),
+    DEFINE_PREG(p10),
+    DEFINE_PREG(p11),
+    DEFINE_PREG(p12),
+    DEFINE_PREG(p13),
+    DEFINE_PREG(p14),
+    DEFINE_PREG(p15),
+
+    // DEFINE FFR
+    DEFINE_PREG(ffr)
+    // clang-format on
+};
+
+#endif // DECLARE_REGISTER_INFOS_ARM64_SVE_STRUCT

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h

 //===-- RegisterContextPOSIXCore_arm64.h ------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM64_H
 #define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM64_H
 
+#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
 #include "Plugins/Process/Utility/RegisterContextPOSIX_arm64.h"
+
 #include "Plugins/Process/elf-core/RegisterUtilities.h"
 #include "lldb/Utility/DataBufferHeap.h"
 #include "lldb/Utility/DataExtractor.h"
 
 class RegisterContextCorePOSIX_arm64 : public RegisterContextPOSIX_arm64 {
 public:
   RegisterContextCorePOSIX_arm64(
       lldb_private::Thread &thread,
       std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
       const lldb_private::DataExtractor &gpregset,
       llvm::ArrayRef<lldb_private::CoreNote> notes);
 
   ~RegisterContextCorePOSIX_arm64() override;
 
   bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
                     lldb_private::RegisterValue &value) override;
 
   bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
                      const lldb_private::RegisterValue &value) override;
 
   bool ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
 
   bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
 
   bool HardwareSingleStep(bool enable) override;
 
 protected:
   bool ReadGPR() override;
 
   bool ReadFPR() override;
 
   bool WriteGPR() override;
 
   bool WriteFPR() override;
 
 private:
   lldb::DataBufferSP m_gpr_buffer;
   lldb_private::DataExtractor m_gpr;
   lldb_private::DataExtractor m_fpregset;
+  lldb_private::DataExtractor m_sveregset;
+
+  SVEState m_sve_state;
+  uint16_t m_sve_vector_length = 0;
+
+  const uint8_t *GetSVEBuffer(uint64_t offset = 0);
+
+  void ConfigureRegisterContext();
+
+  uint32_t CalculateSVEOffset(const lldb_private::RegisterInfo *reg_info);
+
+  uint64_t GetSVERegVG() { return m_sve_vector_length / 8; }
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM64_H

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

 //===-- RegisterContextPOSIXCore_arm64.cpp --------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "RegisterContextPOSIXCore_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
 
 #include "Plugins/Process/elf-core/RegisterUtilities.h"
 #include "lldb/Target/Thread.h"
 #include "lldb/Utility/RegisterValue.h"
 
 #include <memory>
 
 using namespace lldb_private;
 
 RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64(
     Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
     const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
     : RegisterContextPOSIX_arm64(thread, std::move(register_info)) {
   m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
                                                   gpregset.GetByteSize());
   m_gpr.SetData(m_gpr_buffer);
   m_gpr.SetByteOrder(gpregset.GetByteOrder());
 
   m_fpregset = getRegset(
       notes, m_register_info_up->GetTargetArchitecture().GetTriple(), FPR_Desc);
+
+  m_sveregset =
+      getRegset(notes, m_register_info_up->GetTargetArchitecture().GetTriple(),
+                AARCH64_SVE_Desc);
+
+  ConfigureRegisterContext();
 }
 
 RegisterContextCorePOSIX_arm64::~RegisterContextCorePOSIX_arm64() {}
 
 bool RegisterContextCorePOSIX_arm64::ReadGPR() { return true; }
 
 bool RegisterContextCorePOSIX_arm64::ReadFPR() { return false; }
 
 bool RegisterContextCorePOSIX_arm64::WriteGPR() {
   assert(0);
   return false;
 }
 
 bool RegisterContextCorePOSIX_arm64::WriteFPR() {
   assert(0);
   return false;
 }
 
+const uint8_t *RegisterContextCorePOSIX_arm64::GetSVEBuffer(uint64_t offset) {
+  return m_sveregset.GetDataStart() + offset;
+}
+
+void RegisterContextCorePOSIX_arm64::ConfigureRegisterContext() {
+  if (m_sveregset.GetByteSize() > sizeof(user_sve_header)) {
+    uint64_t sve_header_field_offset = 8;
+    m_sve_vector_length = m_sveregset.GetU16(&sve_header_field_offset);
+    sve_header_field_offset = 12;
+    uint16_t sve_header_flags_field =
+        m_sveregset.GetU16(&sve_header_field_offset);
+    if ((sve_header_flags_field & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD)
+      m_sve_state = SVEState::FPSIMD;
+    else if ((sve_header_flags_field & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE)
+      m_sve_state = SVEState::Full;
+
+    if (sve_vl_valid(m_sve_vector_length))
+      m_register_info_up->ConfigureVectorRegisterInfos(
+          sve_vq_from_vl(m_sve_vector_length));
+    else {
+      m_sve_state = SVEState::Disabled;
+      m_sve_vector_length = 0;
+    }
+  } else
+    m_sve_state = SVEState::Disabled;
+}
+
+uint32_t RegisterContextCorePOSIX_arm64::CalculateSVEOffset(
+    const RegisterInfo *reg_info) {
+  // Start of Z0 data is after GPRs plus 8 bytes of vg register
+  uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
+  if (m_sve_state == SVEState::FPSIMD) {
+    const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+    sve_reg_offset = SVE_PT_FPSIMD_OFFSET + (reg - GetRegNumSVEZ0()) * 16;
+  } else if (m_sve_state == SVEState::Full) {
+    uint32_t sve_z0_offset = GetGPRSize() + 8;
+    sve_reg_offset =
+        SVE_SIG_REGS_OFFSET + reg_info->byte_offset - sve_z0_offset;
+  }
+
+  return sve_reg_offset;
+}
+
 bool RegisterContextCorePOSIX_arm64::ReadRegister(const RegisterInfo *reg_info,
                                                   RegisterValue &value) {
-  lldb::offset_t offset = reg_info->byte_offset;
+  Status error;
+  lldb::offset_t offset;
+
+  offset = reg_info->byte_offset;
   if (offset + reg_info->byte_size <= GetGPRSize()) {
     uint64_t v = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
     if (offset == reg_info->byte_offset + reg_info->byte_size) {
       value = v;
       return true;
     }
   }
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
   if (reg == LLDB_INVALID_REGNUM)
     return false;
 
+  if (IsFPR(reg)) {
+    if (m_sve_state == SVEState::Disabled) {
+      // SVE is disabled take legacy route for FPU register access
       offset -= GetGPRSize();
-  if (IsFPR(reg) && offset + reg_info->byte_size <= GetFPUSize()) {
-    Status error;
+      if (offset < m_fpregset.GetByteSize()) {
         value.SetFromMemoryData(reg_info, m_fpregset.GetDataStart() + offset,
-                            reg_info->byte_size, lldb::eByteOrderLittle, error);
+                                reg_info->byte_size, lldb::eByteOrderLittle,
+                                error);
         return error.Success();
       }
+    } else {
+      // FPSR and FPCR will be located right after Z registers in
+      // SVEState::FPSIMD while in SVEState::Full they will be located at the
+      // end of register data after an alignment correction based on currently
+      // selected vector length.
+      uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
+      if (reg == GetRegNumFPSR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPSR_OFFSET(sve_vq_from_vl(m_sve_vector_length));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16);
+      } else if (reg == GetRegNumFPCR()) {
+        sve_reg_num = reg;
+        if (m_sve_state == SVEState::Full)
+          offset = SVE_PT_SVE_FPCR_OFFSET(sve_vq_from_vl(m_sve_vector_length));
+        else if (m_sve_state == SVEState::FPSIMD)
+          offset = SVE_PT_FPSIMD_OFFSET + (32 * 16) + 4;
+      } else {
+        // Extract SVE Z register value register number for this reg_info
+        if (reg_info->value_regs &&
+            reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
+          sve_reg_num = reg_info->value_regs[0];
+        offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
+      }
+
+      assert(sve_reg_num != LLDB_INVALID_REGNUM);
+      assert(offset < m_sveregset.GetByteSize());
+      value.SetFromMemoryData(reg_info, GetSVEBuffer(offset),
+                              reg_info->byte_size, lldb::eByteOrderLittle,
+                              error);
+    }
+  } else if (IsSVE(reg)) {
+    if (IsSVEVG(reg)) {
+      value = GetSVERegVG();
+      return true;
+    }
 
+    switch (m_sve_state) {
+    case SVEState::FPSIMD: {
+      // In FPSIMD state SVE payload mirrors legacy fpsimd struct and so just
+      // copy 16 bytes of v register to the start of z register. All other
+      // SVE register will be set to zero.
+      uint64_t byte_size = 1;
+      uint8_t zeros = 0;
+      const uint8_t *src = &zeros;
+      if (IsSVEZ(reg)) {
+        byte_size = 16;
+        offset = CalculateSVEOffset(reg_info);
+        assert(offset < m_sveregset.GetByteSize());
+        src = GetSVEBuffer(offset);
+      }
+      value.SetFromMemoryData(reg_info, src, byte_size, lldb::eByteOrderLittle,
+                              error);
+    } break;
+    case SVEState::Full:
+      offset = CalculateSVEOffset(reg_info);
+      assert(offset < m_sveregset.GetByteSize());
+      value.SetFromMemoryData(reg_info, GetSVEBuffer(offset),
+                              reg_info->byte_size, lldb::eByteOrderLittle,
+                              error);
+      break;
+    case SVEState::Disabled:
+    default:
       return false;
     }
+  } else
+    return false;
+
+  return error.Success();
+}
 
 bool RegisterContextCorePOSIX_arm64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {
   return false;
 }
 
 bool RegisterContextCorePOSIX_arm64::WriteRegister(const RegisterInfo *reg_info,
                                                    const RegisterValue &value) {

lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

constexpr RegsetDesc FPR_Desc[] = {
     // The result from FXSAVE is in NT_PRXFPREG for i386 core files
     {llvm::Triple::Linux, llvm::Triple::x86, llvm::ELF::NT_PRXFPREG},
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_FPREGSET},
     {llvm::Triple::NetBSD, llvm::Triple::aarch64, NETBSD::AARCH64::NT_FPREGS},
     {llvm::Triple::NetBSD, llvm::Triple::x86_64, NETBSD::AMD64::NT_FPREGS},
     {llvm::Triple::OpenBSD, llvm::Triple::UnknownArch, OPENBSD::NT_FPREGS},
 };
 
+constexpr RegsetDesc AARCH64_SVE_Desc[] = {
+    {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_SVE},
+};
+
 constexpr RegsetDesc PPC_VMX_Desc[] = {
     {llvm::Triple::FreeBSD, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},
 };
 
 constexpr RegsetDesc PPC_VSX_Desc[] = {
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VSX},
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERUTILITIES_H

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

class LinuxCoreTestCase(TestBase):
 
     _aarch64_regions = 4
     _i386_regions = 4
     _x86_64_regions = 5
     _s390x_regions = 2
     _mips_regions = 5
     _ppc64le_regions = 2
 
-
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("AArch64")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_aarch64(self):
         """Test that lldb can read the process information from an aarch64 linux core file."""
-        self.do_test("linux-aarch64", self._aarch64_pid, self._aarch64_regions, "a.out")
+        self.do_test("linux-aarch64", self._aarch64_pid,
+                     self._aarch64_regions, "a.out")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_i386(self):
         """Test that lldb can read the process information from an i386 linux core file."""
         self.do_test("linux-i386", self._i386_pid, self._i386_regions, "a.out")
 
     @skipIfLLVMTargetMissing("Mips")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_mips_o32(self):
         """Test that lldb can read the process information from an MIPS O32 linux core file."""
         self.do_test("linux-mipsel-gnuabio32", self._mips_o32_pid,
                      self._mips_regions, "linux-mipsel-gn")
 
     @skipIfLLVMTargetMissing("Mips")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_mips_n32(self):
         """Test that lldb can read the process information from an MIPS N32 linux core file """
         self.do_test("linux-mips64el-gnuabin32", self._mips64_n32_pid,
                      self._mips_regions, "linux-mips64el-")
 
     @skipIfLLVMTargetMissing("Mips")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_mips_n64(self):
         """Test that lldb can read the process information from an MIPS N64 linux core file """
         self.do_test("linux-mips64el-gnuabi64", self._mips64_n64_pid,
                      self._mips_regions, "linux-mips64el-")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("PowerPC")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_ppc64le(self):
         """Test that lldb can read the process information from an ppc64le linux core file."""
         self.do_test("linux-ppc64le", self._ppc64le_pid, self._ppc64le_regions,
                      "linux-ppc64le.ou")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_x86_64(self):
         """Test that lldb can read the process information from an x86_64 linux core file."""
         self.do_test("linux-x86_64", self._x86_64_pid, self._x86_64_regions,
                      "a.out")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("SystemZ")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_s390x(self):
         """Test that lldb can read the process information from an s390x linux core file."""
         self.do_test("linux-s390x", self._s390x_pid, self._s390x_regions,
                      "a.out")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_same_pid_running(self):
         """Test that we read the information from the core correctly even if we have a running
         process with the same PID around"""
         exe_file = self.getBuildArtifact("linux-x86_64-pid.out")
         core_file = self.getBuildArtifact("linux-x86_64-pid.core")
         shutil.copyfile("linux-x86_64.out", exe_file)
         shutil.copyfile("linux-x86_64.core", core_file)
         with open(core_file, "r+b") as f:
             # These are offsets into the NT_PRSTATUS and NT_PRPSINFO structures in the note
             # segment of the core file. If you update the file, these offsets may need updating
             # as well. (Notes can be viewed with readelf --notes.)
             for pid_offset in [0x1c4, 0x320]:
                 f.seek(pid_offset)
                 self.assertEqual(
                     struct.unpack(
                         "<I",
                         f.read(4))[0],
                     self._x86_64_pid)
 
                 # We insert our own pid, and make sure the test still
                 # works.
                 f.seek(pid_offset)
                 f.write(struct.pack("<I", os.getpid()))
         self.do_test(self.getBuildArtifact("linux-x86_64-pid"), os.getpid(),
                      self._x86_64_regions, "a.out")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_two_cores_same_pid(self):
         """Test that we handle the situation if we have two core files with the same PID
         around"""
         alttarget = self.dbg.CreateTarget("altmain.out")
         altprocess = alttarget.LoadCore("altmain.core")
         self.assertTrue(altprocess, PROCESS_IS_VALID)
         self.assertEqual(altprocess.GetNumThreads(), 1)
         self.assertEqual(altprocess.GetProcessID(), self._x86_64_pid)
def test_two_cores_same_pid(self):
         F = altprocess.ReadCStringFromMemory(
             altframe.FindVariable("F").GetValueAsUnsigned(), 256, error)
         self.assertTrue(error.Success())
         self.assertEqual(F, "_start")
 
         # without destroying this process, run the test which opens another core file with the
         # same pid
         self.do_test("linux-x86_64", self._x86_64_pid, self._x86_64_regions,
                      "a.out")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
     def test_FPR_SSE(self):
         # check x86_64 core file
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore("linux-fpr_sse_x86_64.core")
def test_FPR_SSE(self):
         values["xmm2"] = "{0x07 0xc2 0x1f 0xd7 0x07 0xc2 0x1f 0xd7 0x07 0xc2 0x1f 0xd7 0x07 0xc2 0x1f 0xd7}"
         values["xmm3"] = "{0xa2 0x20 0x48 0x25 0xa2 0x20 0x48 0x25 0xa2 0x20 0x48 0x25 0xa2 0x20 0x48 0x25}"
         values["xmm4"] = "{0xeb 0x5a 0xa8 0xc4 0xeb 0x5a 0xa8 0xc4 0xeb 0x5a 0xa8 0xc4 0xeb 0x5a 0xa8 0xc4}"
         values["xmm5"] = "{0x49 0x41 0x20 0x0b 0x49 0x41 0x20 0x0b 0x49 0x41 0x20 0x0b 0x49 0x41 0x20 0x0b}"
         values["xmm6"] = "{0xf8 0xf1 0x8b 0x4f 0xf8 0xf1 0x8b 0x4f 0xf8 0xf1 0x8b 0x4f 0xf8 0xf1 0x8b 0x4f}"
         values["xmm7"] = "{0x13 0xf1 0x30 0xcd 0x13 0xf1 0x30 0xcd 0x13 0xf1 0x30 0xcd 0x13 0xf1 0x30 0xcd}"
 
         for regname, value in values.items():
-            self.expect("register read {}".format(regname), substrs=["{} = {}".format(regname, value)])
-
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
 
         # now check i386 core file
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore("linux-fpr_sse_i386.core")
 
         values["fioff"] = "0x080480cc"
 
         for regname, value in values.items():
-            self.expect("register read {}".format(regname), substrs=["{} = {}".format(regname, value)])
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_i386_sysroot(self):
         """Test that lldb can find the exe for an i386 linux core file using the sysroot."""
 
         # Copy linux-i386.out to tmp_sysroot/home/labath/test/a.out (since it was compiled as
         # /home/labath/test/a.out)
-        tmp_sysroot = os.path.join(self.getBuildDir(), "lldb_i386_mock_sysroot")
-        executable = os.path.join(tmp_sysroot, "home", "labath", "test", "a.out")
+        tmp_sysroot = os.path.join(
+            self.getBuildDir(), "lldb_i386_mock_sysroot")
+        executable = os.path.join(
+            tmp_sysroot, "home", "labath", "test", "a.out")
         lldbutil.mkdir_p(os.path.dirname(executable))
         shutil.copyfile("linux-i386.out", executable)
 
         # Set sysroot and load core
-        self.runCmd("platform select remote-linux --sysroot '%s'" % tmp_sysroot)
+        self.runCmd("platform select remote-linux --sysroot '%s'" %
+                    tmp_sysroot)
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore("linux-i386.core")
 
         # Check that we found a.out from the sysroot
         self.check_all(process, self._i386_pid, self._i386_regions, "a.out")
 
         self.dbg.DeleteTarget(target)
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("X86")
     @skipIfWindows
-    @skipIfReproducer # lldb::FileSP used in typemap cannot be instrumented.
+    @skipIfReproducer  # lldb::FileSP used in typemap cannot be instrumented.
     def test_x86_64_sysroot(self):
         """Test that sysroot has more priority then local filesystem."""
 
         # Copy wrong executable to the location outside of sysroot
         exe_outside = os.path.join(self.getBuildDir(), "bin", "a.out")
         lldbutil.mkdir_p(os.path.dirname(exe_outside))
         shutil.copyfile("altmain.out", exe_outside)
 
         # Copy correct executable to the location inside sysroot
         tmp_sysroot = os.path.join(self.getBuildDir(), "mock_sysroot")
-        exe_inside = os.path.join(tmp_sysroot, os.path.relpath(exe_outside, "/"))
+        exe_inside = os.path.join(
+            tmp_sysroot, os.path.relpath(exe_outside, "/"))
         lldbutil.mkdir_p(os.path.dirname(exe_inside))
         shutil.copyfile("linux-x86_64.out", exe_inside)
 
         # Prepare patched core file
         core_file = os.path.join(self.getBuildDir(), "patched.core")
         with open("linux-x86_64.core", "rb") as f:
             core = f.read()
         core = replace_path(core, "/test" * 817 + "/a.out", exe_outside)
         with open(core_file, "wb") as f:
             f.write(core)
 
         # Set sysroot and load core
-        self.runCmd("platform select remote-linux --sysroot '%s'" % tmp_sysroot)
+        self.runCmd("platform select remote-linux --sysroot '%s'" %
+                    tmp_sysroot)
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore(core_file)
 
         # Check that we found executable from the sysroot
         mod_path = str(target.GetModuleAtIndex(0).GetFileSpec())
         self.assertEqual(mod_path, exe_inside)
-        self.check_all(process, self._x86_64_pid, self._x86_64_regions, "a.out")
+        self.check_all(process, self._x86_64_pid,
+                       self._x86_64_regions, "a.out")
 
         self.dbg.DeleteTarget(target)
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("AArch64")
     def test_aarch64_regs(self):
         # check 64 bit ARM core files
         target = self.dbg.CreateTarget(None)
def test_aarch64_regs(self):
         values["d7"] = "5.38269928421123e-315"
         values["d8"] = "1.80107573659442e-226"
         values["d30"] = "0"
         values["d31"] = "1.39804328609529e-76"
         values["fpsr"] = "0x00000000"
         values["fpcr"] = "0x00000000"
 
         for regname, value in values.items():
-            self.expect("register read {}".format(regname), substrs=["{} = {}".format(regname, value)])
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
+
+        self.expect("register read --all")
+
+    @skipIf(triple='^mips')
+    @skipIfLLVMTargetMissing("AArch64")
+    def test_aarch64_sve_regs_fpsimd(self):
+        # check 64 bit ARM core files
+        target = self.dbg.CreateTarget(None)
+        self.assertTrue(target, VALID_TARGET)
+        process = target.LoadCore("linux-aarch64-sve-fpsimd.core")
+
+        values = {}
+        values["x1"] = "0x000000000000002f"
+        values["w1"] = "0x0000002f"
+        values["fp"] = "0x0000ffffcbad8d50"
+        values["lr"] = "0x0000000000400180"
+        values["sp"] = "0x0000ffffcbad8d30"
+        values["pc"] = "0x000000000040014c"
+        values["cpsr"] = "0x00001000"
+        values["v0"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0xe0 0x3f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v1"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0xf8 0x3f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v2"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v3"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v4"] = "{0x00 0x00 0x90 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v5"] = "{0x00 0x00 0xb0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v6"] = "{0x00 0x00 0xd0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v7"] = "{0x00 0x00 0xf0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v8"] = "{0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11}"
+        values["v27"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v28"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v31"] = "{0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30}"
+        values["s2"] = "0"
+        values["s3"] = "0"
+        values["s4"] = "4.5"
+        values["s5"] = "5.5"
+        values["s6"] = "6.5"
+        values["s7"] = "7.5"
+        values["s8"] = "1.14437e-28"
+        values["s30"] = "0"
+        values["s31"] = "6.40969e-10"
+        values["d0"] = "0.5"
+        values["d1"] = "1.5"
+        values["d2"] = "2.5"
+        values["d3"] = "3.5"
+        values["d4"] = "5.35161536149201e-315"
+        values["d5"] = "5.36197666906508e-315"
+        values["d6"] = "5.37233797663815e-315"
+        values["d7"] = "5.38269928421123e-315"
+        values["d8"] = "1.80107573659442e-226"
+        values["d30"] = "0"
+        values["d31"] = "1.39804328609529e-76"
+        values["fpsr"] = "0x00000000"
+        values["fpcr"] = "0x00000000"
+        values["vg"] = "0x0000000000000004"
+        values["z0"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0xe0 0x3f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z1"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0xf8 0x3f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z2"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z3"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z4"] = "{0x00 0x00 0x90 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z5"] = "{0x00 0x00 0xb0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z6"] = "{0x00 0x00 0xd0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z7"] = "{0x00 0x00 0xf0 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z8"] = "{0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z27"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z28"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z31"] = "{0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["p0"] = "{0x00 0x00 0x00 0x00}"
+        values["p1"] = "{0x00 0x00 0x00 0x00}"
+        values["p2"] = "{0x00 0x00 0x00 0x00}"
+        values["p4"] = "{0x00 0x00 0x00 0x00}"
+        values["p3"] = "{0x00 0x00 0x00 0x00}"
+        values["p6"] = "{0x00 0x00 0x00 0x00}"
+        values["p5"] = "{0x00 0x00 0x00 0x00}"
+        values["p7"] = "{0x00 0x00 0x00 0x00}"
+        values["p8"] = "{0x00 0x00 0x00 0x00}"
+        values["p9"] = "{0x00 0x00 0x00 0x00}"
+        values["p11"] = "{0x00 0x00 0x00 0x00}"
+        values["p10"] = "{0x00 0x00 0x00 0x00}"
+        values["p12"] = "{0x00 0x00 0x00 0x00}"
+        values["p13"] = "{0x00 0x00 0x00 0x00}"
+        values["p14"] = "{0x00 0x00 0x00 0x00}"
+        values["p15"] = "{0x00 0x00 0x00 0x00}"
+        values["ffr"] = "{0x00 0x00 0x00 0x00}"
+
+        for regname, value in values.items():
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
+
+        self.expect("register read --all")
+
+    @skipIf(triple='^mips')
+    @skipIfLLVMTargetMissing("AArch64")
+    def test_aarch64_sve_regs_full(self):
+        # check 64 bit ARM core files
+        target = self.dbg.CreateTarget(None)
+        self.assertTrue(target, VALID_TARGET)
+        process = target.LoadCore("linux-aarch64-sve-full.core")
+
+        values = {}
+        values["fp"] = "0x0000fffffc1ff4f0"
+        values["lr"] = "0x0000000000400170"
+        values["sp"] = "0x0000fffffc1ff4d0"
+        values["pc"] = "0x000000000040013c"
+        values["v0"] = "{0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40}"
+        values["v1"] = "{0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41}"
+        values["v2"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["v3"] = "{0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41}"
+        values["s0"] = "7.5"
+        values["s1"] = "11.5"
+        values["s2"] = "0"
+        values["s3"] = "15.5"
+        values["d0"] = "65536.0158538818"
+        values["d1"] = "1572864.25476074"
+        values["d2"] = "0"
+        values["d3"] = "25165828.0917969"
+        values["vg"] = "0x0000000000000004"
+        values["z0"] = "{0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40 0x00 0x00 0xf0 0x40}"
+        values["z1"] = "{0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41 0x00 0x00 0x38 0x41}"
+        values["z2"] = "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
+        values["z3"] = "{0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41 0x00 0x00 0x78 0x41}"
+        values["p0"] = "{0x11 0x11 0x11 0x11}"
+        values["p1"] = "{0x11 0x11 0x11 0x11}"
+        values["p2"] = "{0x00 0x00 0x00 0x00}"
+        values["p3"] = "{0x11 0x11 0x11 0x11}"
+        values["p4"] = "{0x00 0x00 0x00 0x00}"
+
+        for regname, value in values.items():
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
 
         self.expect("register read --all")
 
     @skipIf(triple='^mips')
     @skipIfLLVMTargetMissing("ARM")
     def test_arm_core(self):
         # check 32 bit ARM core file
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
         process = target.LoadCore("linux-arm.core")
 
         values = {}
         values["r0"] = "0x00000000"
def test_arm_core(self):
         values["r10"] = "0x0000000a"
         values["r11"] = "0x0000000b"
         values["r12"] = "0x0000000c"
         values["sp"] = "0x0000000d"
         values["lr"] = "0x0000000e"
         values["pc"] = "0x0000000f"
         values["cpsr"] = "0x00000010"
         for regname, value in values.items():
-            self.expect("register read {}".format(regname), substrs=["{} = {}".format(regname, value)])
+            self.expect("register read {}".format(regname),
+                        substrs=["{} = {}".format(regname, value)])
 
         self.expect("register read --all")
 
     def check_memory_regions(self, process, region_count):
         region_list = process.GetMemoryRegions()
         self.assertEqual(region_list.GetSize(), region_count)
 
         region = lldb.SBMemoryRegionInfo()
class LinuxCoreTestCase(TestBase):
     def do_test(self, filename, pid, region_count, thread_name):
         target = self.dbg.CreateTarget(filename + ".out")
         process = target.LoadCore(filename + ".core")
 
         self.check_all(process, pid, region_count, thread_name)
 
         self.dbg.DeleteTarget(target)
 
+
 def replace_path(binary, replace_from, replace_to):
     src = replace_from.encode()
     dst = replace_to.encode()
     dst += b"\0" * (len(src) - len(dst))
     return binary.replace(src, dst)

lldb/test/API/functionalities/postmortem/elf-core/linux-aarch64-sve.c

+// compile with -march=armv8-a+sve on compatible aarch64 compiler
+// linux-aarch64-sve.core was generated by: aarch64-linux-gnu-gcc-8
+// commandline: -march=armv8-a+sve -nostdlib -static -g linux-aarch64-sve.c
+static void bar(char *boom) {
+  char F = 'b';
+  asm volatile("ptrue p0.s\n\t");
+  asm volatile("fcpy  z0.s, p0/m, #7.5\n\t");
+  asm volatile("ptrue p1.s\n\t");
+  asm volatile("fcpy  z1.s, p1/m, #11.5\n\t");
+  asm volatile("ptrue p3.s\n\t");
+  asm volatile("fcpy  z3.s, p3/m, #15.5\n\t");
+
+  *boom = 47; // Frame bar
+}
+
+static void foo(char *boom, void (*boomer)(char *)) {
+  char F = 'f';
+  boomer(boom); // Frame foo
+}
+
+void _start(void) {
+  char F = '_';
+  foo(0, bar); // Frame _start
+}