[WebAssembly] Renumber SIMD opcodes

[tlively]

Summary

As described in https://github.com/WebAssembly/simd/pull/209. This is
the final reorganization of the SIMD opcode space before
standardization. It has been landed in concert with corresponding
changes in other projects in the WebAssembly SIMD ecosystem.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

186

So these have been decided not be included in the spec?

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

88

We don't need this anymore?

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

479

Ditto

[tlively]

• Remove i64x2 conversion ops in clang as well

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

186

That's correct

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

88

No, these instructions have been removed because they are no longer in the proposal and there is not a great set of opcodes to assign them to. These test functions are still here to test that the compiler doesn't crash, but their contents aren't important to test here. The instructions get scalarized and our normal complicated lowering of fp-to-int gets applied, so we end up with a very large amount of code in this case.

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

479

These LLVM intrinsics are no longer supported, so the entire function is removed.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 
 TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, "V16cV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16cV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_widen_low_s_i16x8_i8x16, "V8sV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_widen_high_s_i16x8_i8x16, "V8sV16c", "nc", "simd128")

clang/lib/CodeGen/CGBuiltin.cpp

case WebAssembly::BI__builtin_wasm_trunc_u_i64_f64: {
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_trunc_unsigned,
                                         {ResT, Src->getType()});
     return Builder.CreateCall(Callee, {Src});
   }
   case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i32_f32:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i32_f64:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i64_f32:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i64_f64:
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i32x4_f32x4:
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i64x2_f64x2: {
+  case WebAssembly::BI__builtin_wasm_trunc_saturate_s_i32x4_f32x4: {
     Value *Src = EmitScalarExpr(E->getArg(0));
     llvm::Type *ResT = ConvertType(E->getType());
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_trunc_saturate_signed,
                                      {ResT, Src->getType()});
     return Builder.CreateCall(Callee, {Src});
   }
   case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i32_f32:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i32_f64:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i64_f32:
   case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i64_f64:
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i32x4_f32x4:
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i64x2_f64x2: {
+  case WebAssembly::BI__builtin_wasm_trunc_saturate_u_i32x4_f32x4: {
     Value *Src = EmitScalarExpr(E->getArg(0));
     llvm::Type *ResT = ConvertType(E->getType());
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_trunc_saturate_unsigned,
                                      {ResT, Src->getType()});
     return Builder.CreateCall(Callee, {Src});
   }
   case WebAssembly::BI__builtin_wasm_min_f32:
   case WebAssembly::BI__builtin_wasm_min_f64:

clang/lib/Headers/wasm_simd128.h

wasm_i32x4_trunc_saturate_f32x4(v128_t __a) {
   return (v128_t)__builtin_wasm_trunc_saturate_s_i32x4_f32x4((__f32x4)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u32x4_trunc_saturate_f32x4(v128_t __a) {
   return (v128_t)__builtin_wasm_trunc_saturate_u_i32x4_f32x4((__f32x4)__a);
 }
 
-#ifdef __wasm_unimplemented_simd128__
-
-static __inline__ v128_t __DEFAULT_FN_ATTRS
-wasm_i64x2_trunc_saturate_f64x2(v128_t __a) {
-  return (v128_t)__builtin_wasm_trunc_saturate_s_i64x2_f64x2((__f64x2)__a);
-}
-
-static __inline__ v128_t __DEFAULT_FN_ATTRS
-wasm_u64x2_trunc_saturate_f64x2(v128_t __a) {
-  return (v128_t)__builtin_wasm_trunc_saturate_s_i64x2_f64x2((__f64x2)__a);
-}
-
-#endif // __wasm_unimplemented_simd128__
-
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_f32x4_convert_i32x4(v128_t __a) {
   return (v128_t) __builtin_convertvector((__i32x4)__a, __f32x4);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_f32x4_convert_u32x4(v128_t __a) {
   return (v128_t) __builtin_convertvector((__u32x4)__a, __f32x4);
 }
 
-#ifdef __wasm_unimplemented_simd128__
-
-static __inline__ v128_t __DEFAULT_FN_ATTRS
-wasm_f64x2_convert_i64x2(v128_t __a) {
-  return (v128_t) __builtin_convertvector((__i64x2)__a, __f64x2);
-}
-
-static __inline__ v128_t __DEFAULT_FN_ATTRS
-wasm_f64x2_convert_u64x2(v128_t __a) {
-  return (v128_t) __builtin_convertvector((__u64x2)__a, __f64x2);
-}
-
-#endif // __wasm_unimplemented_simd128__
-
 #define wasm_v8x16_shuffle(__a, __b, __c0, __c1, __c2, __c3, __c4, __c5, __c6, \
                            __c7, __c8, __c9, __c10, __c11, __c12, __c13,       \
                            __c14, __c15)                                       \
   ((v128_t)(__builtin_shufflevector(                                           \
       (__u8x16)(__a), (__u8x16)(__b), __c0, __c1, __c2, __c3, __c4, __c5,      \
       __c6, __c7, __c8, __c9, __c10, __c11, __c12, __c13, __c14, __c15)))
 
 #define wasm_v16x8_shuffle(__a, __b, __c0, __c1, __c2, __c3, __c4, __c5, __c6, \

clang/test/CodeGen/builtins-wasm.c

 }
 
 i32x4 trunc_saturate_u_i32x4_f32x4(f32x4 f) {
   return __builtin_wasm_trunc_saturate_u_i32x4_f32x4(f);
   // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %f)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i64x2 trunc_saturate_s_i64x2_f64x2(f64x2 f) {
-  return __builtin_wasm_trunc_saturate_s_i64x2_f64x2(f);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double> %f)
-  // WEBASSEMBLY-NEXT: ret
-}
-
-i64x2 trunc_saturate_u_i64x2_f64x2(f64x2 f) {
-  return __builtin_wasm_trunc_saturate_u_i64x2_f64x2(f);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %f)
-  // WEBASSEMBLY-NEXT: ret
-}
-
 i8x16 narrow_s_i8x16_i16x8(i16x8 low, i16x8 high) {
   return __builtin_wasm_narrow_s_i8x16_i16x8(low, high);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %low, <8 x i16> %high)
   // WEBASSEMBLY: ret
 }
 
 i8x16 narrow_u_i8x16_i16x8(i16x8 low, i16x8 high) {

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
       for (auto T : {MVT::v4f32, MVT::v2f64})
         setOperationAction(Op, T, Expand);
 
     // Expand operations not supported for i64x2 vectors
     for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
       setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
 
     // 64x2 conversions are not in the spec
-    if (!Subtarget->hasUnimplementedSIMD128())
-      for (auto Op :
-           {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
-        for (auto T : {MVT::v2i64, MVT::v2f64})
-          setOperationAction(Op, T, Expand);
   }
 
   // As a special case, these operators use the type to mean the type to
   // sign-extend from.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   if (!Subtarget->hasSignExt()) {
     // Sign extends are legal only when extending a vector extract
     auto Action = Subtarget->hasSIMD128() ? Custom : Expand;

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

let mayLoad = 1, UseNamedOperandTable = 1,
       Predicates = [HasUnimplementedSIMD128] in
   defm LOAD_SPLAT_#vec :
     SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
            vec#".load_splat\t$dst, ${off}(${addr})$p2align",
            vec#".load_splat\t$off$p2align", simdop>;
 }
 
-defm "" : SIMDLoadSplat<"v8x16", 194>;
-defm "" : SIMDLoadSplat<"v16x8", 195>;
-defm "" : SIMDLoadSplat<"v32x4", 196>;
-defm "" : SIMDLoadSplat<"v64x2", 197>;
+defm "" : SIMDLoadSplat<"v8x16", 7>;
+defm "" : SIMDLoadSplat<"v16x8", 8>;
+defm "" : SIMDLoadSplat<"v32x4", 9>;
+defm "" : SIMDLoadSplat<"v64x2", 10>;
 
 def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
 def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
 
 let Predicates = [HasUnimplementedSIMD128] in
 foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
   defm LOAD_EXTEND_U_#vec_t :
     SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
            name#"_u\t$dst, ${off}(${addr})$p2align",
            name#"_u\t$off$p2align", !add(simdop, 1)>;
   }
 }
 
-defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 210>;
-defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>;
-defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 214>;
+defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 1>;
+defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 3>;
+defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 5>;
 
 let Predicates = [HasUnimplementedSIMD128] in
 foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
 foreach exts = [["sextloadv", "_S"],
                 ["zextloadv", "_U"],
                 ["extloadv", "_U"]] in {
 def : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]),
                       !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;

 
 
 // Store: v128.store
 let mayStore = 1, UseNamedOperandTable = 1 in
 defm STORE_V128 :
   SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
          (outs), (ins P2Align:$p2align, offset32_op:$off), [],
          "v128.store\t${off}(${addr})$p2align, $vec",
-         "v128.store\t$off$p2align", 1>;
+         "v128.store\t$off$p2align", 11>;
 
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
 def : StorePatNoOffset<vec_t, store, STORE_V128>;
 def : StorePatImmOff<vec_t, store, regPlusImm, STORE_V128>;
 def : StorePatImmOff<vec_t, store, or_is_add, STORE_V128>;
 def : StorePatOffsetOnly<vec_t, store, STORE_V128>;
 def : StorePatGlobalAddrOffOnly<vec_t, store, STORE_V128>;
 }
 
 //===----------------------------------------------------------------------===//
 // Constructing SIMD values
 //===----------------------------------------------------------------------===//
 
 // Constant: v128.const
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
   let isMoveImm = 1, isReMaterializable = 1,
       Predicates = [HasUnimplementedSIMD128] in
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
-                                  "v128.const\t"#args, 2>;
+                                  "v128.const\t"#args, 12>;
 }
 
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,
SIMD_I<(outs V128:$dst),
            vec_i8imm_op:$mE, vec_i8imm_op:$mF),
          [],
          "v8x16.shuffle\t$dst, $x, $y, "#
            "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
            "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
          "v8x16.shuffle\t"#
            "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
            "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
-         3>;
+         13>;
 
 // Shuffles after custom lowering
 def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
 def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),

 // Swizzle lanes: v8x16.swizzle
 def wasm_swizzle_t : SDTypeProfile<1, 2, []>;
 def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
 let Predicates = [HasUnimplementedSIMD128] in
 defm SWIZZLE :
   SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
          [(set (v16i8 V128:$dst),
            (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
-         "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 192>;
+         "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>;
 
 def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
           (SWIZZLE V128:$src, V128:$mask)>;
 
 // Create vector with identical lanes: splat
 def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
 def splat4 : PatFrag<(ops node:$x), (build_vector
                        node:$x, node:$x, node:$x, node:$x)>;
multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
                  PatFrag splat_pat, bits<32> simdop> {
   // Prefer splats over v128.const for const splats (65 is lowest that works)
   let AddedComplexity = 65 in
   defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
                              [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
                              vec#".splat\t$dst, $x", vec#".splat", simdop>;
 }
 
-defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
-defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
-defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
-defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
-defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
-defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
+defm "" : Splat<v16i8, "i8x16", I32, splat16, 15>;
+defm "" : Splat<v8i16, "i16x8", I32, splat8, 16>;
+defm "" : Splat<v4i32, "i32x4", I32, splat4, 17>;
+defm "" : Splat<v2i64, "i64x2", I64, splat2, 18>;
+defm "" : Splat<v4f32, "f32x4", F32, splat4, 19>;
+defm "" : Splat<v2f64, "f64x2", F64, splat2, 20>;
 
 // scalar_to_vector leaves high lanes undefined, so can be a splat
 class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
                      WebAssemblyRegClass reg_t> :
   Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
       (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
 
 def : ScalarSplatPat<v16i8, i32, I32>;
multiclass ExtractLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
                        bits<32> simdop, string suffix = ""> {
   defm EXTRACT_LANE_#vec_t#suffix :
       SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
              (outs), (ins vec_i8imm_op:$idx), [],
              vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
              vec#".extract_lane"#suffix#"\t$idx", simdop>;
 }
 
-defm "" : ExtractLane<v16i8, "i8x16", I32, 5, "_s">;
-defm "" : ExtractLane<v16i8, "i8x16", I32, 6, "_u">;
-defm "" : ExtractLane<v8i16, "i16x8", I32, 9, "_s">;
-defm "" : ExtractLane<v8i16, "i16x8", I32, 10, "_u">;
-defm "" : ExtractLane<v4i32, "i32x4", I32, 13>;
-defm "" : ExtractLane<v2i64, "i64x2", I64, 16>;
-defm "" : ExtractLane<v4f32, "f32x4", F32, 19>;
-defm "" : ExtractLane<v2f64, "f64x2", F64, 22>;
+defm "" : ExtractLane<v16i8, "i8x16", I32, 21, "_s">;
+defm "" : ExtractLane<v16i8, "i8x16", I32, 22, "_u">;
+defm "" : ExtractLane<v8i16, "i16x8", I32, 24, "_s">;
+defm "" : ExtractLane<v8i16, "i16x8", I32, 25, "_u">;
+defm "" : ExtractLane<v4i32, "i32x4", I32, 27>;
+defm "" : ExtractLane<v2i64, "i64x2", I64, 29>;
+defm "" : ExtractLane<v4f32, "f32x4", F32, 31>;
+defm "" : ExtractLane<v2f64, "f64x2", F64, 33>;
 
 def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
           (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>;
 def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
           (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>;
 def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
           (EXTRACT_LANE_v4i32 V128:$vec, imm:$idx)>;
 def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
defm REPLACE_LANE_#vec_t :
       SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
              (outs), (ins vec_i8imm_op:$idx),
              [(set V128:$dst, (vector_insert
                (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
              vec#".replace_lane\t$dst, $vec, $idx, $x",
              vec#".replace_lane\t$idx", simdop>;
 }
 
-defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>;
-defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>;
-defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>;
-defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>;
-defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
-defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>;
+defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 23>;
+defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 26>;
+defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 28>;
+defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 30>;
+defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 32>;
+defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 34>;
 
 // Lower undef lane indices to zero
 def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
           (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
 def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
           (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
 def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
           (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;

 multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
   defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
   defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
                           !add(baseInst, 6)>;
 }
 
 // Equality: eq
 let isCommutable = 1 in {
-defm EQ : SIMDConditionInt<"eq", SETEQ, 24>;
-defm EQ : SIMDConditionFP<"eq", SETOEQ, 64>;
+defm EQ : SIMDConditionInt<"eq", SETEQ, 35>;
+defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>;
 } // isCommutable = 1
 
 // Non-equality: ne
 let isCommutable = 1 in {
-defm NE : SIMDConditionInt<"ne", SETNE, 25>;
-defm NE : SIMDConditionFP<"ne", SETUNE, 65>;
+defm NE : SIMDConditionInt<"ne", SETNE, 36>;
+defm NE : SIMDConditionFP<"ne", SETUNE, 66>;
 } // isCommutable = 1
 
 // Less than: lt_s / lt_u / lt
-defm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>;
-defm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>;
-defm LT : SIMDConditionFP<"lt", SETOLT, 66>;
+defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>;
+defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>;
+defm LT : SIMDConditionFP<"lt", SETOLT, 67>;
 
 // Greater than: gt_s / gt_u / gt
-defm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>;
-defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>;
-defm GT : SIMDConditionFP<"gt", SETOGT, 67>;
+defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>;
+defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>;
+defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
 
 // Less than or equal: le_s / le_u / le
-defm LE_S : SIMDConditionInt<"le_s", SETLE, 30>;
-defm LE_U : SIMDConditionInt<"le_u", SETULE, 31>;
-defm LE : SIMDConditionFP<"le", SETOLE, 68>;
+defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>;
+defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>;
+defm LE : SIMDConditionFP<"le", SETOLE, 69>;
 
 // Greater than or equal: ge_s / ge_u / ge
-defm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>;
-defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>;
-defm GE : SIMDConditionFP<"ge", SETOGE, 69>;
+defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>;
+defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>;
+defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
 
 // Lower float comparisons that don't care about NaN to standard WebAssembly
 // float comparisons. These instructions are generated with nnan and in the
 // target-independent expansion of unordered comparisons and ordered ne.
 foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32],
                  [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in
 def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
           (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
                         [(set (vec_t V128:$dst),
                           (vec_t (node (vec_t V128:$vec)))
                         )],
                         vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
 }
 
 // Bitwise logic: v128.not
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
-defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
+defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 77>;
 
-// Bitwise logic: v128.and / v128.or / v128.xor
+// Bitwise logic: v128.and / v128.andnot / v128.or / v128.xor
 let isCommutable = 1 in {
-defm AND : SIMDBitwise<and, "and", 77>;
-defm OR : SIMDBitwise<or, "or", 78>;
-defm XOR : SIMDBitwise<xor, "xor", 79>;
+defm AND : SIMDBitwise<and, "and", 78>;
+defm OR : SIMDBitwise<or, "or", 80>;
+defm XOR : SIMDBitwise<xor, "xor", 81>;
 } // isCommutable = 1
 
 // Bitwise logic: v128.andnot
 def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>;
 let Predicates = [HasUnimplementedSIMD128] in
-defm ANDNOT : SIMDBitwise<andnot, "andnot", 216>;
+defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>;
 
 // Bitwise select: v128.bitselect
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
   defm BITSELECT_#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
            [(set (vec_t V128:$dst),
              (vec_t (int_wasm_bitselect
                (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
              ))
            )],
-           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
+           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>;
 
 // Bitselect is equivalent to (c & v1) | (~c & v2)
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
   def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
               (and (vnot V128:$c), (vec_t V128:$v2)))),
             (!cast<Instruction>("BITSELECT_"#vec_t)
               V128:$v1, V128:$v2, V128:$c)>;
 
 //===----------------------------------------------------------------------===//
 // Integer unary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
-  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
-  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
-  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
+  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
+  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
+  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
 }
 
 multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
                          bits<32> simdop> {
   defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
                         [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
                         vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
 }
 
 multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
   defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
-  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
-  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
-  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
+  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 32)>;
+  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 64)>;
+  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 96)>;
 }
 
 // Integer vector negation
 def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
 
 // Integer absolute value: abs
-defm ABS : SIMDUnary<v16i8, "i8x16", abs, "abs", 225>;
-defm ABS : SIMDUnary<v8i16, "i16x8", abs, "abs", 226>;
-defm ABS : SIMDUnary<v4i32, "i32x4", abs, "abs", 227>;
+defm ABS : SIMDUnaryInt<abs, "abs", 96>;
 
 // Integer negation: neg
-defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
+defm NEG : SIMDUnaryInt<ivneg, "neg", 97>;
 
 // Any lane true: any_true
-defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
+defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>;
 
 // All lanes true: all_true
-defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;
+defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>;
 
 // Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
 // can be folded out
 foreach reduction =
   [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
 foreach ty = [v16i8, v8i16, v4i32, v2i64] in {
 def : Pat<(i32 (and
             (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),

 multiclass SIMDBitmask<ValueType vec_t, string vec, bits<32> simdop> {
   defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
                          [(set I32:$dst,
                            (i32 (int_wasm_bitmask (vec_t V128:$vec)))
                          )],
                          vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>;
 }
 
-defm BITMASK : SIMDBitmask<v16i8, "i8x16", 228>;
-defm BITMASK : SIMDBitmask<v8i16, "i16x8", 229>;
-defm BITMASK : SIMDBitmask<v4i32, "i32x4", 230>;
+defm BITMASK : SIMDBitmask<v16i8, "i8x16", 100>;
+defm BITMASK : SIMDBitmask<v8i16, "i16x8", 132>;
+defm BITMASK : SIMDBitmask<v4i32, "i32x4", 164>;
 
 //===----------------------------------------------------------------------===//
 // Bit shifts
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
                      string name, bits<32> simdop> {
   defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
                         (outs), (ins),
                         [(set (vec_t V128:$dst),
                           (node V128:$vec, (vec_t shift_vec)))],
                         vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
 }
 
 multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
   defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
-                      !add(baseInst, 17)>;
+                      !add(baseInst, 32)>;
   defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
-                      !add(baseInst, 34)>;
+                      !add(baseInst, 64)>;
   defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
-                      name, !add(baseInst, 51)>;
+                      name, !add(baseInst, 96)>;
 }
 
 // Left shift by scalar: shl
-defm SHL : SIMDShiftInt<shl, "shl", 84>;
+defm SHL : SIMDShiftInt<shl, "shl", 107>;
 
 // Right shift by scalar: shr_s / shr_u
-defm SHR_S : SIMDShiftInt<sra, "shr_s", 85>;
-defm SHR_U : SIMDShiftInt<srl, "shr_u", 86>;
+defm SHR_S : SIMDShiftInt<sra, "shr_s", 108>;
+defm SHR_U : SIMDShiftInt<srl, "shr_u", 109>;
 
 // Truncate i64 shift operands to i32s, except if they are already i32s
 foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in {
 def : Pat<(v2i64 (shifts[0]
             (v2i64 V128:$vec),
             (v2i64 (splat2 (i64 (sext I32:$x))))
           )),
           (v2i64 (shifts[1] (v2i64 V128:$vec), (i32 I32:$x)))>;
def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
           (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
 
 //===----------------------------------------------------------------------===//
 // Integer binary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
-  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
+  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
 }
 
 multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
-  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
+  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
 }
 
 multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
-  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
+  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
 }
 
 // Integer addition: add / add_saturate_s / add_saturate_u
 let isCommutable = 1 in {
-defm ADD : SIMDBinaryInt<add, "add", 87>;
-defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>;
-defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>;
+defm ADD : SIMDBinaryInt<add, "add", 110>;
+defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>;
+defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>;
 } // isCommutable = 1
 
 // Integer subtraction: sub / sub_saturate_s / sub_saturate_u
-defm SUB : SIMDBinaryInt<sub, "sub", 90>;
+defm SUB : SIMDBinaryInt<sub, "sub", 113>;
 defm SUB_SAT_S :
-  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>;
+  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>;
 defm SUB_SAT_U :
-  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
+  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>;
 
 // Integer multiplication: mul
 let isCommutable = 1 in
-defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
+defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 117>;
 
 // Integer min_s / min_u / max_s / max_u
 let isCommutable = 1 in {
-defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 94>;
-defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 95>;
-defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 96>;
-defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 97>;
+defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>;
+defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>;
+defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>;
+defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>;
 } // isCommutable = 1
 
 // Integer unsigned rounding average: avgr_u
 let isCommutable = 1 in {
-defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 217>;
-defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 218>;
+defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 123>;
+defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 155>;
 }
 
 def add_nuw : PatFrag<(ops node:$lhs, node:$rhs),
                       (add node:$lhs, node:$rhs),
                       "return N->getFlags().hasNoUnsignedWrap();">;
 
 foreach nodes = [[v16i8, splat16], [v8i16, splat8]] in
 def : Pat<(srl
             (add_nuw
               (add_nuw (nodes[0] V128:$lhs), (nodes[0] V128:$rhs)),
               (nodes[1] (i32 1))
             ),
             (nodes[0] (nodes[1] (i32 1)))
           ),
           (!cast<NI>("AVGR_U_"#nodes[0]) V128:$lhs, V128:$rhs)>;
 
 // Widening dot product: i32x4.dot_i16x8_s
 let isCommutable = 1 in
 defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
                   [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))],
                   "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s",
-                  219>;
+                  180>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point unary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
-  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
+  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 12)>;
 }
 
 // Absolute value: abs
-defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
+defm ABS : SIMDUnaryFP<fabs, "abs", 224>;
 
 // Negation: neg
-defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
+defm NEG : SIMDUnaryFP<fneg, "neg", 225>;
 
 // Square root: sqrt
-defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
+defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point binary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
-  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
+  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 12)>;
 }
 
 // Addition: add
 let isCommutable = 1 in
-defm ADD : SIMDBinaryFP<fadd, "add", 154>;
+defm ADD : SIMDBinaryFP<fadd, "add", 228>;
 
 // Subtraction: sub
-defm SUB : SIMDBinaryFP<fsub, "sub", 155>;
+defm SUB : SIMDBinaryFP<fsub, "sub", 229>;
 
 // Multiplication: mul
 let isCommutable = 1 in
-defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
+defm MUL : SIMDBinaryFP<fmul, "mul", 230>;
 
 // Division: div
-defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
+defm DIV : SIMDBinaryFP<fdiv, "div", 231>;
 
 // NaN-propagating minimum: min
-defm MIN : SIMDBinaryFP<fminimum, "min", 158>;
+defm MIN : SIMDBinaryFP<fminimum, "min", 232>;
 
 // NaN-propagating maximum: max
-defm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
+defm MAX : SIMDBinaryFP<fmaximum, "max", 233>;
 
 //===----------------------------------------------------------------------===//
 // Conversions
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
                        string name, bits<32> simdop> {
   defm op#_#vec_t#_#arg_t :
     SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
            [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
            name#"\t$dst, $vec", name, simdop>;
 }
 
-// Integer to floating point: convert
-defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
-defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
-
-let Predicates = [HasUnimplementedSIMD128] in {
-defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
-defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
-}
-
 // Floating point to integer with saturation: trunc_sat
-defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
-defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 248>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 249>;
 
-let Predicates = [HasUnimplementedSIMD128] in {
-defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
-defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
-}
+// Integer to floating point: convert
+defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 250>;
+defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 251>;
 
 // Widening operations
 multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
                      bits<32> baseInst> {
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed,
                         vec#".widen_low_"#arg#"_s", baseInst>;
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed,
                         vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned,
                         vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>;
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned,
                         vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>;
 }
 
-defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 202>;
-defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 206>;
+defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 135>;
+defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 167>;
 
 // Narrowing operations
 multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
                       bits<32> baseInst> {
   defm NARROW_S_#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
            [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
              (arg_t V128:$low), (arg_t V128:$high))))],
            vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
            baseInst>;
   defm NARROW_U_#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
            [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
              (arg_t V128:$low), (arg_t V128:$high))))],
            vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
            !add(baseInst, 1)>;
 }
 
-defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 198>;
-defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 200>;
+defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 101>;
+defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 133>;
 
 // Lower llvm.wasm.trunc.saturate.* to saturating instructions
 def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
           (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
 def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
           (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
-def : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))),
-          (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>;
-def : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))),
-          (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>;
 
 // Bitcasts are nops
 // Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
 foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
 foreach t2 = !foldl(
   []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
   acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
     acc, !listconcat(acc, [cur])
multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> baseInst> {
   defm QFMS_#vec_t :
     SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
            (outs), (ins),
            [(set (vec_t V128:$dst),
              (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
            vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", !add(baseInst, 1)>;
 }
 
-defm "" : SIMDQFM<v4f32, "f32x4", 0x98>;
-defm "" : SIMDQFM<v2f64, "f64x2", 0xa3>;
+defm "" : SIMDQFM<v4f32, "f32x4", 252>;
+defm "" : SIMDQFM<v2f64, "f64x2", 254>;

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

define <4 x float> @convert_u_v4f32(<4 x i32> %x) {
   %a = uitofp <4 x i32> %x to <4 x float>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: convert_s_v2f64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: f64x2.convert_i64x2_s
 ; SIMD128-NEXT: .functype convert_s_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_i64x2_s $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
 define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
   %a = sitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: convert_u_v2f64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: f64x2.convert_i64x2_u
 ; SIMD128-NEXT: .functype convert_u_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_i64x2_u $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
 define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
   %a = uitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = fptoui <4 x float> %x to <4 x i32>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v2i64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_s
 ; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.trunc_sat_f64x2_s $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
 define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
   %a = fptosi <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v2i64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_u
 ; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.trunc_sat_f64x2_u $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
 define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
   %a = fptoui <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
     <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c
   )
   ret <2 x i64> %a
 }
 
-; CHECK-LABEL: trunc_sat_s_v2i64:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.trunc_sat_f64x2_s $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
-declare <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double>)
-define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
-  %a = call <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double> %x)
-  ret <2 x i64> %a
-}
-
-; CHECK-LABEL: trunc_sat_u_v2i64:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.trunc_sat_f64x2_u $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
-declare <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double>)
-define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
-  %a = call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %x)
-  ret <2 x i64> %a
-}
-
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v4f32:
 ; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)

llvm/test/MC/Disassembler/WebAssembly/wasm.txt

 # CHECK: local.get 128
 0x20 0x80 0x01
 
 # Prefix byte example:
 # CHECK: i64.trunc_sat_f64_u
 0xFC 0x07
 
 # CHECK: v128.const 50462976, 117835012, 185207048, 252579084
-0xFD 0x02 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
+0xFD 0x0C 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
 
 # CHECK: v8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-0xFD 0x03 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
+0xFD 0x0D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
 
 # Check LEB128 encoding of SIMD instructions
-# CHECK: i64x2.all_true
-0xFD 0x86 0x01
+# CHECK: i16x8.all_true
+0xFD 0x83 0x01
 
 # Including non-canonical LEB128 encodings
-# CHECK: i64x2.any_true
-# CHECK-NOT: i64.div_u
-0xFD 0x85 0x81 0x80 0x80 0x80 0x80 0x00
+# CHECK: i16x8.any_true
+# CHECK-NOT: i16x8.neg
+0xFD 0x82 0x81 0x80 0x80 0x80 0x80 0x00
 
 # Check br_table, which has its own operand type.
 # CHECK: br_table {0, 1, 2}
 0x0E 0x02 0x00 0x01 0x02
 
 # This can mean end_block/end_loop/end_if/end_function/end_try..
 # CHECK: end
 0x0B
 
 # CHECK: br_on_exn 0, 0
 0x0A 0x00 0x00

llvm/test/MC/WebAssembly/simd-encodings.s

 # RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+unimplemented-simd128 < %s | FileCheck %s
 
 main:
     .functype main () -> ()
 
     # CHECK: v128.load 48 # encoding: [0xfd,0x00,0x04,0x30]
     v128.load 48
 
-    # CHECK: v128.store 48 # encoding: [0xfd,0x01,0x04,0x30]
+    # CHECK: i16x8.load8x8_s 32 # encoding: [0xfd,0x01,0x03,0x20]
+    i16x8.load8x8_s 32
+
+    # CHECK: i16x8.load8x8_u 32 # encoding: [0xfd,0x02,0x03,0x20]
+    i16x8.load8x8_u 32
+
+    # CHECK: i32x4.load16x4_s 32 # encoding: [0xfd,0x03,0x03,0x20]
+    i32x4.load16x4_s 32
+
+    # CHECK: i32x4.load16x4_u 32 # encoding: [0xfd,0x04,0x03,0x20]
+    i32x4.load16x4_u 32
+
+    # CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0x05,0x03,0x20]
+    i64x2.load32x2_s 32
+
+    # CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0x06,0x03,0x20]
+    i64x2.load32x2_u 32
+
+    # CHECK: v8x16.load_splat 48 # encoding: [0xfd,0x07,0x00,0x30]
+    v8x16.load_splat 48
+
+    # CHECK: v16x8.load_splat 48 # encoding: [0xfd,0x08,0x01,0x30]
+    v16x8.load_splat 48
+
+    # CHECK: v32x4.load_splat 48 # encoding: [0xfd,0x09,0x02,0x30]
+    v32x4.load_splat 48
+
+    # CHECK: v64x2.load_splat 48 # encoding: [0xfd,0x0a,0x03,0x30]
+    v64x2.load_splat 48
+
+    # CHECK: v128.store 48 # encoding: [0xfd,0x0b,0x04,0x30]
     v128.store 48
 
     # CHECK: v128.const 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-    # CHECK-SAME: # encoding: [0xfd,0x02,
+    # CHECK-SAME: # encoding: [0xfd,0x0c,
     # CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
     # CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
     v128.const 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 
     # CHECK: v128.const 256, 770, 1284, 1798, 2312, 2826, 3340, 3854
-    # CHECK-SAME: # encoding: [0xfd,0x02,
+    # CHECK-SAME: # encoding: [0xfd,0x0c,
     # CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
     # CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
     v128.const 256, 770, 1284, 1798, 2312, 2826, 3340, 3854
 
     # TODO(tlively): Fix assembler so v128.const works with 4xi32 and 2xi64
 
     # CHECK: v128.const 0x1.0402p-121, 0x1.0c0a08p-113,
     # CHECK-SAME:       0x1.14121p-105, 0x1.1c1a18p-97
-    # CHECK-SAME: # encoding: [0xfd,0x02,
+    # CHECK-SAME: # encoding: [0xfd,0x0c,
     # CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
     # CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
     v128.const 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97
 
     # CHECK: v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
-    # CHECK-SAME: # encoding: [0xfd,0x02,
+    # CHECK-SAME: # encoding: [0xfd,0x0c,
     # CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
     # CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
     v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
 
     # CHECK: v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
     # CHECK-SAME:          8, 25, 10, 27, 12, 29, 14, 31
-    # CHECK-SAME: # encoding: [0xfd,0x03,
+    # CHECK-SAME: # encoding: [0xfd,0x0d,
     # CHECK-SAME: 0x00,0x11,0x02,0x13,0x04,0x15,0x06,0x17,
     # CHECK-SAME: 0x08,0x19,0x0a,0x1b,0x0c,0x1d,0x0e,0x1f]
     v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
 
-    # CHECK: i8x16.splat # encoding: [0xfd,0x04]
+    # CHECK: v8x16.swizzle # encoding: [0xfd,0x0e]
+    v8x16.swizzle
+
+    # CHECK: i8x16.splat # encoding: [0xfd,0x0f]
     i8x16.splat
 
-    # CHECK: i8x16.extract_lane_s 15 # encoding: [0xfd,0x05,0x0f]
+    # CHECK: i16x8.splat # encoding: [0xfd,0x10]
+    i16x8.splat
+
+    # CHECK: i32x4.splat # encoding: [0xfd,0x11]
+    i32x4.splat
+
+    # CHECK: i64x2.splat # encoding: [0xfd,0x12]
+    i64x2.splat
+
+    # CHECK: f32x4.splat # encoding: [0xfd,0x13]
+    f32x4.splat
+
+    # CHECK: f64x2.splat # encoding: [0xfd,0x14]
+    f64x2.splat
+
+    # CHECK: i8x16.extract_lane_s 15 # encoding: [0xfd,0x15,0x0f]
     i8x16.extract_lane_s 15
 
-    # CHECK: i8x16.extract_lane_u 15 # encoding: [0xfd,0x06,0x0f]
+    # CHECK: i8x16.extract_lane_u 15 # encoding: [0xfd,0x16,0x0f]
     i8x16.extract_lane_u 15
 
-    # CHECK: i8x16.replace_lane 15 # encoding: [0xfd,0x07,0x0f]
+    # CHECK: i8x16.replace_lane 15 # encoding: [0xfd,0x17,0x0f]
     i8x16.replace_lane 15
 
-    # CHECK: i16x8.splat # encoding: [0xfd,0x08]
-    i16x8.splat
-
-    # CHECK: i16x8.extract_lane_s 7 # encoding: [0xfd,0x09,0x07]
+    # CHECK: i16x8.extract_lane_s 7 # encoding: [0xfd,0x18,0x07]
     i16x8.extract_lane_s 7
 
-    # CHECK: i16x8.extract_lane_u 7 # encoding: [0xfd,0x0a,0x07]
+    # CHECK: i16x8.extract_lane_u 7 # encoding: [0xfd,0x19,0x07]
     i16x8.extract_lane_u 7
 
-    # CHECK: i16x8.replace_lane 7 # encoding: [0xfd,0x0b,0x07]
+    # CHECK: i16x8.replace_lane 7 # encoding: [0xfd,0x1a,0x07]
     i16x8.replace_lane 7
 
-    # CHECK: i32x4.splat # encoding: [0xfd,0x0c]
-    i32x4.splat
-
-    # CHECK: i32x4.extract_lane 3 # encoding: [0xfd,0x0d,0x03]
+    # CHECK: i32x4.extract_lane 3 # encoding: [0xfd,0x1b,0x03]
     i32x4.extract_lane 3
 
-    # CHECK: i32x4.replace_lane 3 # encoding: [0xfd,0x0e,0x03]
+    # CHECK: i32x4.replace_lane 3 # encoding: [0xfd,0x1c,0x03]
     i32x4.replace_lane 3
 
-    # CHECK: i64x2.splat # encoding: [0xfd,0x0f]
-    i64x2.splat
-
-    # CHECK: i64x2.extract_lane 1 # encoding: [0xfd,0x10,0x01]
+    # CHECK: i64x2.extract_lane 1 # encoding: [0xfd,0x1d,0x01]
     i64x2.extract_lane 1
 
-    # CHECK: i64x2.replace_lane 1 # encoding: [0xfd,0x11,0x01]
+    # CHECK: i64x2.replace_lane 1 # encoding: [0xfd,0x1e,0x01]
     i64x2.replace_lane 1
 
-    # CHECK: f32x4.splat # encoding: [0xfd,0x12]
-    f32x4.splat
-
-    # CHECK: f32x4.extract_lane 3 # encoding: [0xfd,0x13,0x03]
+    # CHECK: f32x4.extract_lane 3 # encoding: [0xfd,0x1f,0x03]
     f32x4.extract_lane 3
 
-    # CHECK: f32x4.replace_lane 3 # encoding: [0xfd,0x14,0x03]
+    # CHECK: f32x4.replace_lane 3 # encoding: [0xfd,0x20,0x03]
     f32x4.replace_lane 3
 
-    # CHECK: f64x2.splat # encoding: [0xfd,0x15]
-    f64x2.splat
-
-    # CHECK: f64x2.extract_lane 1 # encoding: [0xfd,0x16,0x01]
+    # CHECK: f64x2.extract_lane 1 # encoding: [0xfd,0x21,0x01]
     f64x2.extract_lane 1
 
-    # CHECK: f64x2.replace_lane 1 # encoding: [0xfd,0x17,0x01]
+    # CHECK: f64x2.replace_lane 1 # encoding: [0xfd,0x22,0x01]
     f64x2.replace_lane 1
 
-    # CHECK: i8x16.eq # encoding: [0xfd,0x18]
+    # CHECK: i8x16.eq # encoding: [0xfd,0x23]
     i8x16.eq
 
-    # CHECK: i8x16.ne # encoding: [0xfd,0x19]
+    # CHECK: i8x16.ne # encoding: [0xfd,0x24]
     i8x16.ne
 
-    # CHECK: i8x16.lt_s # encoding: [0xfd,0x1a]
+    # CHECK: i8x16.lt_s # encoding: [0xfd,0x25]
     i8x16.lt_s
 
-    # CHECK: i8x16.lt_u # encoding: [0xfd,0x1b]
+    # CHECK: i8x16.lt_u # encoding: [0xfd,0x26]
     i8x16.lt_u
 
-    # CHECK: i8x16.gt_s # encoding: [0xfd,0x1c]
+    # CHECK: i8x16.gt_s # encoding: [0xfd,0x27]
     i8x16.gt_s
 
-    # CHECK: i8x16.gt_u # encoding: [0xfd,0x1d]
+    # CHECK: i8x16.gt_u # encoding: [0xfd,0x28]
     i8x16.gt_u
 
-    # CHECK: i8x16.le_s # encoding: [0xfd,0x1e]
+    # CHECK: i8x16.le_s # encoding: [0xfd,0x29]
     i8x16.le_s
 
-    # CHECK: i8x16.le_u # encoding: [0xfd,0x1f]
+    # CHECK: i8x16.le_u # encoding: [0xfd,0x2a]
     i8x16.le_u
 
-    # CHECK: i8x16.ge_s # encoding: [0xfd,0x20]
+    # CHECK: i8x16.ge_s # encoding: [0xfd,0x2b]
     i8x16.ge_s
 
-    # CHECK: i8x16.ge_u # encoding: [0xfd,0x21]
+    # CHECK: i8x16.ge_u # encoding: [0xfd,0x2c]
     i8x16.ge_u
 
-    # CHECK: i16x8.eq # encoding: [0xfd,0x22]
+    # CHECK: i16x8.eq # encoding: [0xfd,0x2d]
     i16x8.eq
 
-    # CHECK: i16x8.ne # encoding: [0xfd,0x23]
+    # CHECK: i16x8.ne # encoding: [0xfd,0x2e]
     i16x8.ne
 
-    # CHECK: i16x8.lt_s # encoding: [0xfd,0x24]
+    # CHECK: i16x8.lt_s # encoding: [0xfd,0x2f]
     i16x8.lt_s
 
-    # CHECK: i16x8.lt_u # encoding: [0xfd,0x25]
+    # CHECK: i16x8.lt_u # encoding: [0xfd,0x30]
     i16x8.lt_u
 
-    # CHECK: i16x8.gt_s # encoding: [0xfd,0x26]
+    # CHECK: i16x8.gt_s # encoding: [0xfd,0x31]
     i16x8.gt_s
 
-    # CHECK: i16x8.gt_u # encoding: [0xfd,0x27]
+    # CHECK: i16x8.gt_u # encoding: [0xfd,0x32]
     i16x8.gt_u
 
-    # CHECK: i16x8.le_s # encoding: [0xfd,0x28]
+    # CHECK: i16x8.le_s # encoding: [0xfd,0x33]
     i16x8.le_s
 
-    # CHECK: i16x8.le_u # encoding: [0xfd,0x29]
+    # CHECK: i16x8.le_u # encoding: [0xfd,0x34]
     i16x8.le_u
 
-    # CHECK: i16x8.ge_s # encoding: [0xfd,0x2a]
+    # CHECK: i16x8.ge_s # encoding: [0xfd,0x35]
     i16x8.ge_s
 
-    # CHECK: i16x8.ge_u # encoding: [0xfd,0x2b]
+    # CHECK: i16x8.ge_u # encoding: [0xfd,0x36]
     i16x8.ge_u
 
-    # CHECK: i32x4.eq # encoding: [0xfd,0x2c]
+    # CHECK: i32x4.eq # encoding: [0xfd,0x37]
     i32x4.eq
 
-    # CHECK: i32x4.ne # encoding: [0xfd,0x2d]
+    # CHECK: i32x4.ne # encoding: [0xfd,0x38]
     i32x4.ne
 
-    # CHECK: i32x4.lt_s # encoding: [0xfd,0x2e]
+    # CHECK: i32x4.lt_s # encoding: [0xfd,0x39]
     i32x4.lt_s
 
-    # CHECK: i32x4.lt_u # encoding: [0xfd,0x2f]
+    # CHECK: i32x4.lt_u # encoding: [0xfd,0x3a]
     i32x4.lt_u
 
-    # CHECK: i32x4.gt_s # encoding: [0xfd,0x30]
+    # CHECK: i32x4.gt_s # encoding: [0xfd,0x3b]
     i32x4.gt_s
 
-    # CHECK: i32x4.gt_u # encoding: [0xfd,0x31]
+    # CHECK: i32x4.gt_u # encoding: [0xfd,0x3c]
     i32x4.gt_u
 
-    # CHECK: i32x4.le_s # encoding: [0xfd,0x32]
+    # CHECK: i32x4.le_s # encoding: [0xfd,0x3d]
     i32x4.le_s
 
-    # CHECK: i32x4.le_u # encoding: [0xfd,0x33]
+    # CHECK: i32x4.le_u # encoding: [0xfd,0x3e]
     i32x4.le_u
 
-    # CHECK: i32x4.ge_s # encoding: [0xfd,0x34]
+    # CHECK: i32x4.ge_s # encoding: [0xfd,0x3f]
     i32x4.ge_s
 
-    # CHECK: i32x4.ge_u # encoding: [0xfd,0x35]
+    # CHECK: i32x4.ge_u # encoding: [0xfd,0x40]
     i32x4.ge_u
 
-    # CHECK: f32x4.eq # encoding: [0xfd,0x40]
+    # CHECK: f32x4.eq # encoding: [0xfd,0x41]
     f32x4.eq
 
-    # CHECK: f32x4.ne # encoding: [0xfd,0x41]
+    # CHECK: f32x4.ne # encoding: [0xfd,0x42]
     f32x4.ne
 
-    # CHECK: f32x4.lt # encoding: [0xfd,0x42]
+    # CHECK: f32x4.lt # encoding: [0xfd,0x43]
     f32x4.lt
 
-    # CHECK: f32x4.gt # encoding: [0xfd,0x43]
+    # CHECK: f32x4.gt # encoding: [0xfd,0x44]
     f32x4.gt
 
-    # CHECK: f32x4.le # encoding: [0xfd,0x44]
+    # CHECK: f32x4.le # encoding: [0xfd,0x45]
     f32x4.le
 
-    # CHECK: f32x4.ge # encoding: [0xfd,0x45]
+    # CHECK: f32x4.ge # encoding: [0xfd,0x46]
     f32x4.ge
 
-    # CHECK: f64x2.eq # encoding: [0xfd,0x46]
+    # CHECK: f64x2.eq # encoding: [0xfd,0x47]
     f64x2.eq
 
-    # CHECK: f64x2.ne # encoding: [0xfd,0x47]
+    # CHECK: f64x2.ne # encoding: [0xfd,0x48]
     f64x2.ne
 
-    # CHECK: f64x2.lt # encoding: [0xfd,0x48]
+    # CHECK: f64x2.lt # encoding: [0xfd,0x49]
     f64x2.lt
 
-    # CHECK: f64x2.gt # encoding: [0xfd,0x49]
+    # CHECK: f64x2.gt # encoding: [0xfd,0x4a]
     f64x2.gt
 
-    # CHECK: f64x2.le # encoding: [0xfd,0x4a]
+    # CHECK: f64x2.le # encoding: [0xfd,0x4b]
     f64x2.le
 
-    # CHECK: f64x2.ge # encoding: [0xfd,0x4b]
+    # CHECK: f64x2.ge # encoding: [0xfd,0x4c]
     f64x2.ge
 
-    # CHECK: v128.not # encoding: [0xfd,0x4c]
+    # CHECK: v128.not # encoding: [0xfd,0x4d]
     v128.not
 
-    # CHECK: v128.and # encoding: [0xfd,0x4d]
+    # CHECK: v128.and # encoding: [0xfd,0x4e]
     v128.and
 
-    # CHECK: v128.or # encoding: [0xfd,0x4e]
+    # CHECK: v128.andnot # encoding: [0xfd,0x4f]
+    v128.andnot
+
+    # CHECK: v128.or # encoding: [0xfd,0x50]
     v128.or
 
-    # CHECK: v128.xor # encoding: [0xfd,0x4f]
+    # CHECK: v128.xor # encoding: [0xfd,0x51]
     v128.xor
 
-    # CHECK: v128.bitselect # encoding: [0xfd,0x50]
+    # CHECK: v128.bitselect # encoding: [0xfd,0x52]
     v128.bitselect
 
-    # CHECK: i8x16.neg # encoding: [0xfd,0x51]
+    # CHECK: i8x16.abs # encoding: [0xfd,0x60]
+    i8x16.abs
+
+    # CHECK: i8x16.neg # encoding: [0xfd,0x61]
     i8x16.neg
 
-    # CHECK: i8x16.any_true # encoding: [0xfd,0x52]
+    # CHECK: i8x16.any_true # encoding: [0xfd,0x62]
     i8x16.any_true
 
-    # CHECK: i8x16.all_true # encoding: [0xfd,0x53]
+    # CHECK: i8x16.all_true # encoding: [0xfd,0x63]
     i8x16.all_true
 
-    # CHECK: i8x16.shl # encoding: [0xfd,0x54]
+    # CHECK: i8x16.bitmask # encoding: [0xfd,0x64]
+    i8x16.bitmask
+
+    # CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0x65]
+    i8x16.narrow_i16x8_s
+
+    # CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0x66]
+    i8x16.narrow_i16x8_u
+
+    # CHECK: i8x16.shl # encoding: [0xfd,0x6b]
     i8x16.shl
 
-    # CHECK: i8x16.shr_s # encoding: [0xfd,0x55]
+    # CHECK: i8x16.shr_s # encoding: [0xfd,0x6c]
     i8x16.shr_s
 
-    # CHECK: i8x16.shr_u # encoding: [0xfd,0x56]
+    # CHECK: i8x16.shr_u # encoding: [0xfd,0x6d]
     i8x16.shr_u
 
-    # CHECK: i8x16.add # encoding: [0xfd,0x57]
+    # CHECK: i8x16.add # encoding: [0xfd,0x6e]
     i8x16.add
 
-    # CHECK: i8x16.add_saturate_s # encoding: [0xfd,0x58]
+    # CHECK: i8x16.add_saturate_s # encoding: [0xfd,0x6f]
     i8x16.add_saturate_s
 
-    # CHECK: i8x16.add_saturate_u # encoding: [0xfd,0x59]
+    # CHECK: i8x16.add_saturate_u # encoding: [0xfd,0x70]
     i8x16.add_saturate_u
 
-    # CHECK: i8x16.sub # encoding: [0xfd,0x5a]
+    # CHECK: i8x16.sub # encoding: [0xfd,0x71]
     i8x16.sub
 
-    # CHECK: i8x16.sub_saturate_s # encoding: [0xfd,0x5b]
+    # CHECK: i8x16.sub_saturate_s # encoding: [0xfd,0x72]
     i8x16.sub_saturate_s
 
-    # CHECK: i8x16.sub_saturate_u # encoding: [0xfd,0x5c]
+    # CHECK: i8x16.sub_saturate_u # encoding: [0xfd,0x73]
     i8x16.sub_saturate_u
 
-    # CHECK: i8x16.mul # encoding: [0xfd,0x5d]
+    # CHECK: i8x16.mul # encoding: [0xfd,0x75]
     i8x16.mul
 
-    # CHECK: i8x16.min_s # encoding: [0xfd,0x5e]
+    # CHECK: i8x16.min_s # encoding: [0xfd,0x76]
     i8x16.min_s
 
-    # CHECK: i8x16.min_u # encoding: [0xfd,0x5f]
+    # CHECK: i8x16.min_u # encoding: [0xfd,0x77]
     i8x16.min_u
 
-    # CHECK: i8x16.max_s # encoding: [0xfd,0x60]
+    # CHECK: i8x16.max_s # encoding: [0xfd,0x78]
     i8x16.max_s
 
-    # CHECK: i8x16.max_u # encoding: [0xfd,0x61]
+    # CHECK: i8x16.max_u # encoding: [0xfd,0x79]
     i8x16.max_u
 
-    # CHECK: i16x8.neg # encoding: [0xfd,0x62]
+    # CHECK: i8x16.avgr_u # encoding: [0xfd,0x7b]
+    i8x16.avgr_u
+
+    # CHECK: i16x8.abs # encoding: [0xfd,0x80,0x01]
+    i16x8.abs
+
+    # CHECK: i16x8.neg # encoding: [0xfd,0x81,0x01]
     i16x8.neg
 
-    # CHECK: i16x8.any_true # encoding: [0xfd,0x63]
+    # CHECK: i16x8.any_true # encoding: [0xfd,0x82,0x01]
     i16x8.any_true
 
-    # CHECK: i16x8.all_true # encoding: [0xfd,0x64]
+    # CHECK: i16x8.all_true # encoding: [0xfd,0x83,0x01]
     i16x8.all_true
 
-    # CHECK: i16x8.shl # encoding: [0xfd,0x65]
+    # CHECK: i16x8.bitmask # encoding: [0xfd,0x84,0x01]
+    i16x8.bitmask
+
+    # CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0x85,0x01]
+    i16x8.narrow_i32x4_s
+
+    # CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0x86,0x01]
+    i16x8.narrow_i32x4_u
+
+    # CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0x87,0x01]
+    i16x8.widen_low_i8x16_s
+
+    # CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0x88,0x01]
+    i16x8.widen_high_i8x16_s
+
+    # CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0x89,0x01]
+    i16x8.widen_low_i8x16_u
+
+    # CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0x8a,0x01]
+    i16x8.widen_high_i8x16_u
+
+    # CHECK: i16x8.shl # encoding: [0xfd,0x8b,0x01]
     i16x8.shl
 
-    # CHECK: i16x8.shr_s # encoding: [0xfd,0x66]
+    # CHECK: i16x8.shr_s # encoding: [0xfd,0x8c,0x01]
     i16x8.shr_s
 
-    # CHECK: i16x8.shr_u # encoding: [0xfd,0x67]
+    # CHECK: i16x8.shr_u # encoding: [0xfd,0x8d,0x01]
     i16x8.shr_u
 
-    # CHECK: i16x8.add # encoding: [0xfd,0x68]
+    # CHECK: i16x8.add # encoding: [0xfd,0x8e,0x01]
     i16x8.add
 
-    # CHECK: i16x8.add_saturate_s # encoding: [0xfd,0x69]
+    # CHECK: i16x8.add_saturate_s # encoding: [0xfd,0x8f,0x01]
     i16x8.add_saturate_s
 
-    # CHECK: i16x8.add_saturate_u # encoding: [0xfd,0x6a]
+    # CHECK: i16x8.add_saturate_u # encoding: [0xfd,0x90,0x01]
     i16x8.add_saturate_u
 
-    # CHECK: i16x8.sub # encoding: [0xfd,0x6b]
+    # CHECK: i16x8.sub # encoding: [0xfd,0x91,0x01]
     i16x8.sub
 
-    # CHECK: i16x8.sub_saturate_s # encoding: [0xfd,0x6c]
+    # CHECK: i16x8.sub_saturate_s # encoding: [0xfd,0x92,0x01]
     i16x8.sub_saturate_s
 
-    # CHECK: i16x8.sub_saturate_u # encoding: [0xfd,0x6d]
+    # CHECK: i16x8.sub_saturate_u # encoding: [0xfd,0x93,0x01]
     i16x8.sub_saturate_u
 
-    # CHECK: i16x8.mul # encoding: [0xfd,0x6e]
+    # CHECK: i16x8.mul # encoding: [0xfd,0x95,0x01]
     i16x8.mul
 
-    # CHECK: i16x8.min_s # encoding: [0xfd,0x6f]
+    # CHECK: i16x8.min_s # encoding: [0xfd,0x96,0x01]
     i16x8.min_s
 
-    # CHECK: i16x8.min_u # encoding: [0xfd,0x70]
+    # CHECK: i16x8.min_u # encoding: [0xfd,0x97,0x01]
     i16x8.min_u
 
-    # CHECK: i16x8.max_s # encoding: [0xfd,0x71]
+    # CHECK: i16x8.max_s # encoding: [0xfd,0x98,0x01]
     i16x8.max_s
 
-    # CHECK: i16x8.max_u # encoding: [0xfd,0x72]
+    # CHECK: i16x8.max_u # encoding: [0xfd,0x99,0x01]
     i16x8.max_u
 
-    # CHECK: i32x4.neg # encoding: [0xfd,0x73]
+    # CHECK: i16x8.avgr_u # encoding: [0xfd,0x9b,0x01]
+    i16x8.avgr_u
+
+    # CHECK: i32x4.abs # encoding: [0xfd,0xa0,0x01]
+    i32x4.abs
+
+    # CHECK: i32x4.neg # encoding: [0xfd,0xa1,0x01]
     i32x4.neg
 
-    # CHECK: i32x4.any_true # encoding: [0xfd,0x74]
+    # CHECK: i32x4.any_true # encoding: [0xfd,0xa2,0x01]
     i32x4.any_true
 
-    # CHECK: i32x4.all_true # encoding: [0xfd,0x75]
+    # CHECK: i32x4.all_true # encoding: [0xfd,0xa3,0x01]
     i32x4.all_true
 
-    # CHECK: i32x4.shl # encoding: [0xfd,0x76]
+    # CHECK: i32x4.bitmask # encoding: [0xfd,0xa4,0x01]
+    i32x4.bitmask
+
+    # CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xa7,0x01]
+    i32x4.widen_low_i16x8_s
+
+    # CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xa8,0x01]
+    i32x4.widen_high_i16x8_s
+
+    # CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xa9,0x01]
+    i32x4.widen_low_i16x8_u
+
+    # CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xaa,0x01]
+    i32x4.widen_high_i16x8_u
+
+    # CHECK: i32x4.shl # encoding: [0xfd,0xab,0x01]
     i32x4.shl
 
-    # CHECK: i32x4.shr_s # encoding: [0xfd,0x77]
+    # CHECK: i32x4.shr_s # encoding: [0xfd,0xac,0x01]
     i32x4.shr_s
 
-    # CHECK: i32x4.shr_u # encoding: [0xfd,0x78]
+    # CHECK: i32x4.shr_u # encoding: [0xfd,0xad,0x01]
     i32x4.shr_u
 
-    # CHECK: i32x4.add # encoding: [0xfd,0x79]
+    # CHECK: i32x4.add # encoding: [0xfd,0xae,0x01]
     i32x4.add
 
-    # CHECK: i32x4.sub # encoding: [0xfd,0x7c]
+    # CHECK: i32x4.sub # encoding: [0xfd,0xb1,0x01]
     i32x4.sub
 
-    # CHECK: i32x4.mul # encoding: [0xfd,0x7f]
+    # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xb4,0x01]
+    i32x4.dot_i16x8_s
+
+    # CHECK: i32x4.mul # encoding: [0xfd,0xb5,0x01]
     i32x4.mul
 
-    # CHECK: i32x4.min_s # encoding: [0xfd,0x80,0x01]
+    # CHECK: i32x4.min_s # encoding: [0xfd,0xb6,0x01]
     i32x4.min_s
 
-    # CHECK: i32x4.min_u # encoding: [0xfd,0x81,0x01]
+    # CHECK: i32x4.min_u # encoding: [0xfd,0xb7,0x01]
     i32x4.min_u
 
-    # CHECK: i32x4.max_s # encoding: [0xfd,0x82,0x01]
+    # CHECK: i32x4.max_s # encoding: [0xfd,0xb8,0x01]
     i32x4.max_s
 
-    # CHECK: i32x4.max_u # encoding: [0xfd,0x83,0x01]
+    # CHECK: i32x4.max_u # encoding: [0xfd,0xb9,0x01]
     i32x4.max_u
 
-    # CHECK: i64x2.neg # encoding: [0xfd,0x84,0x01]
+    # CHECK: i64x2.neg # encoding: [0xfd,0xc1,0x01]
     i64x2.neg
 
-    # CHECK: i64x2.any_true # encoding: [0xfd,0x85,0x01]
+    # CHECK: i64x2.any_true # encoding: [0xfd,0xc2,0x01]
     i64x2.any_true
 
-    # CHECK: i64x2.all_true # encoding: [0xfd,0x86,0x01]
+    # CHECK: i64x2.all_true # encoding: [0xfd,0xc3,0x01]
     i64x2.all_true
 
-    # CHECK: i64x2.shl # encoding: [0xfd,0x87,0x01]
+    # CHECK: i64x2.shl # encoding: [0xfd,0xcb,0x01]
     i64x2.shl
 
-    # CHECK: i64x2.shr_s # encoding: [0xfd,0x88,0x01]
+    # CHECK: i64x2.shr_s # encoding: [0xfd,0xcc,0x01]
     i64x2.shr_s
 
-    # CHECK: i64x2.shr_u # encoding: [0xfd,0x89,0x01]
+    # CHECK: i64x2.shr_u # encoding: [0xfd,0xcd,0x01]
     i64x2.shr_u
 
-    # CHECK: i64x2.add # encoding: [0xfd,0x8a,0x01]
+    # CHECK: i64x2.add # encoding: [0xfd,0xce,0x01]
     i64x2.add
 
-    # CHECK: i64x2.sub # encoding: [0xfd,0x8d,0x01]
+    # CHECK: i64x2.sub # encoding: [0xfd,0xd1,0x01]
     i64x2.sub
 
-    # CHECK: f32x4.abs # encoding: [0xfd,0x95,0x01]
+    # CHECK: f32x4.abs # encoding: [0xfd,0xe0,0x01]
     f32x4.abs
 
-    # CHECK: f32x4.neg # encoding: [0xfd,0x96,0x01]
+    # CHECK: f32x4.neg # encoding: [0xfd,0xe1,0x01]
     f32x4.neg
 
-    # CHECK: f32x4.sqrt # encoding: [0xfd,0x97,0x01]
+    # CHECK: f32x4.sqrt # encoding: [0xfd,0xe3,0x01]
     f32x4.sqrt
 
-    # CHECK: f32x4.qfma # encoding: [0xfd,0x98,0x01]
-    f32x4.qfma
-
-    # CHECK: f32x4.qfms # encoding: [0xfd,0x99,0x01]
-    f32x4.qfms
-
-    # CHECK: f32x4.add # encoding: [0xfd,0x9a,0x01]
+    # CHECK: f32x4.add # encoding: [0xfd,0xe4,0x01]
     f32x4.add
 
-    # CHECK: f32x4.sub # encoding: [0xfd,0x9b,0x01]
+    # CHECK: f32x4.sub # encoding: [0xfd,0xe5,0x01]
     f32x4.sub
 
-    # CHECK: f32x4.mul # encoding: [0xfd,0x9c,0x01]
+    # CHECK: f32x4.mul # encoding: [0xfd,0xe6,0x01]
     f32x4.mul
 
-    # CHECK: f32x4.div # encoding: [0xfd,0x9d,0x01]
+    # CHECK: f32x4.div # encoding: [0xfd,0xe7,0x01]
     f32x4.div
 
-    # CHECK: f32x4.min # encoding: [0xfd,0x9e,0x01]
+    # CHECK: f32x4.min # encoding: [0xfd,0xe8,0x01]
     f32x4.min
 
-    # CHECK: f32x4.max # encoding: [0xfd,0x9f,0x01]
+    # CHECK: f32x4.max # encoding: [0xfd,0xe9,0x01]
     f32x4.max
 
-    # CHECK: f64x2.abs # encoding: [0xfd,0xa0,0x01]
+    # CHECK: f64x2.abs # encoding: [0xfd,0xec,0x01]
     f64x2.abs
 
-    # CHECK: f64x2.neg # encoding: [0xfd,0xa1,0x01]
+    # CHECK: f64x2.neg # encoding: [0xfd,0xed,0x01]
     f64x2.neg
 
-    # CHECK: f64x2.sqrt # encoding: [0xfd,0xa2,0x01]
+    # CHECK: f64x2.sqrt # encoding: [0xfd,0xef,0x01]
     f64x2.sqrt
 
-    # CHECK: f64x2.qfma # encoding: [0xfd,0xa3,0x01]
-    f64x2.qfma
-
-    # CHECK: f64x2.qfms # encoding: [0xfd,0xa4,0x01]
-    f64x2.qfms
-
-    # CHECK: f64x2.add # encoding: [0xfd,0xa5,0x01]
+    # CHECK: f64x2.add # encoding: [0xfd,0xf0,0x01]
     f64x2.add
 
-    # CHECK: f64x2.sub # encoding: [0xfd,0xa6,0x01]
+    # CHECK: f64x2.sub # encoding: [0xfd,0xf1,0x01]
     f64x2.sub
 
-    # CHECK: f64x2.mul # encoding: [0xfd,0xa7,0x01]
+    # CHECK: f64x2.mul # encoding: [0xfd,0xf2,0x01]
     f64x2.mul
 
-    # CHECK: f64x2.div # encoding: [0xfd,0xa8,0x01]
+    # CHECK: f64x2.div # encoding: [0xfd,0xf3,0x01]
     f64x2.div
 
-    # CHECK: f64x2.min # encoding: [0xfd,0xa9,0x01]
+    # CHECK: f64x2.min # encoding: [0xfd,0xf4,0x01]
     f64x2.min
 
-    # CHECK: f64x2.max # encoding: [0xfd,0xaa,0x01]
+    # CHECK: f64x2.max # encoding: [0xfd,0xf5,0x01]
     f64x2.max
 
-    # CHECK: i32x4.trunc_sat_f32x4_s # encoding: [0xfd,0xab,0x01]
+    # CHECK: i32x4.trunc_sat_f32x4_s # encoding: [0xfd,0xf8,0x01]
     i32x4.trunc_sat_f32x4_s
 
-    # CHECK: i32x4.trunc_sat_f32x4_u # encoding: [0xfd,0xac,0x01]
+    # CHECK: i32x4.trunc_sat_f32x4_u # encoding: [0xfd,0xf9,0x01]
     i32x4.trunc_sat_f32x4_u
 
-    # CHECK: i64x2.trunc_sat_f64x2_s # encoding: [0xfd,0xad,0x01]
-    i64x2.trunc_sat_f64x2_s
-
-    # CHECK: i64x2.trunc_sat_f64x2_u # encoding: [0xfd,0xae,0x01]
-    i64x2.trunc_sat_f64x2_u
-
-    # CHECK: f32x4.convert_i32x4_s # encoding: [0xfd,0xaf,0x01]
+    # CHECK: f32x4.convert_i32x4_s # encoding: [0xfd,0xfa,0x01]
     f32x4.convert_i32x4_s
 
-    # CHECK: f32x4.convert_i32x4_u # encoding: [0xfd,0xb0,0x01]
+    # CHECK: f32x4.convert_i32x4_u # encoding: [0xfd,0xfb,0x01]
     f32x4.convert_i32x4_u
 
-    # CHECK: f64x2.convert_i64x2_s # encoding: [0xfd,0xb1,0x01]
-    f64x2.convert_i64x2_s
-
-    # CHECK: f64x2.convert_i64x2_u # encoding: [0xfd,0xb2,0x01]
-    f64x2.convert_i64x2_u
-
-    # CHECK: v8x16.swizzle # encoding: [0xfd,0xc0,0x01]
-    v8x16.swizzle
-
-    # CHECK: v8x16.load_splat 48 # encoding: [0xfd,0xc2,0x01,0x00,0x30]
-    v8x16.load_splat 48
-
-    # CHECK: v16x8.load_splat 48 # encoding: [0xfd,0xc3,0x01,0x01,0x30]
-    v16x8.load_splat 48
-
-    # CHECK: v32x4.load_splat 48 # encoding: [0xfd,0xc4,0x01,0x02,0x30]
-    v32x4.load_splat 48
-
-    # CHECK: v64x2.load_splat 48 # encoding: [0xfd,0xc5,0x01,0x03,0x30]
-    v64x2.load_splat 48
-
-    # CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0xc6,0x01]
-    i8x16.narrow_i16x8_s
-
-    # CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0xc7,0x01]
-    i8x16.narrow_i16x8_u
-
-    # CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0xc8,0x01]
-    i16x8.narrow_i32x4_s
-
-    # CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0xc9,0x01]
-    i16x8.narrow_i32x4_u
-
-    # CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0xca,0x01]
-    i16x8.widen_low_i8x16_s
-
-    # CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0xcb,0x01]
-    i16x8.widen_high_i8x16_s
-
-    # CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0xcc,0x01]
-    i16x8.widen_low_i8x16_u
-
-    # CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0xcd,0x01]
-    i16x8.widen_high_i8x16_u
-
-    # CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xce,0x01]
-    i32x4.widen_low_i16x8_s
-
-    # CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xcf,0x01]
-    i32x4.widen_high_i16x8_s
-
-    # CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xd0,0x01]
-    i32x4.widen_low_i16x8_u
-
-    # CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
-    i32x4.widen_high_i16x8_u
-
-    # CHECK: i16x8.load8x8_s 32 # encoding: [0xfd,0xd2,0x01,0x03,0x20]
-    i16x8.load8x8_s 32
-
-    # CHECK: i16x8.load8x8_u 32 # encoding: [0xfd,0xd3,0x01,0x03,0x20]
-    i16x8.load8x8_u 32
-
-    # CHECK: i32x4.load16x4_s 32 # encoding: [0xfd,0xd4,0x01,0x03,0x20]
-    i32x4.load16x4_s 32
-
-    # CHECK: i32x4.load16x4_u 32 # encoding: [0xfd,0xd5,0x01,0x03,0x20]
-    i32x4.load16x4_u 32
-
-    # CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0xd6,0x01,0x03,0x20]
-    i64x2.load32x2_s 32
-
-    # CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0xd7,0x01,0x03,0x20]
-    i64x2.load32x2_u 32
-
-    # CHECK: v128.andnot # encoding: [0xfd,0xd8,0x01]
-    v128.andnot
-
-    # CHECK: i8x16.avgr_u # encoding: [0xfd,0xd9,0x01]
-    i8x16.avgr_u
-
-    # CHECK: i16x8.avgr_u # encoding: [0xfd,0xda,0x01]
-    i16x8.avgr_u
-
-    # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
-    i32x4.dot_i16x8_s
-
-    # CHECK: i8x16.abs # encoding: [0xfd,0xe1,0x01]
-    i8x16.abs
-
-    # CHECK: i16x8.abs # encoding: [0xfd,0xe2,0x01]
-    i16x8.abs
-
-    # CHECK: i32x4.abs # encoding: [0xfd,0xe3,0x01]
-    i32x4.abs
+    # CHECK: f32x4.qfma # encoding: [0xfd,0xfc,0x01]
+    f32x4.qfma
 
-    # CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
-    i8x16.bitmask
+    # CHECK: f32x4.qfms # encoding: [0xfd,0xfd,0x01]
+    f32x4.qfms
 
-    # CHECK: i16x8.bitmask # encoding: [0xfd,0xe5,0x01]
-    i16x8.bitmask
+    # CHECK: f64x2.qfma # encoding: [0xfd,0xfe,0x01]
+    f64x2.qfma
 
-    # CHECK: i32x4.bitmask # encoding: [0xfd,0xe6,0x01]
-    i32x4.bitmask
+    # CHECK: f64x2.qfms # encoding: [0xfd,0xff,0x01]
+    f64x2.qfms
 
     end_function