[NFC] [PowerPC] Narrow fast-math flags in tests

[qiucf]

Summary

A lot of tests under PowerPC are using fast flag, while fast is just alias of 7 fast-math flags. This change makes test points clearer.

mc-instrlat.ll and sms-iterator.ll keeps unchanged since they are not testing fast-math behavior (one for machine combiner crash, one for machine pipeliner bug).

[qiucf]

Remove an incorrect update_script header

[spatel]

More precise FMF in tests is appreciated - LGTM.

llvm/test/CodeGen/PowerPC/fma-mutate.ll

1–4

This comment does not seem to match the content of this file, so it might be better to update this independently or with a 2nd commit (and auto-generating the complete output would be nice too).

[steven.zhang]

llvm/test/CodeGen/PowerPC/scalar-equal.ll

55

The change here is questionable. If we have the fast flag set, we shouldn't see the different instruction sequence w/o --enable-unsafe-fp-math. Please double confirm with compiler implementation to see what happens.

llvm/test/CodeGen/PowerPC/scalar-min-max.ll

131

The same as above comments.

[qiucf]

llvm/test/CodeGen/PowerPC/scalar-equal.ll

55

That's not related to unsafe-fp-math. That's a bug about flag propagation. See D79074, thanks.

[steven.zhang]

LGTM now as far as D79074 is addressed. We missed to respect the fast flags when lowering the select_cc. Thank you for doing this.

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; CHECK-NEXT:    xvmaddadp 1, 0, 2
 ; CHECK-NEXT:    xvmsubadp 2, 2, 1
 ; CHECK-NEXT:    xvmuldp 34, 34, 2
 ; CHECK-NEXT:    xvmuldp 35, 35, 2
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
-  %div = fdiv fast <4 x double> %a1, %splat.splat
-  %sub = fsub fast <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
+  %div = fdiv reassoc nsz arcp <4 x double> %a1, %splat.splat
+  %sub = fsub reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/fdiv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
 
 define dso_local float @foo(float %0, float %1) local_unnamed_addr {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsresp 3, 2
 ; CHECK-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-NEXT:    xsnmsubasp 1, 2, 0
 ; CHECK-NEXT:    xsmaddasp 0, 3, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
-  %3 = fdiv fast float %0, %1
+  %3 = fdiv reassoc arcp float %0, %1
   ret float %3
 }

llvm/test/CodeGen/PowerPC/fma-assoc.ll

 ;
 ; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC2:
 ; CHECK-VSX:       # %bb.0:
 ; CHECK-VSX-NEXT:    xsnmsubmdp 3, 4, 5
 ; CHECK-VSX-NEXT:    xsnmsubadp 3, 1, 2
 ; CHECK-VSX-NEXT:    fmr 1, 3
 ; CHECK-VSX-NEXT:    blr
                                  double %D, double %E) {
-  %F = fmul fast double %A, %B         ; <double> [#uses=1]
-  %G = fmul fast double %C, %D         ; <double> [#uses=1]
-  %H = fadd fast double %F, %G         ; <double> [#uses=1]
-  %I = fsub fast double %E, %H         ; <double> [#uses=1]
+  %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
+  %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
+  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
+  %I = fsub reassoc nsz double %E, %H         ; <double> [#uses=1]
   ret double %I
 }
 
 define double @test_reassoc_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
 ; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmadd 0, 1, 2, 5
 ; CHECK-NEXT:    fmadd 1, 3, 4, 0

llvm/test/CodeGen/PowerPC/fma-combine.ll

 ; CHECK-NEXT:    lfs 3, .LCPI4_1@toc@l(4)
 ; CHECK-NEXT:    lfs 1, .LCPI4_2@toc@l(3)
 ; CHECK-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-NEXT:    xsmaddasp 1, 2, 3
 ; CHECK-NEXT:    xsnmsubasp 1, 3, 2
 ; CHECK-NEXT:    blr
   %tmp = load float, float* undef, align 4
   %tmp2 = load float, float* undef, align 4
-  %tmp3 = fmul fast float %tmp, 0x3FE372D780000000
-  %tmp4 = fadd fast float %tmp3, 1.000000e+00
-  %tmp5 = fmul fast float %tmp2, %tmp4
+  %tmp3 = fmul reassoc float %tmp, 0x3FE372D780000000
+  %tmp4 = fadd reassoc float %tmp3, 1.000000e+00
+  %tmp5 = fmul reassoc float %tmp2, %tmp4
   %tmp6 = load float, float* undef, align 4
   %tmp7 = load float, float* undef, align 4
-  %tmp8 = fmul fast float %tmp7, 0x3FE372D780000000
-  %tmp9 = fsub fast float -1.000000e+00, %tmp8
-  %tmp10 = fmul fast float %tmp9, %tmp6
-  %tmp11 = fadd fast float %tmp5, 5.000000e-01
-  %tmp12 = fadd fast float %tmp11, %tmp10
+  %tmp8 = fmul reassoc float %tmp7, 0x3FE372D780000000
+  %tmp9 = fsub reassoc nsz float -1.000000e+00, %tmp8
+  %tmp10 = fmul reassoc float %tmp9, %tmp6
+  %tmp11 = fadd reassoc float %tmp5, 5.000000e-01
+  %tmp12 = fadd reassoc float %tmp11, %tmp10
   ret float %tmp12
 }
 
 ; This would crash while trying getNegatedExpression().
 define double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_1@toc@ha

 ; CHECK-NEXT:    addis 4, 2, .LCPI5_0@toc@ha
 ; CHECK-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
 ; CHECK-NEXT:    lfs 4, .LCPI5_0@toc@l(4)
 ; CHECK-NEXT:    xssubdp 0, 1, 3
 ; CHECK-NEXT:    xsmaddadp 3, 1, 4
 ; CHECK-NEXT:    xsmaddadp 0, 3, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
-  %neg = fneg fast double %x
-  %fma = call fast double @llvm.fma.f64(double %neg, double 42.0, double -1.0)
-  %add = fadd fast double %x, 1.0
-  %fma1 = call fast double @llvm.fma.f64(double %fma, double %y, double %add)
+  %neg = fneg reassoc double %x
+  %fma = call reassoc nsz double @llvm.fma.f64(double %neg, double 42.0, double -1.0)
+  %add = fadd reassoc nsz double %x, 1.0
+  %fma1 = call reassoc nsz double @llvm.fma.f64(double %fma, double %y, double %add)
   ret double %fma1
 }
 declare double @llvm.fma.f64(double, double, double) nounwind readnone

llvm/test/CodeGen/PowerPC/fma-mutate.ll

 ; Test several VSX FMA mutation opportunities.  The first one isn't a
 ; reasonable transformation because the killed product register is the
 ; same as the FMA target register.  The second one is legal.  The third
 ; one doesn't fit the feeding-copy pattern.
 
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 declare double @llvm.sqrt.f64(double)
 
 define double @foo3_fmf(double %a) nounwind {
 ; CHECK: @foo3_fmf
 ; CHECK-NOT: fmr
 ; CHECK: xsmaddmdp
 ; CHECK: xsmaddadp
-  %r = call fast double @llvm.sqrt.f64(double %a)
+  %r = call reassoc afn ninf double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_safe(double %a) nounwind {
 ; CHECK: @foo3_safe
 ; CHECK-NOT: fmr
 ; CHECK: xssqrtdp
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 

llvm/test/CodeGen/PowerPC/fma-negate.ll

 ; VSX-NEXT:    xsnmsubadp 1, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_mul_sub_f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsub 1, 2, 3, 1
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul fast double %b, %c
-  %1 = fsub fast double %a, %0
+  %0 = fmul reassoc double %b, %c
+  %1 = fsub reassoc double %a, %0
   ret double %1
 }
 
 define double @test_fast_2mul_sub_f64(double %a, double %b, double %c,
 ; VSX-LABEL: test_fast_2mul_sub_f64:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsmuldp 0, 3, 4
 ; VSX-NEXT:    xsmsubadp 0, 1, 2
 ; VSX-NEXT:    fmr 1, 0
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_2mul_sub_f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fmul 0, 3, 4
 ; NO-VSX-NEXT:    fmsub 1, 1, 2, 0
 ; NO-VSX-NEXT:    blr
                                       double %d) {
 entry:
-  %0 = fmul fast double %a, %b
-  %1 = fmul fast double %c, %d
-  %2 = fsub fast double %0, %1
+  %0 = fmul reassoc double %a, %b
+  %1 = fmul reassoc double %c, %d
+  %2 = fsub reassoc double %0, %1
   ret double %2
 }
 
 define double @test_fast_neg_fma_f64(double %a, double %b, double %c) {
 ; VSX-LABEL: test_fast_neg_fma_f64:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsnmsubadp 3, 1, 2
 ; VSX-NEXT:    fmr 1, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsub 1, 1, 2, 3
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fsub fast double -0.0, %a
-  %1 = call fast double @llvm.fma.f64(double %0, double %b, double %c)
+  %0 = fsub reassoc double -0.0, %a
+  %1 = call reassoc double @llvm.fma.f64(double %0, double %b, double %c)
   ret double %1
 }
 
 define float @test_fast_mul_sub_f32(float %a, float %b, float %c) {
 ; VSX-LABEL: test_fast_mul_sub_f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsnmsubasp 1, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_mul_sub_f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsubs 1, 2, 3, 1
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul fast float %b, %c
-  %1 = fsub fast float %a, %0
+  %0 = fmul reassoc float %b, %c
+  %1 = fsub reassoc float %a, %0
   ret float %1
 }
 
 define float @test_fast_2mul_sub_f32(float %a, float %b, float %c, float %d) {
 ; VSX-LABEL: test_fast_2mul_sub_f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsmulsp 0, 3, 4
 ; VSX-NEXT:    xsmsubasp 0, 1, 2
 ; VSX-NEXT:    fmr 1, 0
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_2mul_sub_f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fmuls 0, 3, 4
 ; NO-VSX-NEXT:    fmsubs 1, 1, 2, 0
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul fast float %a, %b
-  %1 = fmul fast float %c, %d
-  %2 = fsub fast float %0, %1
+  %0 = fmul reassoc float %a, %b
+  %1 = fmul reassoc float %c, %d
+  %2 = fsub reassoc float %0, %1
   ret float %2
 }
 
 define float @test_fast_neg_fma_f32(float %a, float %b, float %c) {
 ; VSX-LABEL: test_fast_neg_fma_f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsnmsubasp 3, 1, 2
 ; VSX-NEXT:    fmr 1, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsubs 1, 1, 2, 3
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fsub fast float -0.0, %a
-  %1 = call fast float @llvm.fma.f32(float %0, float %b, float %c)
+  %0 = fsub reassoc float -0.0, %a
+  %1 = call reassoc float @llvm.fma.f32(float %0, float %b, float %c)
   ret float %1
 }
 
 define <2 x double> @test_fast_neg_fma_v2f64(<2 x double> %a, <2 x double> %b,
 ; VSX-LABEL: test_fast_neg_fma_v2f64:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xvnmsubadp 36, 34, 35
 ; VSX-NEXT:    vmr 2, 4
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_v2f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsub 1, 1, 3, 5
 ; NO-VSX-NEXT:    fnmsub 2, 2, 4, 6
 ; NO-VSX-NEXT:    blr
                                              <2 x double> %c) {
 entry:
-  %0 = fsub fast <2 x double> <double -0.0, double -0.0>, %a
-  %1 = call fast <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %b,
+  %0 = fsub reassoc <2 x double> <double -0.0, double -0.0>, %a
+  %1 = call reassoc <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %b,
                                               <2 x double> %c)
   ret <2 x double> %1
 }
 
 define <4 x float> @test_fast_neg_fma_v4f32(<4 x float> %a, <4 x float> %b,
 ; VSX-LABEL: test_fast_neg_fma_v4f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xvnmsubasp 36, 34, 35
 ; VSX-NEXT:    vmr 2, 4
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_v4f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    vspltisb 5, -1
 ; NO-VSX-NEXT:    vslw 5, 5, 5
 ; NO-VSX-NEXT:    vsubfp 2, 5, 2
 ; NO-VSX-NEXT:    vmaddfp 2, 2, 3, 4
 ; NO-VSX-NEXT:    blr
                                             <4 x float> %c) {
 entry:
-  %0 = fsub fast <4 x float> <float -0.0, float -0.0, float -0.0,
+  %0 = fsub reassoc <4 x float> <float -0.0, float -0.0, float -0.0,
                                           float -0.0>, %a
-  %1 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %b,
+  %1 = call reassoc <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %b,
                                                          <4 x float> %c)
   ret <4 x float> %1
 }
 
 declare float  @llvm.fma.f32(float  %a, float  %b, float  %c)
 declare double @llvm.fma.f64(double %a, double %b, double %c)
 declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,
                                                     <4 x float> %c)
 declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,
                                                       <2 x double> %c)

llvm/test/CodeGen/PowerPC/fma-precision.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-linux-gnu | FileCheck %s
 
 ; Verify that the fold of a*b-c*d respect the uses of a*b
 define double @fsub1(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fsub1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 2, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    xsnmsubadp 1, 4, 3
 ; CHECK-NEXT:    xsmuldp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %sub = fsub fast double %mul, %mul1
-  %mul3 = fmul fast double %mul, %sub
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %sub = fsub reassoc double %mul, %mul1
+  %mul3 = fmul reassoc double %mul, %sub
   ret double %mul3
 }
 
 ; Verify that the fold of a*b-c*d respect the uses of c*d
 define double @fsub2(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fsub2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 4, 3
 ; CHECK-NEXT:    fmr 3, 0
 ; CHECK-NEXT:    xsmsubadp 3, 2, 1
 ; CHECK-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %sub = fsub fast double %mul, %mul1
-  %mul3 = fmul fast double %mul1, %sub
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %sub = fsub reassoc double %mul, %mul1
+  %mul3 = fmul reassoc double %mul1, %sub
   ret double %mul3
 }
 
 ; Verify that the fold of a*b-c*d if there is no uses of a*b and c*d
 define double @fsub3(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fsub3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 4, 3
 ; CHECK-NEXT:    xsmsubadp 0, 2, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %sub = fsub fast double %mul, %mul1
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %sub = fsub reassoc double %mul, %mul1
   ret double %sub
 }
 
 ; Verify that the fold of a*b+c*d respect the uses of a*b
 define double @fadd1(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fadd1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 2, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    xsmaddadp 1, 4, 3
 ; CHECK-NEXT:    xsmuldp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %add = fadd fast double %mul1, %mul
-  %mul3 = fmul fast double %mul, %add
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %add = fadd reassoc double %mul1, %mul
+  %mul3 = fmul reassoc double %mul, %add
   ret double %mul3
 }
 
 ; Verify that the fold of a*b+c*d respect the uses of c*d
 define double @fadd2(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fadd2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 4, 3
 ; CHECK-NEXT:    fmr 3, 0
 ; CHECK-NEXT:    xsmaddadp 3, 2, 1
 ; CHECK-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %add = fadd fast double %mul1, %mul
-  %mul3 = fmul fast double %mul1, %add
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %add = fadd reassoc double %mul1, %mul
+  %mul3 = fmul reassoc double %mul1, %add
   ret double %mul3
 }
 
 ; Verify that the fold of a*b+c*d if there is no uses of a*b and c*d
 define double @fadd3(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fadd3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 1, 2, 1
 ; CHECK-NEXT:    xsmaddadp 1, 4, 3
 ; CHECK-NEXT:    blr
 entry:
-  %mul = fmul fast double %b, %a
-  %mul1 = fmul fast double %d, %c
-  %add = fadd fast double %mul1, %mul
+  %mul = fmul reassoc double %b, %a
+  %mul1 = fmul reassoc double %d, %c
+  %add = fadd reassoc double %mul1, %mul
   ret double %add
 }
 
 define double @fma_multi_uses1(double %a, double %b, double %c, double %d, double* %p1, double* %p2, double* %p3) {
 ; CHECK-LABEL: fma_multi_uses1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmuldp 1, 1, 2
 ; CHECK-NEXT:    xsmuldp 0, 3, 4
 ; CHECK-NEXT:    stfd 1, 0(7)
 ; CHECK-NEXT:    stfd 1, 0(8)
 ; CHECK-NEXT:    xsnmsubadp 1, 3, 4
 ; CHECK-NEXT:    stfd 0, 0(9)
 ; CHECK-NEXT:    blr
-  %ab = fmul fast double %a, %b
-  %cd = fmul fast double %c, %d
+  %ab = fmul reassoc double %a, %b
+  %cd = fmul reassoc double %c, %d
   store double %ab, double* %p1 ; extra use of %ab
   store double %ab, double* %p2 ; another extra use of %ab
   store double %cd, double* %p3 ; extra use of %cd
-  %r = fsub fast double %ab, %cd
+  %r = fsub reassoc double %ab, %cd
   ret double %r
 }
 
 define double @fma_multi_uses2(double %a, double %b, double %c, double %d, double* %p1, double* %p2, double* %p3) {
 ; CHECK-LABEL: fma_multi_uses2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmuldp 5, 1, 2
 ; CHECK-NEXT:    xsmuldp 0, 3, 4
 ; CHECK-NEXT:    stfd 5, 0(7)
 ; CHECK-NEXT:    stfd 0, 0(8)
 ; CHECK-NEXT:    stfd 0, 0(9)
 ; CHECK-NEXT:    xsmsubadp 0, 1, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
-  %ab = fmul fast double %a, %b
-  %cd = fmul fast double %c, %d
+  %ab = fmul reassoc double %a, %b
+  %cd = fmul reassoc double %c, %d
   store double %ab, double* %p1 ; extra use of %ab
   store double %cd, double* %p2 ; extra use of %cd
   store double %cd, double* %p3 ; another extra use of %cd
-  %r = fsub fast double %ab, %cd
+  %r = fsub reassoc double %ab, %cd
   ret double %r
 }
 
 define double @fma_multi_uses3(double %a, double %b, double %c, double %d, double %f, double %g, double* %p1, double* %p2, double* %p3) {
 ; CHECK-LABEL: fma_multi_uses3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-NEXT:    xsmuldp 1, 5, 6
 ; CHECK-NEXT:    ld 3, 96(1)
 ; CHECK-NEXT:    stfd 0, 0(9)
 ; CHECK-NEXT:    stfd 0, 0(10)
 ; CHECK-NEXT:    stfd 1, 0(3)
 ; CHECK-NEXT:    xsnmsubadp 1, 3, 4
 ; CHECK-NEXT:    xsnmsubadp 0, 3, 4
 ; CHECK-NEXT:    xsadddp 1, 0, 1
 ; CHECK-NEXT:    blr
-  %ab = fmul fast double %a, %b
-  %cd = fmul fast double %c, %d
-  %fg = fmul fast double %f, %g
+  %ab = fmul reassoc double %a, %b
+  %cd = fmul reassoc double %c, %d
+  %fg = fmul reassoc double %f, %g
   store double %ab, double* %p1 ; extra use of %ab
   store double %ab, double* %p2 ; another extra use of %ab
   store double %fg, double* %p3 ; extra use of %fg
-  %q = fsub fast double %fg, %cd ; The uses of %cd reduce to 1 after %r is folded. 2 uses of %fg, fold %cd, remove def of %cd
-  %r = fsub fast double %ab, %cd ; Fold %r before %q. 3 uses of %ab, 2 uses of %cd, fold %cd
-  %add = fadd fast double %r, %q
+  %q = fsub reassoc double %fg, %cd ; The uses of %cd reduce to 1 after %r is folded. 2 uses of %fg, fold %cd, remove def of %cd
+  %r = fsub reassoc double %ab, %cd ; Fold %r before %q. 3 uses of %ab, 2 uses of %cd, fold %cd
+  %add = fadd reassoc double %r, %q
   ret double %add
 }

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, %y
   %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; The fadd is now fully 'fast'. This implies that contraction is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast1:'
-; FMFDEBUG:         fma nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_fast1:'
 
 define float @fmul_fadd_fast1(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_fast1:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xsmaddasp 3, 1, 2
 ; FMF-NEXT:    fmr 1, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_fast1:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
-  %mul = fmul fast float %x, %y
-  %add = fadd fast float %mul, %z
+  %mul = fmul reassoc float %x, %y
+  %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast2:'
-; FMFDEBUG:         fma nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_fast2:'
 
 define float @fmul_fadd_fast2(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_fast2:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xsmaddasp 3, 1, 2
 ; FMF-NEXT:    fmr 1, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_fast2:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
-  %mul = fmul fast float %x, %y
-  %add = fadd fast float %mul, %z
+  %mul = fmul reassoc float %x, %y
+  %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; fma(X, 7.0, X * 42.0) --> X * 49.0
 ; This is the minimum FMF needed for this transform - the FMA allows reassociation.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
 ; FMFDEBUG:         fmul reassoc {{t[0-9]+}},
; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, 42.0
   %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; The FMA is now fully 'fast'. This implies that reassociation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast1:'
-; FMFDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast1:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast1:'
-; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast1:'
 
 define float @fmul_fma_fast1(float %x) {
 ; FMF-LABEL: fmul_fma_fast1:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; FMF-NEXT:    lfs 0, .LCPI8_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_fast1:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; GLOBAL-NEXT:    lfs 0, .LCPI8_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
   %mul = fmul float %x, 42.0
-  %fma = call fast float @llvm.fma.f32(float %x, float 7.0, float %mul)
+  %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast2:'
-; FMFDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast2:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast2:'
-; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast2:'
 
 define float @fmul_fma_fast2(float %x) {
 ; FMF-LABEL: fmul_fma_fast2:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; FMF-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_fast2:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; GLOBAL-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
-  %mul = fmul fast float %x, 42.0
-  %fma = call fast float @llvm.fma.f32(float %x, float 7.0, float %mul)
+  %mul = fmul reassoc float %x, 42.0
+  %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; Reduced precision for sqrt is allowed - should use estimate and NR iterations.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
 ; FMFDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'

 ; GLOBAL-NEXT:    blr
   %rt = call afn float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; The call is now fully 'fast'. This implies that approximation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
-; FMFDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
-; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
 ; FMF-NEXT:    fabs 0, 1
 ; FMF-NEXT:    lfs 2, .LCPI14_2@toc@l(3)

 ; GLOBAL-NEXT:    lfs 3, .LCPI14_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB14_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
-  %rt = call fast float @llvm.sqrt.f32(float %x)
+  %rt = call reassoc afn ninf float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; The call is now fully 'fast'. This implies that approximation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
-; FMFDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
-; GLOBALDEBUG:         fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 
 define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_fast_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    fcmpu 0, 1, 0
 ; FMF-NEXT:    beq 0, .LBB15_2

 ; GLOBAL-NEXT:    lfs 3, .LCPI15_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB15_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
-  %rt = call fast float @llvm.sqrt.f32(float %x)
+  %rt = call reassoc ninf afn float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; fcmp can have fast-math-flags.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
 ; FMFDEBUG:         select_cc nnan {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fcmp_nnan:'

llvm/test/CodeGen/PowerPC/load-two-flts.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-bgq-linux"
 
 define void @_Z4testSt7complexIfE(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) {
 entry:
   %v2 = load i64, i64* %ref.tmp, align 8
   %v3 = lshr i64 %v2, 32
   %v4 = trunc i64 %v3 to i32
   %v5 = bitcast i32 %v4 to float
   %v6 = trunc i64 %v2 to i32
   %v7 = bitcast i32 %v6 to float
-  %mul_ad.i.i = fmul fast float %v5, %v1
-  %mul_bc.i.i = fmul fast float %v7, %v0
-  %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i
-  %mul_ac.i.i = fmul fast float %v5, %v0
-  %mul_bd.i.i = fmul fast float %v7, %v1
-  %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i
+  %mul_ad.i.i = fmul float %v5, %v1
+  %mul_bc.i.i = fmul float %v7, %v0
+  %mul_i.i.i = fadd float %mul_ad.i.i, %mul_bc.i.i
+  %mul_ac.i.i = fmul float %v5, %v0
+  %mul_bd.i.i = fmul float %v7, %v1
+  %mul_r.i.i = fsub float %mul_ac.i.i, %mul_bd.i.i
   store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4
   store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4
   ret void
 
 ; CHECK-LABEL: @_Z4testSt7complexIfE
 ; CHECK-NOT: ld {{[0-9]+}}, 0(5)
 ; CHECK-NOT: stw
 ; CHECK-NOT: rldicl
 ; CHECK-DAG: lfs {{[0-9]+}}, 4(5)
 ; CHECK-DAG: lfs {{[0-9]+}}, 0(5)
 ; CHECK: blr
 }
 
 define i64* @_Z4testSt7complexIfE_idx(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) {
 entry:
   %r = getelementptr i64, i64* %ref.tmp, i64 1
   %v2 = load i64, i64* %r, align 8
   %v3 = lshr i64 %v2, 32
   %v4 = trunc i64 %v3 to i32
   %v5 = bitcast i32 %v4 to float
   %v6 = trunc i64 %v2 to i32
   %v7 = bitcast i32 %v6 to float
-  %mul_ad.i.i = fmul fast float %v5, %v1
-  %mul_bc.i.i = fmul fast float %v7, %v0
-  %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i
-  %mul_ac.i.i = fmul fast float %v5, %v0
-  %mul_bd.i.i = fmul fast float %v7, %v1
-  %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i
+  %mul_ad.i.i = fmul float %v5, %v1
+  %mul_bc.i.i = fmul float %v7, %v0
+  %mul_i.i.i = fadd float %mul_ad.i.i, %mul_bc.i.i
+  %mul_ac.i.i = fmul float %v5, %v0
+  %mul_bd.i.i = fmul float %v7, %v1
+  %mul_r.i.i = fsub float %mul_ac.i.i, %mul_bd.i.i
   store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4
   store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4
   ret i64* %r
 
 ; CHECK-LABEL: @_Z4testSt7complexIfE
 ; CHECK-NOT: ld {{[0-9]+}}, 8(5)
 ; CHECK-NOT: ldu {{[0-9]+}}, 8(5)
 ; CHECK-NOT: stw
 ; CHECK-NOT: rldicl
 ; CHECK-DAG: lfsu {{[0-9]+}}, 8(3)
 ; CHECK-DAG: lfs {{[0-9]+}}, 4(3)
 ; CHECK: blr
 }
 

llvm/test/CodeGen/PowerPC/pow.75.ll

 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[SQRT]]
 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]]
 ; CHECK-NEXT:  ... into: [[R]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]]
   %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 7.5e-01)
   ret double %r
 }
 
 define <4 x float> @pow_v4f32_three_fourth_fmf(<4 x float> %x) nounwind {
-; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}}
-; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]]
-; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]]
-; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]]
-; CHECK-NEXT:  ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]]
-  %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 7.5e-1, float 7.5e-1, float 7.5e-01, float 7.5e-01>)
+; CHECK: Combining: {{.*}}: v4f32 = fpow ninf afn [[X:t[0-9]+]], {{.*}}
+; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt ninf afn [[X]]
+; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt ninf afn [[SQRT]]
+; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul ninf afn [[SQRT]], [[SQRTSQRT]]
+; CHECK-NEXT:  ... into: [[R]]: v4f32 = fmul ninf afn [[SQRT]], [[SQRTSQRT]]
+  %r = call ninf afn <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 7.5e-1, float 7.5e-1, float 7.5e-01, float 7.5e-01>)
   ret <4 x float> %r
 }
 
 define <2 x double> @pow_v2f64_three_fourth_fmf(<2 x double> %x) nounwind {
-; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}}
-; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]]
-; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]]
-; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]]
-; CHECK-NEXT:  ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]]
-  %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 7.5e-1, double 7.5e-1>)
+; CHECK: Combining: {{.*}}: v2f64 = fpow ninf afn [[X:t[0-9]+]], {{.*}}
+; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt ninf afn [[X]]
+; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt ninf afn [[SQRT]]
+; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul ninf afn [[SQRT]], [[SQRTSQRT]]
+; CHECK-NEXT:  ... into: [[R]]: v2f64 = fmul ninf afn [[SQRT]], [[SQRTSQRT]]
+  %r = call ninf afn <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 7.5e-1, double 7.5e-1>)
   ret <2 x double> %r
 }

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Test with float/double/float128 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbf1(float %a, float %b) {
-  %t1 = fcmp fast olt float %a, %b
-  %t2 = fcmp fast olt float %b, %a
+  %t1 = fcmp nnan olt float %a, %b
+  %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbf1:
 ; CHECK-NOT: li
 ; CHECK: fcmpu cr0, f1, f2
 ; CHECK-NEXT: setb r3, cr0
 ; CHECK-NOT: isel
 ; CHECK-NOT: li
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbf1
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setbf2(float %a, float %b) {
-  %t1 = fcmp fast ogt float %b, %a
-  %t2 = fcmp fast olt float %b, %a
+  %t1 = fcmp nnan ogt float %b, %a
+  %t2 = fcmp nnan olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbf2:
 ; CHECK-NOT: li
 ; CHECK: fcmpu cr0, f1, f2
 ; CHECK-NEXT: setb r3, cr0
 ; CHECK-NOT: isel
 ; CHECK-NOT: li
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbf2
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setbdf1(double %a, double %b) {
-  %t1 = fcmp fast oeq double %b, %a
-  %t2 = fcmp fast ogt double %b, %a
+  %t1 = fcmp nnan oeq double %b, %a
+  %t2 = fcmp nnan ogt double %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbdf1:
 ; CHECK: xscmpudp cr0, f1, f2
 ; CHECK-NEXT: setb r3, cr0
 ; CHECK-NOT: li
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbdf1
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbdf2(double %a, double %b) {
-  %t1 = fcmp fast olt double %b, %a
-  %t2 = fcmp fast ogt double %b, %a
+  %t1 = fcmp nnan olt double %b, %a
+  %t2 = fcmp nnan ogt double %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbdf2:
 ; CHECK-NOT: fcmpu
 ; CHECK-NOT: li
 ; CHECK: xscmpudp cr0, f1, f2
 ; CHECK-NEXT: setb r3, cr0
 ; CHECK-NOT: li
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbdf2
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 define i64 @setbf128(fp128 %a, fp128 %b) {
-  %t1 = fcmp fast ogt fp128 %a, %b
-  %t2 = fcmp fast olt fp128 %a, %b
+  %t1 = fcmp nnan ogt fp128 %a, %b
+  %t2 = fcmp nnan olt fp128 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbf128:
 ; CHECK-NOT: li
 ; CHECK: xscmpuqp cr0, v2, v3
 ; CHECK-NEXT: setb r3, cr0
 ; CHECK-NOT: isel

llvm/test/CodeGen/PowerPC/qpx-recipest.ll

 ; CHECK-NEXT:    qvfnmsub 4, 2, 4, 0
 ; CHECK-NEXT:    qvfmul 3, 3, 4
 ; CHECK-NEXT:    qvfmul 4, 3, 3
 ; CHECK-NEXT:    qvfnmsub 0, 2, 4, 0
 ; CHECK-NEXT:    qvfmul 0, 3, 0
 ; CHECK-NEXT:    qvfmul 1, 1, 0
 ; CHECK-NEXT:    blr
 entry:
-  %x = call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
-  %r = fdiv fast <4 x double> %a, %x
+  %x = call ninf afn reassoc <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
+  %r = fdiv arcp reassoc <4 x double> %a, %x
   ret <4 x double> %r
 }
 
 define <4 x double> @foo_safe(<4 x double> %a, <4 x double> %b) nounwind {
 ; CHECK-LABEL: foo_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 5, 2, 3
 ; CHECK-NEXT:    qvesplati 3, 2, 1

 ; CHECK-NEXT:    qvlfsx 0, 0, 3
 ; CHECK-NEXT:    qvfmuls 4, 3, 3
 ; CHECK-NEXT:    qvfnmsubs 2, 2, 0, 2
 ; CHECK-NEXT:    qvfmadds 0, 2, 4, 0
 ; CHECK-NEXT:    qvfmuls 0, 3, 0
 ; CHECK-NEXT:    qvfmul 1, 1, 0
 ; CHECK-NEXT:    blr
 entry:
-  %x = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %x = call afn ninf reassoc <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
   %y = fpext <4 x float> %x to <4 x double>
-  %r = fdiv fast <4 x double> %a, %y
+  %r = fdiv arcp reassoc nsz <4 x double> %a, %y
   ret <4 x double> %r
 }
 
 define <4 x double> @foof_safe(<4 x double> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: foof_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 0, 2, 3
 ; CHECK-NEXT:    qvesplati 3, 2, 2

 ; CHECK-NEXT:    qvfmul 3, 3, 4
 ; CHECK-NEXT:    qvfmul 4, 3, 3
 ; CHECK-NEXT:    qvfnmsub 0, 2, 4, 0
 ; CHECK-NEXT:    qvfmul 0, 3, 0
 ; CHECK-NEXT:    qvfrsp 0, 0
 ; CHECK-NEXT:    qvfmuls 1, 1, 0
 ; CHECK-NEXT:    blr
 entry:
-  %x = call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
+  %x = call afn ninf reassoc <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
   %y = fptrunc <4 x double> %x to <4 x float>
-  %r = fdiv fast <4 x float> %a, %y
+  %r = fdiv arcp reassoc <4 x float> %a, %y
   ret <4 x float> %r
 }
 
 define <4 x float> @food_safe(<4 x float> %a, <4 x double> %b) nounwind {
 ; CHECK-LABEL: food_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 0, 2, 3
 ; CHECK-NEXT:    qvesplati 3, 2, 2

 ; CHECK-NEXT:    qvlfsx 0, 0, 3
 ; CHECK-NEXT:    qvfmuls 4, 3, 3
 ; CHECK-NEXT:    qvfnmsubs 2, 2, 0, 2
 ; CHECK-NEXT:    qvfmadds 0, 2, 4, 0
 ; CHECK-NEXT:    qvfmuls 0, 3, 0
 ; CHECK-NEXT:    qvfmuls 1, 1, 0
 ; CHECK-NEXT:    blr
 entry:
-  %x = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
-  %r = fdiv fast <4 x float> %a, %x
+  %x = call afn ninf reassoc <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %r = fdiv arcp reassoc nsz <4 x float> %a, %x
   ret <4 x float> %r
 }
 
 define <4 x float> @goo_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: goo_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 5, 2, 3
 ; CHECK-NEXT:    qvesplati 3, 2, 1

 ; CHECK-NEXT:    qvlfdx 0, 0, 3
 ; CHECK-NEXT:    qvfmadd 0, 2, 3, 0
 ; CHECK-NEXT:    qvfnmsub 0, 3, 0, 3
 ; CHECK-NEXT:    qvfmul 3, 1, 0
 ; CHECK-NEXT:    qvfnmsub 1, 2, 3, 1
 ; CHECK-NEXT:    qvfmadd 1, 0, 1, 3
 ; CHECK-NEXT:    blr
 entry:
-  %r = fdiv fast <4 x double> %a, %b
+  %r = fdiv arcp reassoc nsz <4 x double> %a, %b
   ret <4 x double> %r
 }
 
 define <4 x double> @foo2_safe(<4 x double> %a, <4 x double> %b) nounwind {
 ; CHECK-LABEL: foo2_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    qvesplati 3, 2, 3
 ; CHECK-NEXT:    qvesplati 4, 1, 3

 ; CHECK-LABEL: goo2_fmf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvfres 0, 2
 ; CHECK-NEXT:    qvfmuls 3, 1, 0
 ; CHECK-NEXT:    qvfnmsubs 1, 2, 3, 1
 ; CHECK-NEXT:    qvfmadds 1, 0, 1, 3
 ; CHECK-NEXT:    blr
 entry:
-  %r = fdiv fast <4 x float> %a, %b
+  %r = fdiv arcp reassoc <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @goo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: goo2_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 3, 2, 3
 ; CHECK-NEXT:    qvesplati 4, 1, 3

 ; CHECK-NEXT:    addi 3, 3, .LCPI12_2@toc@l
 ; CHECK-NEXT:    qvlfdx 3, 0, 3
 ; CHECK-NEXT:    qvfmul 0, 0, 1
 ; CHECK-NEXT:    qvfabs 1, 1
 ; CHECK-NEXT:    qvfcmplt 1, 1, 2
 ; CHECK-NEXT:    qvfsel 1, 1, 3, 0
 ; CHECK-NEXT:    blr
 entry:
-  %r = call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
+  %r = call reassoc ninf afn <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
   ret <4 x double> %r
 }
 
 define <4 x double> @foo3_fmf_denorm_off(<4 x double> %a) #1 {
 ; CHECK-LABEL: foo3_fmf_denorm_off:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
 ; CHECK-NEXT:    qvfrsqrte 0, 1

 ; CHECK-NEXT:    qvfnmsub 2, 4, 3, 2
 ; CHECK-NEXT:    qvfmul 0, 0, 2
 ; CHECK-NEXT:    qvlfdx 2, 0, 3
 ; CHECK-NEXT:    qvfmul 0, 0, 1
 ; CHECK-NEXT:    qvfcmpeq 1, 1, 2
 ; CHECK-NEXT:    qvfsel 1, 1, 2, 0
 ; CHECK-NEXT:    blr
 entry:
-  %r = call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
+  %r = call afn reassoc ninf <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
   ret <4 x double> %r
 }
 
 define <4 x double> @foo3_safe_denorm_on(<4 x double> %a) #0 {
 ; CHECK-LABEL: foo3_safe_denorm_on:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 2, 1, 3
 ; CHECK-NEXT:    qvesplati 3, 1, 2

 ; CHECK-NEXT:    qvlfsx 4, 0, 3
 ; CHECK-NEXT:    qvfmuls 0, 2, 0
 ; CHECK-NEXT:    qvfabs 2, 1
 ; CHECK-NEXT:    qvfmuls 0, 0, 1
 ; CHECK-NEXT:    qvfcmplt 1, 2, 3
 ; CHECK-NEXT:    qvfsel 1, 1, 4, 0
 ; CHECK-NEXT:    blr
 entry:
-  %r = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+  %r = call reassoc afn ninf nsz <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @goo3_fmf_denorm_off(<4 x float> %a) #1 {
 ; CHECK-LABEL: goo3_fmf_denorm_off:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_1@toc@ha
 ; CHECK-NEXT:    qvfrsqrtes 2, 1
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_1@toc@l
 ; CHECK-NEXT:    qvlfsx 0, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
 ; CHECK-NEXT:    qvfmuls 4, 2, 2
 ; CHECK-NEXT:    qvfnmsubs 3, 1, 0, 1
 ; CHECK-NEXT:    qvfmadds 0, 3, 4, 0
 ; CHECK-NEXT:    qvlfsx 3, 0, 3
 ; CHECK-NEXT:    qvfmuls 0, 2, 0
 ; CHECK-NEXT:    qvfmuls 0, 0, 1
 ; CHECK-NEXT:    qvfcmpeq 1, 1, 3
 ; CHECK-NEXT:    qvfsel 1, 1, 3, 0
 ; CHECK-NEXT:    blr
 entry:
-  %r = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+  %r = call reassoc ninf afn nsz <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @goo3_safe(<4 x float> %a) nounwind {
 ; CHECK-LABEL: goo3_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 2, 1, 3
 ; CHECK-NEXT:    qvesplati 3, 1, 2

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-NEXT:    fmul 0, 0, 5
 ; CHECK-NEXT:    fmul 0, 0, 3
 ; CHECK-NEXT:    fmul 2, 2, 0
 ; CHECK-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-NEXT:    fmul 0, 0, 5
 ; CHECK-NEXT:    fmul 0, 0, 2
 ; CHECK-NEXT:    fmul 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast double @llvm.sqrt.f64(double %b)
-  %r = fdiv fast double %a, %x
+  %x = call arcp reassoc double @llvm.sqrt.f64(double %b)
+  %r = fdiv arcp reassoc double %a, %x
   ret double %r
 }
 
 define double @foo_safe(double %a, double %b) nounwind {
 ; CHECK-LABEL: foo_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrt 0, 2
 ; CHECK-NEXT:    fdiv 1, 1, 0
 ; CHECK-NEXT:    blr
   %x = call double @llvm.sqrt.f64(double %b)
   %r = fdiv double %a, %x
   ret double %r
 }
 
 define double @no_estimate_refinement_f64(double %a, double %b) #0 {
 ; CHECK-LABEL: no_estimate_refinement_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frsqrte 0, 2
 ; CHECK-NEXT:    fmul 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast double @llvm.sqrt.f64(double %b)
-  %r = fdiv fast double %a, %x
+  %x = call arcp reassoc double @llvm.sqrt.f64(double %b)
+  %r = fdiv arcp reassoc double %a, %x
   ret double %r
 }
 
 define double @foof_fmf(double %a, float %b) nounwind {
 ; CHECK-LABEL: foof_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frsqrtes 0, 2
 ; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
 ; CHECK-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
 ; CHECK-NEXT:    lfs 4, .LCPI3_1@toc@l(4)
 ; CHECK-NEXT:    fmuls 2, 2, 0
 ; CHECK-NEXT:    fmadds 2, 2, 0, 3
 ; CHECK-NEXT:    fmuls 0, 0, 4
 ; CHECK-NEXT:    fmuls 0, 0, 2
 ; CHECK-NEXT:    fmul 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast float @llvm.sqrt.f32(float %b)
+  %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
   %y = fpext float %x to double
-  %r = fdiv fast double %a, %y
+  %r = fdiv reassoc arcp double %a, %y
   ret double %r
 }
 
 define double @foof_safe(double %a, float %b) nounwind {
 ; CHECK-LABEL: foof_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrts 0, 2
 ; CHECK-NEXT:    fdiv 1, 1, 0

 ; CHECK-NEXT:    fmul 0, 0, 3
 ; CHECK-NEXT:    fmul 2, 2, 0
 ; CHECK-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-NEXT:    fmul 0, 0, 5
 ; CHECK-NEXT:    fmul 0, 0, 2
 ; CHECK-NEXT:    frsp 0, 0
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast double @llvm.sqrt.f64(double %b)
+  %x = call reassoc arcp double @llvm.sqrt.f64(double %b)
   %y = fptrunc double %x to float
-  %r = fdiv fast float %a, %y
+  %r = fdiv reassoc arcp float %a, %y
   ret float %r
 }
 
 define float @food_safe(float %a, double %b) nounwind {
 ; CHECK-LABEL: food_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrt 0, 2
 ; CHECK-NEXT:    frsp 0, 0

 ; CHECK-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
 ; CHECK-NEXT:    lfs 4, .LCPI7_1@toc@l(4)
 ; CHECK-NEXT:    fmuls 2, 2, 0
 ; CHECK-NEXT:    fmadds 2, 2, 0, 3
 ; CHECK-NEXT:    fmuls 0, 0, 4
 ; CHECK-NEXT:    fmuls 0, 0, 2
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast float @llvm.sqrt.f32(float %b)
-  %r = fdiv fast float %a, %x
+  %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
+  %r = fdiv reassoc arcp float %a, %x
   ret float %r
 }
 
 define float @goo_safe(float %a, float %b) nounwind {
 ; CHECK-LABEL: goo_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrts 0, 2
 ; CHECK-NEXT:    fdivs 1, 1, 0
 ; CHECK-NEXT:    blr
   %x = call float @llvm.sqrt.f32(float %b)
   %r = fdiv float %a, %x
   ret float %r
 }
 
 define float @no_estimate_refinement_f32(float %a, float %b) #0 {
 ; CHECK-LABEL: no_estimate_refinement_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frsqrtes 0, 2
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    blr
-  %x = call fast float @llvm.sqrt.f32(float %b)
-  %r = fdiv fast float %a, %x
+  %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
+  %r = fdiv reassoc arcp float %a, %x
   ret float %r
 }
 
 ; Recognize that this is rsqrt(a) * rcp(b) * c,
 ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
 define float @rsqrt_fmul_fmf(float %a, float %b, float %c) {
 ; CHECK-LABEL: rsqrt_fmul_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frsqrtes 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
 ; CHECK-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
 ; CHECK-NEXT:    lfs 5, .LCPI10_1@toc@l(4)
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    fmadds 1, 1, 0, 4
 ; CHECK-NEXT:    fmuls 0, 0, 5
 ; CHECK-NEXT:    fmuls 0, 0, 1
 ; CHECK-NEXT:    fres 1, 2
 ; CHECK-NEXT:    fmuls 4, 0, 1
 ; CHECK-NEXT:    fnmsubs 0, 2, 4, 0
 ; CHECK-NEXT:    fmadds 0, 1, 0, 4
 ; CHECK-NEXT:    fmuls 1, 3, 0
 ; CHECK-NEXT:    blr
-  %x = call fast float @llvm.sqrt.f32(float %a)
-  %y = fmul fast float %x, %b
-  %z = fdiv fast float %c, %y
+  %x = call reassoc arcp float @llvm.sqrt.f32(float %a)
+  %y = fmul reassoc float %x, %b
+  %z = fdiv reassoc arcp float %c, %y
   ret float %z
 }
 
 ; Recognize that this is rsqrt(a) * rcp(b) * c,
 ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
 define float @rsqrt_fmul_safe(float %a, float %b, float %c) {
 ; CHECK-LABEL: rsqrt_fmul_safe:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    lvx 1, 0, 3
 ; CHECK-NEXT:    vslw 4, 4, 4
 ; CHECK-NEXT:    vmaddfp 3, 3, 5, 4
 ; CHECK-NEXT:    vmaddfp 3, 3, 5, 0
 ; CHECK-NEXT:    vmaddfp 5, 5, 1, 4
 ; CHECK-NEXT:    vmaddfp 3, 5, 3, 4
 ; CHECK-NEXT:    vmaddfp 2, 2, 3, 4
 ; CHECK-NEXT:    blr
-  %x = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
-  %r = fdiv fast <4 x float> %a, %x
+  %x = call reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %r = fdiv reassoc arcp <4 x float> %a, %x
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: hoo_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 3, 1, -32
 ; CHECK-NEXT:    stvx 3, 0, 3

 ; CHECK-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
 ; CHECK-NEXT:    lfs 3, .LCPI14_0@toc@l(3)
 ; CHECK-NEXT:    fmadd 3, 2, 0, 3
 ; CHECK-NEXT:    fnmsub 0, 0, 3, 0
 ; CHECK-NEXT:    fmul 3, 1, 0
 ; CHECK-NEXT:    fnmsub 1, 2, 3, 1
 ; CHECK-NEXT:    fmadd 1, 0, 1, 3
 ; CHECK-NEXT:    blr
-  %r = fdiv fast double %a, %b
+  %r = fdiv reassoc arcp nsz double %a, %b
   ret double %r
 }
 
 define double @foo2_safe(double %a, double %b) nounwind {
 ; CHECK-LABEL: foo2_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fdiv 1, 1, 2
 ; CHECK-NEXT:    blr
   %r = fdiv double %a, %b
   ret double %r
 }
 
 define float @goo2_fmf(float %a, float %b) nounwind {
 ; CHECK-LABEL: goo2_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fres 0, 2
 ; CHECK-NEXT:    fmuls 3, 1, 0
 ; CHECK-NEXT:    fnmsubs 1, 2, 3, 1
 ; CHECK-NEXT:    fmadds 1, 0, 1, 3
 ; CHECK-NEXT:    blr
-  %r = fdiv fast float %a, %b
+  %r = fdiv reassoc arcp float %a, %b
   ret float %r
 }
 
 define float @goo2_safe(float %a, float %b) nounwind {
 ; CHECK-LABEL: goo2_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fdivs 1, 1, 2
 ; CHECK-NEXT:    blr

 ; CHECK-NEXT:    vspltisb 0, -1
 ; CHECK-NEXT:    vslw 0, 0, 0
 ; CHECK-NEXT:    vslw 4, 4, 4
 ; CHECK-NEXT:    vsubfp 3, 0, 3
 ; CHECK-NEXT:    vmaddfp 4, 2, 5, 4
 ; CHECK-NEXT:    vmaddfp 2, 3, 4, 2
 ; CHECK-NEXT:    vmaddfp 2, 5, 2, 4
 ; CHECK-NEXT:    blr
-  %r = fdiv fast <4 x float> %a, %b
+  %r = fdiv reassoc arcp <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: hoo2_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 3, 1, -32
 ; CHECK-NEXT:    addi 4, 1, -48

 ; CHECK-NEXT:    fmadd 0, 1, 0, 3
 ; CHECK-NEXT:    fmul 1, 1, 4
 ; CHECK-NEXT:    fmul 1, 1, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB20_2:
 ; CHECK-NEXT:    addis 3, 2, .LCPI20_3@toc@ha
 ; CHECK-NEXT:    lfs 1, .LCPI20_3@toc@l(3)
 ; CHECK-NEXT:    blr
-  %r = call fast double @llvm.sqrt.f64(double %a)
+  %r = call reassoc ninf afn double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_safe(double %a) nounwind {
 ; CHECK-LABEL: foo3_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrt 1, 1
 ; CHECK-NEXT:    blr

 ; CHECK-NEXT:    fmadds 0, 1, 0, 2
 ; CHECK-NEXT:    fmuls 1, 1, 3
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB22_2:
 ; CHECK-NEXT:    addis 3, 2, .LCPI22_3@toc@ha
 ; CHECK-NEXT:    lfs 1, .LCPI22_3@toc@l(3)
 ; CHECK-NEXT:    blr
-  %r = call fast float @llvm.sqrt.f32(float %a)
+  %r = call reassoc ninf afn float @llvm.sqrt.f32(float %a)
   ret float %r
 }
 
 define float @goo3_safe(float %a) nounwind {
 ; CHECK-LABEL: goo3_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrts 1, 1
 ; CHECK-NEXT:    blr

 ; CHECK-NEXT:    vmaddfp 5, 2, 4, 3
 ; CHECK-NEXT:    vmaddfp 4, 5, 4, 0
 ; CHECK-NEXT:    vmaddfp 5, 5, 1, 3
 ; CHECK-NEXT:    vxor 0, 0, 0
 ; CHECK-NEXT:    vmaddfp 3, 5, 4, 3
 ; CHECK-NEXT:    vcmpeqfp 2, 2, 0
 ; CHECK-NEXT:    vsel 2, 3, 0, 2
 ; CHECK-NEXT:    blr
-  %r = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+  %r = call reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo3_safe(<4 x float> %a) nounwind {
 ; CHECK-LABEL: hoo3_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 3, 1, -32
 ; CHECK-NEXT:    stvx 2, 0, 3

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; CHECK-NEXT:    xvresp 1, 0
 ; CHECK-NEXT:    xvmaddasp 35, 0, 1
 ; CHECK-NEXT:    xvmulsp 0, 34, 36
 ; CHECK-NEXT:    xvnmsubasp 1, 1, 35
 ; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
-  %t1 = fmul fast <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
-  %mul = fdiv fast <4 x float> %t1, %splat
+  %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
+  %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 

llvm/test/CodeGen/PowerPC/scalar-equal.ll

 ; NO-FAST-P8:       # %bb.0: # %entry
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    beqlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f4
 ; NO-FAST-P8-NEXT:    blr
 entry:
-  %cmp = fcmp fast oeq double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp oeq double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }

llvm/test/CodeGen/PowerPC/scalar-min-max.ll

 ; NO-FAST-P8-LABEL: testfmax_fast:
 ; NO-FAST-P8:       # %bb.0: # %entry
 ; NO-FAST-P8-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P8-NEXT:    bgtlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    blr
 entry:
-  %cmp = fcmp fast ogt float %a, %b
+  %cmp = fcmp ogt float %a, %b
   %cond = select i1 %cmp, float %a, float %b
   ret float %cond
 }
 define dso_local double @testdmax_fast(double %a, double %b) local_unnamed_addr {
 ; CHECK-LABEL: testdmax_fast:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmaxdp f1, f1, f2
 ; CHECK-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: testdmax_fast:
 ; NO-FAST-P9:       # %bb.0: # %entry
 ; NO-FAST-P9-NEXT:    xsmaxcdp f1, f1, f2
 ; NO-FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: testdmax_fast:
 ; NO-FAST-P8:       # %bb.0: # %entry
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P8-NEXT:    bgtlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    blr
 entry:
-  %cmp = fcmp fast ogt double %a, %b
+  %cmp = fcmp ogt double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 }
 define dso_local float @testfmin_fast(float %a, float %b) local_unnamed_addr {
 ; CHECK-LABEL: testfmin_fast:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmindp f1, f1, f2
 ; CHECK-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: testfmin_fast:
 ; NO-FAST-P9:       # %bb.0: # %entry
 ; NO-FAST-P9-NEXT:    xsmincdp f1, f1, f2
 ; NO-FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: testfmin_fast:
 ; NO-FAST-P8:       # %bb.0: # %entry
 ; NO-FAST-P8-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P8-NEXT:    bltlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    blr
 entry:
-  %cmp = fcmp fast olt float %a, %b
+  %cmp = fcmp olt float %a, %b
   %cond = select i1 %cmp, float %a, float %b
   ret float %cond
 }
 define dso_local double @testdmin_fast(double %a, double %b) local_unnamed_addr {
 ; CHECK-LABEL: testdmin_fast:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmindp f1, f1, f2
 ; CHECK-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: testdmin_fast:
 ; NO-FAST-P9:       # %bb.0: # %entry
 ; NO-FAST-P9-NEXT:    xsmincdp f1, f1, f2
 ; NO-FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: testdmin_fast:
 ; NO-FAST-P8:       # %bb.0: # %entry
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P8-NEXT:    bltlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    blr
 entry:
-  %cmp = fcmp fast olt double %a, %b
+  %cmp = fcmp olt double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 }

llvm/test/CodeGen/PowerPC/scalar_cmp.ll

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    beq cr0, .LBB2_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB2_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast oeq float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp oeq float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_oeq_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_oeq_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f1, f2
 ; FAST-P8-NEXT:    xsnegdp f1, f0

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    beq cr0, .LBB3_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB3_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast oeq double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp oeq double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 
 ; Test one
 define float @select_one_float(float %a, float %b, float %c, float %d) {
 ; FAST-P8-LABEL: select_one_float:
 ; FAST-P8:       # %bb.0: # %entry

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bne cr0, .LBB6_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB6_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast one float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp nnan one float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_one_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_one_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f1, f2
 ; FAST-P8-NEXT:    xsnegdp f1, f0

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bne cr0, .LBB7_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB7_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast one double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp nnan one double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 
 ; Test oge
 define float @select_oge_float(float %a, float %b, float %c, float %d) {
 ; FAST-P8-LABEL: select_oge_float:
 ; FAST-P8:       # %bb.0: # %entry

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bge cr0, .LBB10_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB10_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast oge float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp nnan oge float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_oge_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_oge_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f1, f2
 ; FAST-P8-NEXT:    fsel f1, f0, f3, f4

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bge cr0, .LBB11_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB11_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast oge double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp nnan oge double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 
 ; Test olt
 define float @select_olt_float(float %a, float %b, float %c, float %d) {
 ; FAST-P8-LABEL: select_olt_float:
 ; FAST-P8:       # %bb.0: # %entry

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    blt cr0, .LBB14_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB14_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast olt float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp olt float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_olt_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_olt_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f1, f2
 ; FAST-P8-NEXT:    fsel f1, f0, f4, f3

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    blt cr0, .LBB15_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB15_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast olt double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp olt double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 
 ; Test ogt
 define float @select_ogt_float(float %a, float %b, float %c, float %d) {
 ; FAST-P8-LABEL: select_ogt_float:
 ; FAST-P8:       # %bb.0: # %entry

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bgt cr0, .LBB18_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB18_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast ogt float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp ogt float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_ogt_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_ogt_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f2, f1
 ; FAST-P8-NEXT:    fsel f1, f0, f4, f3

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    bgt cr0, .LBB19_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB19_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast ogt double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp ogt double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 
 ; Test ole
 define float @select_ole_float(float %a, float %b, float %c, float %d) {
 ; FAST-P8-LABEL: select_ole_float:
 ; FAST-P8:       # %bb.0: # %entry

 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f2
 ; NO-FAST-P9-NEXT:    ble cr0, .LBB22_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB22_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast ole float %a, %b
-  %cond = select fast i1 %cmp, float %c, float %d
+  %cmp = fcmp nnan ole float %a, %b
+  %cond = select i1 %cmp, float %c, float %d
   ret float %cond
 }
 
 define double @select_fast_ole_double(double %a, double %b, double %c, double %d) {
 ; FAST-P8-LABEL: select_fast_ole_double:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    xssubdp f0, f2, f1
 ; FAST-P8-NEXT:    fsel f1, f0, f3, f4

 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f2
 ; NO-FAST-P9-NEXT:    ble cr0, .LBB23_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f4
 ; NO-FAST-P9-NEXT:  .LBB23_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
-  %cmp = fcmp fast ole double %a, %b
-  %cond = select fast i1 %cmp, double %c, double %d
+  %cmp = fcmp nnan ole double %a, %b
+  %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 ; Test RHS is 1.000000e+00
 define double @onecmp1(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp1:
 ; FAST-P8:       # %bb.0: # %entry
 ; FAST-P8-NEXT:    addis r3, r2, .LCPI24_0@toc@ha

llvm/test/CodeGen/PowerPC/vec-min-max.ll

 ; CHECK-NEXT:    xvmaxsp 34, 34, 35
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsmaxf32:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xvmaxsp 34, 34, 35
 ; NOP8VEC-NEXT:    blr
 entry:
-  %0 = fcmp fast oge <4 x float> %a, %b
+  %0 = fcmp nnan nsz oge <4 x float> %a, %b
   %1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
 }
 
 define <2 x double> @getsmaxf64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: getsmaxf64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xvmaxdp 34, 34, 35
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsmaxf64:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xvmaxdp 34, 34, 35
 ; NOP8VEC-NEXT:    blr
 entry:
-  %0 = fcmp fast oge <2 x double> %a, %b
+  %0 = fcmp nnan nsz oge <2 x double> %a, %b
   %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
   ret <2 x double> %1
 }
 
 define <16 x i8> @getsmini8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: getsmini8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vminsb 2, 2, 3

 ; CHECK-NEXT:    xvminsp 34, 34, 35
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsminf32:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xvminsp 34, 34, 35
 ; NOP8VEC-NEXT:    blr
 entry:
-  %0 = fcmp fast ole <4 x float> %a, %b
+  %0 = fcmp nnan nsz ole <4 x float> %a, %b
   %1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
   ret <4 x float> %1
 }
 
 define <2 x double> @getsminf64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: getsminf64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xvmindp 34, 34, 35
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsminf64:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xvmindp 34, 34, 35
 ; NOP8VEC-NEXT:    blr
 entry:
-  %0 = fcmp fast ole <2 x double> %a, %b
+  %0 = fcmp nnan nsz ole <2 x double> %a, %b
   %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
   ret <2 x double> %1
 }
 
 define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
 ; CHECK-LABEL: invalidv1i128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mfvsrd 3, 36

llvm/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define void @LSH_recall_init(float %d_min, float %W) #0 {
 entry:
   br i1 undef, label %for.body.lr.ph, label %for.end
 
 ; CHECK-LABEL: @LSH_recall_init
 ; CHECK: xsmaddadp
 
 for.body.lr.ph:                                   ; preds = %entry
   %conv3 = fpext float %W to double
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
-  %div = fdiv fast float 0.000000e+00, %W
-  %add = fadd fast float %div, %d_min
+  %div = fdiv reassoc arcp float 0.000000e+00, %W
+  %add = fadd reassoc float %div, %d_min
   %conv2 = fpext float %add to double
   %0 = tail call double @llvm.sqrt.f64(double %conv2)
-  %div4 = fdiv fast double %conv3, %0
+  %div4 = fdiv reassoc arcp double %conv3, %0
   %call = tail call signext i32 bitcast (i32 (...)* @p_col_helper to i32 (double)*)(double %div4) #2
   br label %for.body
 
 for.end:                                          ; preds = %entry
   ret void
 }
 
 ; Function Attrs: nounwind readnone
 declare double @llvm.sqrt.f64(double) #1
 
 declare signext i32 @p_col_helper(...) #2
 
 attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="pwr7" "unsafe-fp-math"="true" }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind }
 

llvm/test/CodeGen/PowerPC/vsx-recip-est.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
 @a = global float 3.000000e+00, align 4
 @b = global float 4.000000e+00, align 4
 @c = global double 3.000000e+00, align 8
 @d = global double 4.000000e+00, align 8
 
 ; Function Attrs: nounwind
 define float @emit_xsresp() {
 entry:
   %0 = load float, float* @a, align 4
   %1 = load float, float* @b, align 4
-  %div = fdiv fast float %0, %1
+  %div = fdiv arcp float %0, %1
   ret float %div
 ; CHECK-LABEL: @emit_xsresp
 ; CHECK: xsresp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define float @emit_xsrsqrtesp(float %f) {
 entry:
   %f.addr = alloca float, align 4
   store float %f, float* %f.addr, align 4
   %0 = load float, float* %f.addr, align 4
   %1 = load float, float* @b, align 4
   %2 = call float @llvm.sqrt.f32(float %1)
-  %div = fdiv fast float %0, %2
+  %div = fdiv arcp float %0, %2
   ret float %div
 ; CHECK-LABEL: @emit_xsrsqrtesp
 ; CHECK: xsrsqrtesp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind readnone
 declare float @llvm.sqrt.f32(float)
 
 ; Function Attrs: nounwind
 define double @emit_xsredp() {
 entry:
   %0 = load double, double* @c, align 8
   %1 = load double, double* @d, align 8
-  %div = fdiv fast double %0, %1
+  %div = fdiv arcp double %0, %1
   ret double %div
 ; CHECK-LABEL: @emit_xsredp
 ; CHECK: xsredp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define double @emit_xsrsqrtedp(double %f) {
 entry:
   %f.addr = alloca double, align 8
   store double %f, double* %f.addr, align 8
   %0 = load double, double* %f.addr, align 8
   %1 = load double, double* @d, align 8
   %2 = call double @llvm.sqrt.f64(double %1)
-  %div = fdiv fast double %0, %2
+  %div = fdiv arcp double %0, %2
   ret double %div
 ; CHECK-LABEL: @emit_xsrsqrtedp
 ; CHECK: xsrsqrtedp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind readnone
 declare double @llvm.sqrt.f64(double) #1