[AMDGPU][CODEGEN] Added 'A' constraint for inline assembler

[dp]

Summary

The 'A' constraint requires an integer or a floating-point inline constant.

[arsenm]

llvm/docs/LangRef.rst

4053 ↗

(On Diff #258731)

Shouldn't this be any inline immediate, which includes the FP values (plus the subtarget dependent one)

llvm/test/CodeGen/AMDGPU/inline-constraints.ll

100

FP value tests including the subtarget dependent inv 2pi one?

[arsenm]

I also assume this needs a clang part?

[dp]

llvm/docs/LangRef.rst

4053 ↗

(On Diff #258731)

Probably should. But GCC actually supports about 30 constraints which we do not.

I'm not sure how easy it will be to add fp constants because llvm's C_Immediate is for integers only. I'll take a look.

[arsenm]

llvm/docs/LangRef.rst

4053 ↗

(On Diff #258731)

The type doesn't matter. The bit values should still work as integers. It doesn't need to be FP

[dp]

llvm/docs/LangRef.rst

4053 ↗

(On Diff #258731)

Ok, thanks!

[dp]

Added support of fp inline constants. Clang part and documentation will be updated by a separate change.

[dp]

Corrected documentation.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

1319

No else after return

llvm/test/CodeGen/AMDGPU/inline-constraints.ll

299

can you also add some tests for packed <2 x i16>/<2 x half> operands

[dp]

Corrected code style; added support of v2x16 types.

[dp]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10735

Should we enforce this limitation? GCC seems to allow arbitrary vector size and type provided that all elements are equal and may be inlined.

[dp]

What issues do you see in this change? Thanks.

[arsenm]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10735

You mean it also accepts <4 x i8> because it's a 32-bit type?

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

1429–1431

Logic doesn't make sense here? Returns the 64-bit value if it's 16 or 32?

1434–1443

I wouldn't expect any FP rounding in the assembler

[dp]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10735

I was wrong about GCC 'vectors'. Looks like they are not regular types and used only for auto-vectorization.

Here is the GCC implementation:

(define_constraint "A"
  "Inline immediate parameter"
  (and (match_code "const_int,const_double,const_vector")
       (match_test "gcn_inline_constant_p (op)")))

...

bool
gcn_inline_constant_p (rtx x)
{
  if (GET_CODE (x) == CONST_INT)
    return INTVAL (x) >= -16 && INTVAL (x) <= 64;
  if (GET_CODE (x) == CONST_DOUBLE)
    return gcn_inline_fp_constant_p (x, false);
  if (GET_CODE (x) == CONST_VECTOR)
    {
      int n;
      if (!vgpr_vector_mode_p (GET_MODE (x)))
	return false;
      n = gcn_inline_constant_p (CONST_VECTOR_ELT (x, 0));
      if (!n)
	return false;
      for (int i = 1; i < 64; i++)
	if (CONST_VECTOR_ELT (x, i) != CONST_VECTOR_ELT (x, 0))
	  return false;
      return 1;
    }
  return false;
}

...

inline bool
vgpr_vector_mode_p (machine_mode mode)
{
  return (mode == V64QImode || mode == V64HImode
	  || mode == V64SImode || mode == V64DImode
	  || mode == V64HFmode || mode == V64SFmode || mode == V64DFmode);
}

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

1429–1431

When working on this fix I was under an impression that types of values passed to inline assembler are not required to match instruction operand types. In other words, I assumed that the following code is legal:

"v_mov_b32 $0, $1", "=v,A"(half 0xH3C00) // 1.0h

Also I assumed that this code required a type conversion to end up as "v_mov_b32 ..., 1.0" and not "v_mov_b32 ..., 0x3C00" because in the latter case the constant cannot be encoded as inline value.

That assumption complicated implementation. Was the assumption incorrect?

If types of values passed to inline assembler are required to match types of corresponding assembler operands, the implementation would be much simpler.

1434–1443

See my comments above.

[arsenm]

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

1429–1431

We have to use 32-bit instruction to materialize 16-bit values. This should be zero extended. This should end up as v_mov_b32 $0, 0x00003c00. For some cases we don't currently use in codegen, (and I'm not sure are supported by the assembler), some 64-bit operands accept 32-bit literals which are zero extended

[dp]

Updated after a discussion with Matt.

[arsenm]

I guess the fundamental problem for the 16-bit immediate case is you can't know the use instruction's context. You're really accepting something that's not an inline immediate in the use context, but you have no way of knowing that.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10741

This should be getZExtValue? It looks like the tests worked correctly here, but not sure why it didn't matter

[arsenm]

In D78494#2049119, @arsenm wrote:

I guess the fundamental problem for the 16-bit immediate case is you can't know the use instruction's context. You're really accepting something that's not an inline immediate in the use context, but you have no way of knowing that.

Actually, could we emit an error in the MC layer if it turns out to not be used in a 16-bit context? That would make more sense, but we don't have a way of tracking the immediate size

[dp]

I guess the fundamental problem for the 16-bit immediate case is you can't know the use instruction's context. You're really accepting something that's not an inline immediate in the use context, but you have no way of knowing that.

I believe this is a generic problem which affects all supported types because of unknown context.
In the previous version of this change I tried to alleviate this problem by emitting all fp constants as double so they would work in any context.
As you have pointed out, this is unsuitable in some cases where the constant type is importand but for these cases we could have used a 'B' constraint:

"v_mov_b32 $0, $1", "=v,B"(half 0xH3C00)

However I think the corrent version of this change is simpler and cleaner and it has its logic.
We expect constant type to match assembler operand type, but in the end it is up to programmer to decide how to use the constant in assembly code.

Actually, could we emit an error in the MC layer if it turns out to not be used in a 16-bit context? That would make more sense, but we don't have a way of tracking the immediate size

Agree, I do not see how this can be done.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10741

This does not really matter because isInlinableLiteralXX truncates input value to XX bits before checking.
However getting sign-extended values is useful to easily recognize negative integer constants and get prettier output.

Consider this code (actually a corner case):

... asm "v_mov_b32 $0, $1", "=v,A"(half bitcast (i16 -1 to half))

Currently the code ends up as

v_mov_b32 v0, -1

If we replace getSExtValue with getZExtValue, the result would be

v_mov_b32 v0, 0xFFFF

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
   }
 
   // TODO: Should be able to support other operand types like globals.
   const MachineOperand &MO = MI->getOperand(OpNo);
   if (MO.isReg()) {
     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
                                        *MF->getSubtarget().getRegisterInfo());
     return false;
+  } else if (MO.isImm()) {
+    int64_t Val = MO.getImm();
+    if (isInlineAsmConst(Val)) {
+      printInlineAsmConst(Val, O);
+      return false;
+    } else { // A literal
+      O << Val;
+      return false;
+    }
   }
-
   return true;
 }

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

public:
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 };
 
+namespace AMDGPU {
+
+void printInlineAsmConst(uint64_t Imm, raw_ostream &O);
+
+} // End namespace AMDGPU
+
 } // End namespace llvm
 
 #endif

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

else if (Imm == FloatToBits(-4.0f))
     O << "-4.0";
   else if (Imm == 0x3e22f983 &&
            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
     O << "0.15915494";
   else
     O << formatHex(static_cast<uint64_t>(Imm));
 }
 
-void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
-                                         const MCSubtargetInfo &STI,
-                                         raw_ostream &O) {
+static bool printInlineConst64(uint64_t Imm, raw_ostream &O, bool HasInv2Pi) {
   int64_t SImm = static_cast<int64_t>(Imm);
   if (SImm >= -16 && SImm <= 64) {
     O << SImm;
-    return;
+    return true;
   }
 
   if (Imm == DoubleToBits(0.0))
     O << "0.0";
   else if (Imm == DoubleToBits(1.0))
     O << "1.0";
   else if (Imm == DoubleToBits(-1.0))
     O << "-1.0";
   else if (Imm == DoubleToBits(0.5))
     O << "0.5";
   else if (Imm == DoubleToBits(-0.5))
     O << "-0.5";
   else if (Imm == DoubleToBits(2.0))
     O << "2.0";
   else if (Imm == DoubleToBits(-2.0))
     O << "-2.0";
   else if (Imm == DoubleToBits(4.0))
     O << "4.0";
   else if (Imm == DoubleToBits(-4.0))
     O << "-4.0";
-  else if (Imm == 0x3fc45f306dc9c882 &&
-           STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+  else if (Imm == 0x3fc45f306dc9c882 && HasInv2Pi)
     O << "0.15915494309189532";
   else {
+    return false;
+  }
+  return true;
+}
+
+void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
+  bool HasInv2Pi = STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
+  if (!printInlineConst64(Imm, O, HasInv2Pi)) {
     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
 
     // In rare situations, we will have a 32-bit literal in a 64-bit
     // operand. This is technically allowed for the encoding of s_mov_b64.
     O << formatHex(static_cast<uint64_t>(Imm));
   }
 }
 
+namespace llvm {
+namespace AMDGPU {
+
+void printInlineAsmConst(uint64_t Imm, raw_ostream &O) {
+  printInlineConst64(Imm, O, true);
+}
+
+} // End namespace AMDGPU
+} // End namespace llvm
+
 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI,
                                   raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (!Imm)
     return;
 
   O << " blgp:" << Imm;

llvm/lib/Target/AMDGPU/SIISelLowering.h

public:
   MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
                                 SDValue Ptr) const;
   MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
                            uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
   ConstraintType getConstraintType(StringRef Constraint) const override;
+  void LowerAsmOperandForConstraint(SDValue Op,
+                                    std::string &Constraint,
+                                    std::vector<SDValue> &Ops,
+                                    SelectionDAG &DAG) const override;
   SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
                    SDValue V) const;
 
   void finalizeLowering(MachineFunction &MF) const override;
 
   void computeKnownBitsForFrameIndex(const SDValue Op,
                                      KnownBits &Known,
                                      const APInt &DemandedElts,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 SITargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default: break;
     case 's':
     case 'v':
     case 'a':
       return C_RegisterClass;
+    case 'A':
+      return C_Other;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
+void SITargetLowering::LowerAsmOperandForConstraint(SDValue Op,
+                                                    std::string &Constraint,
+                                                    std::vector<SDValue> &Ops,
+                                                    SelectionDAG &DAG) const {
+  if (Constraint.length() == 1 && Constraint[0] == 'A') {
+    unsigned Size = Op.getValueSizeInBits();
+    if (Size > 64)
+      return;
+
+    uint64_t Val;
+    bool IsConst = false;
+    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+      Val = C->getSExtValue();
+      IsConst = true;
+    } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
+      Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
+      IsConst = true;
+    }
+
+    if (IsConst) {
+      bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
+      if ((Size == 16 && AMDGPU::isInlinableLiteral16(Val, HasInv2Pi)) ||
+          (Size == 32 && AMDGPU::isInlinableLiteral32(Val, HasInv2Pi)) ||
+          (Size == 64 && AMDGPU::isInlinableLiteral64(Val, HasInv2Pi))) {
+        auto IVal = AMDGPU::createInlineAsmConst(Val, Size);
+        auto Res = DAG.getTargetConstant(IVal, SDLoc(Op), MVT::i64);
+        Ops.push_back(Res);
+      }
+    }
+  } else {
+    TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
+  }
+}
+
 // Figure out which registers should be reserved for stack access. Only after
 // the function is legalized do we know all of the non-spill stack objects or if
 // calls are present.
 void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
     // Allow inlining denormals enabled into denormals flushed functions.
     return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
            oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
            oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
            oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
   }
 };
 
+LLVM_READNONE
+uint64_t createInlineAsmConst(uint64_t Val, unsigned Size);
+
+LLVM_READNONE
+bool isInlineAsmConst(uint64_t Val);
+
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUBaseInfo.h"
 #include "AMDGPU.h"
 #include "AMDGPUAsmUtils.h"
 #include "AMDGPUTargetTransformInfo.h"
 #include "SIDefines.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/ADT/APFloat.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"

 
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo) {
   assert(OpNo < Desc.NumOperands);
   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
   return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
 }
 
+static bool isInlinableIntLiteral(int64_t Literal) {
+  return Literal >= -16 && Literal <= 64;
+}
+
 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
-  if (Literal >= -16 && Literal <= 64)
+  if (isInlinableIntLiteral(Literal))
     return true;
 
   uint64_t Val = static_cast<uint64_t>(Literal);
   return (Val == DoubleToBits(0.0)) ||
          (Val == DoubleToBits(1.0)) ||
          (Val == DoubleToBits(-1.0)) ||
          (Val == DoubleToBits(0.5)) ||
          (Val == DoubleToBits(-0.5)) ||
          (Val == DoubleToBits(2.0)) ||
          (Val == DoubleToBits(-2.0)) ||
          (Val == DoubleToBits(4.0)) ||
          (Val == DoubleToBits(-4.0)) ||
          (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
 }
 
 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
-  if (Literal >= -16 && Literal <= 64)
+  if (isInlinableIntLiteral(Literal))
     return true;
 
   // The actual type of the operand does not seem to matter as long
   // as the bits match one of the inline immediate values.  For example:
   //
   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
   // so it is a legal inline immediate.
   //
return (Val == FloatToBits(0.0f)) ||
          (Val == FloatToBits(-4.0f)) ||
          (Val == 0x3e22f983 && HasInv2Pi);
 }
 
 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
   if (!HasInv2Pi)
     return false;
 
-  if (Literal >= -16 && Literal <= 64)
+  if (isInlinableIntLiteral(Literal))
     return true;
 
   uint16_t Val = static_cast<uint16_t>(Literal);
   return Val == 0x3C00 || // 1.0
          Val == 0xBC00 || // -1.0
          Val == 0x3800 || // 0.5
          Val == 0xB800 || // -0.5
          Val == 0x4000 || // 2.0

 }
 
 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
                                                   const MCSubtargetInfo &STI) {
   return isGFX10(STI) ? getGfx10PlusBufferFormatInfo(Format)
                       : getGfx9BufferFormatInfo(Format);
 }
 
+// Convert fp inline constants to 64-bit. f64 has the following advantages:
+// 1) When printed, these constants are valid for any operand type.
+// 2) Encoding of f64 inline constants is different from any 32-bit literal.
+//    This may be useful for future extensions.
+uint64_t createInlineAsmConst(uint64_t Val, unsigned Size) {
+  assert(Size == 16 || Size == 32 || Size == 64);
+
+  if (isInlinableIntLiteral(Val))
+    return Val;
+
+  // Convert inv2pi.
+  if ((Size == 16 && Val == 0x3118) ||
+      (Size == 32 && Val == 0x3e22f983))
+    return 0x3fc45f306dc9c882;
+
+  // Convert remaining fp constants.
+  if (Size < 64) {
+    bool Lost;
+    const fltSemantics *FltSemantics =
+      (Size == 16) ? &APFloat::IEEEhalf() : &APFloat::IEEEsingle();
+    APFloat FPLiteral(*FltSemantics, APInt(Size, Val));
+    FPLiteral.convert(APFloat::IEEEdouble(),
+                      APFloat::rmNearestTiesToEven,
+                      &Lost);
+    return FPLiteral.bitcastToAPInt().getZExtValue();
+  }
+
+  return Val;
+}
+
+bool isInlineAsmConst(uint64_t Val) {
+  return AMDGPU::isInlinableLiteral64(Val, true);
+}
+
 } // namespace AMDGPU
 } // namespace llvm

llvm/test/CodeGen/AMDGPU/inline-constraints.ll

-; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
+; RUN: not llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s
+; RUN: not llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=VI %s
+
+; RUN: not llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs 2>&1 | FileCheck --check-prefix=NOGCN --check-prefix=NOSI %s
+; RUN: not llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs 2>&1 | FileCheck --check-prefix=NOGCN %s
 
 ; GCN-LABEL: {{^}}inline_reg_constraints:
 ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
 ; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]

 ; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f64:
 ; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}}
 ; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}}
 ; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}}
 define amdgpu_kernel void @inline_sreg_constraint_imm_f64() {
   tail call void asm sideeffect "; use $0", "s"(double 1.0)
   ret void
 }
+
+;==============================================================================
+; 'A' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 64
+define i32 @inline_A_constraint_H0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 64)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_A_constraint_H1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 -16)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H2:
+; VI: v_mov_b32 {{v[0-9]+}}, 1.0
+define i32 @inline_A_constraint_H2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 1.0 to i16))
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, -1.0
+define i32 @inline_A_constraint_H3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half -1.0 to i16))
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0.15915494309189532
+define i32 @inline_A_constraint_H4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(half 0xH3118)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H5:
+; VI: v_mov_b32 {{v[0-9]+}}, 0.15915494309189532
+define i32 @inline_A_constraint_H5() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3118 to i16))
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_H6:
+; VI: v_mov_b32 {{v[0-9]+}}, -0.5
+define i32 @inline_A_constraint_H6() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(half -0.5)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_H7() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3119 to i16))
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_H8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3117 to i16))
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_H9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 65)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'A' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_A_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_A_constraint_F0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 -16)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 1
+define i32 @inline_A_constraint_F1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_F2:
+; GCN: v_mov_b32 {{v[0-9]+}}, -0.5
+define i32 @inline_A_constraint_F2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 bitcast (float -0.5 to i32))
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_F3:
+; GCN: v_mov_b32 {{v[0-9]+}}, 2.0
+define i32 @inline_A_constraint_F3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 bitcast (float 2.0 to i32))
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_F4:
+; GCN: v_mov_b32 {{v[0-9]+}}, -4.0
+define i32 @inline_A_constraint_F4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(float -4.0)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_F5:
+; VI: v_mov_b32 {{v[0-9]+}}, 0.15915494309189532
+define i32 @inline_A_constraint_F5() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1042479491)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_F6:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0.5
+define i32 @inline_A_constraint_F6() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(float 0.5)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_F7() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1042479490)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_F8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 -17)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'A' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_A_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -16
+define i32 @inline_A_constraint_D0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i64 -16)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, -2.0
+define i32 @inline_A_constraint_D1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i64 bitcast (double -2.0 to i64))
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_D2:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0.5
+define i32 @inline_A_constraint_D2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(double 0.5)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_D3:
+; VI: v_mov_b32 {{v[0-9]+}}, 0.15915494309189532
+define i32 @inline_A_constraint_D3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(double 0.15915494309189532)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'A'
+; VI-LABEL: {{^}}inline_A_constraint_D4:
+; VI: v_mov_b32 {{v[0-9]+}}, 0.15915494309189532
+define i32 @inline_A_constraint_D4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i64 bitcast (double 0.15915494309189532 to i64))
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_A_constraint_D5:
+; GCN: v_mov_b32 {{v[0-9]+}}, -2.0
+define i32 @inline_A_constraint_D5() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(double -2.0)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_D8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(double 1.1)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_D9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i64 bitcast (double 0.1 to i64))
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'A' constraint, type errors
+;==============================================================================
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_E1(i32 %x) {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 %x)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'A'
+define i32 @inline_A_constraint_E2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i128 100000000000000000000)
+  ret i32 %v0
+}