[PowerPC] Fold vector merges of swapped vectors to merge the opposite half

[nemanjai]

Summary

There are quite a few sequences that will produce a swap followed by a merge (low/high). This is mainly due to the SCALAR_TO_VECTOR on little endian requiring a swap (since all PPC instructions have a big endian bias). Due to its prevalence, these sequences often appear in fairly hot code, so we want to get rid of unnecessary swaps.

This patch does two things:

1. Convert a merge (high/low) to the opposite merge if both inputs are swapped
2. Convert a merge (high/low) to the opposite merge if one input is swapped and the other is symmetrical about the midpoint

[nemanjai]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

291

MTVSRWS as well as splatting loads are missing.

[nemanjai]

Pulled out the NFC update to PPCInstrVSX.td and rebased on top of that commit. Added the missing symmetrical opcodes.

[stefanp]

This patch LGTM.
I have a few minor comments but that is it.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

274

What about XXSLDWIs here? It's the same as XXSLDWI but we know the two inputs are the same.

313

Question:
I assume that trivial instructions such as: XXLEQV and XXLORC are not worth adding because we will never see them with identical inputs. Basically XXLEQV with MI->getOperand(1).getReg() == MI->getOperand(2).getReg() is the same as XXLEQVOnes so we will never see that by itself.

336

Is this last line there so that the compiler does not complain about having Copy defined but not used when we don't have debug enabled?

llvm/test/CodeGen/PowerPC/merge_of_swap.ll

9

nit:
I don't think we need the #0.
Also can you add a couple of sentences to explain that this test checks that we want to remove swaps that feed merges when we know the input to the swap is symmetrical.

[amyk]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

317

I think it would be good to document this function, as other PPCMIPeephole:: functions are also documented.

637

Just curious but does vmrg[e | o]w apply here, too?

681

Minor nit, but maybe reorder the cases the same way as how they're presented in the cases above?

[lei]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

287

Wondering if it would be good to add a flag in the td file to mark such instructions instead of listing them here. That way when we add future instructions to the td file that will fall into this case, it'll be easier to see that is needed.

680

maybe add a default: llvm_unreachable() here?

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   let AddedComplexity = 400 in {
     // LIWAX - This instruction is used for sign extending i32 -> i64.
     // LIWZX - This instruction will be emitted for i32, f32, and when
     //         zero-extending i32 to i64 (zext i32 -> i64).
     let Predicates = [IsLittleEndian] in {
 
       def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))),
                 (v2i64 (XXPERMDIs
-                (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSFRC), 2))>;
 
       def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))),
                 (v2i64 (XXPERMDIs
-                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2))>;
 
       def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))),
                 (v4i32 (XXPERMDIs
-                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2))>;
 
       def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
                 (v4f32 (XXPERMDIs
-                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2))>;
     }
 
     let Predicates = [IsBigEndian] in {
       def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))),
                 (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>;
 
       def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))),
                 (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>;
def : Pat<(v4f32 (PPCldvsxlh iaddrX4:$src)),
             (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC)>;
 
   let AddedComplexity = 400 in {
   // The following pseudoinstructions are used to ensure the utilization
   // of all 64 VSX registers.
     let Predicates = [IsLittleEndian, HasP9Vector] in {
       def : Pat<(v2i64 (scalar_to_vector (i64 (load iaddrX4:$src)))),
                 (v2i64 (XXPERMDIs
-                (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2))>;
       def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddrX4:$src)))),
                 (v2i64 (XXPERMDIs
-    (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC), 2))>;
+    (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2))>;
 
       def : Pat<(v2f64 (scalar_to_vector (f64 (load iaddrX4:$src)))),
                 (v2f64 (XXPERMDIs
-                (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2))>;
       def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddrX4:$src)))),
                 (v2f64 (XXPERMDIs
-                (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC), 2))>;
+                (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2))>;
       def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xaddrX4:$src),
                 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
                              sub_64), xaddrX4:$src)>;
       def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src),
                 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
                              sub_64), xaddrX4:$src)>;
       def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src),
                 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>;

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

struct PPCMIPeephole : public MachineFunctionPass {
   }
 
 private:
   MachineDominatorTree *MDT;
   MachinePostDominatorTree *MPDT;
   MachineBlockFrequencyInfo *MBFI;
   uint64_t EntryFreq;
 
+  Register getVecCopyOrSubregToReg(MachineInstr &MI, Register SrcReg,
+                                   const TargetRegisterClass *ToRC) const;
   // Initialize class variables.
   void initialize(MachineFunction &MFParm);
 
   // Perform peepholes.
   bool simplifyCode(void);
 
   // Perform peepholes.
   bool eliminateRedundantCompare(void);
void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   // Main entry point for this pass.
   bool runOnMachineFunction(MachineFunction &MF) override {
     if (skipFunction(MF.getFunction()))
       return false;
     initialize(MF);
-    return simplifyCode();
+    bool Changed = simplifyCode();
+#ifndef NDEBUG
+    if (Changed) {
+      LLVM_DEBUG(dbgs() << "Machine function after transformations:\n");
+      LLVM_DEBUG(MF.dump());
+    }
+#endif
+    return Changed;
   }
 };
 
 // Initialize class variables.
 void PPCMIPeephole::initialize(MachineFunction &MFParm) {
   MF = &MFParm;
   MRI = &MF->getRegInfo();
   MDT = &getAnalysis<MachineDominatorTree>();
if (MDT->dominates(CurrInst, MI)) {
       Keep = false;
       break;
     }
   }
   // Add new instruction to map.
   TOCSaves[MI] = Keep;
 }
 
+static bool isSwap(MachineInstr *MI) {
+  unsigned Opc = MI->getOpcode();
+  if (Opc == PPC::XXPERMDIs && MI->getOperand(2).getImm() == 2)
+    return true;
+  if ((Opc == PPC::XXPERMDI || Opc == PPC::XXSLDWI) &&
+      MI->getOperand(1).getReg() == MI->getOperand(2).getReg() &&
+      MI->getOperand(3).getImm() == 2)
+    return true;
+  return false;
+}
+
+// Is the vreg produced by this instruction symmetrical about the midpoint.
+// This is the case for splats, some constants, etc.
+static bool isSymmetrical(MachineInstr *MI) {
+  unsigned Opc = MI->getOpcode();
+  if (Opc == PPC::XXLXORz || Opc == PPC::XXSPLTW || Opc == PPC::XXSPLTWs ||
+      Opc == PPC::XXSPLTIB || Opc == PPC::XXLEQVOnes || Opc == PPC::VSPLTB ||
+      Opc == PPC::VSPLTH || Opc == PPC::VSPLTW || Opc == PPC::VSPLTBs ||
+      Opc == PPC::VSPLTHs || Opc == PPC::VSPLTISB || Opc == PPC::VSPLTISH ||
+      Opc == PPC::VSPLTISW)
+    return true;
+  return false;
+}
+
+Register
+PPCMIPeephole::getVecCopyOrSubregToReg(MachineInstr &MI, Register SrcReg,
+                                       const TargetRegisterClass *ToRC) const {
+  const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
+  const TargetRegisterClass *FromRC = MRI->getRegClass(SrcReg);
+  Register DestReg = MRI->createVirtualRegister(ToRC);
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineInstrBuilder Copy;
+  if (TRI->getRegSizeInBits(*FromRC) >= TRI->getRegSizeInBits(*ToRC))
+    Copy = BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), DestReg)
+               .addReg(SrcReg);
+  else
+    Copy = BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::SUBREG_TO_REG),
+                   DestReg)
+               .addImm(1)
+               .addReg(SrcReg)
+               .addImm(PPC::sub_64);
+  LLVM_DEBUG(dbgs() << "Emitted copy: ");
+  LLVM_DEBUG(Copy->dump());
+  (void)Copy;
+  return DestReg;
+}
+
 // Perform peephole optimizations.
 bool PPCMIPeephole::simplifyCode(void) {
   bool Simplified = false;
   MachineInstr* ToErase = nullptr;
   std::map<MachineInstr *, bool> TOCSaves;
   const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
   NumFunctionsEnteredInMIPeephole++;
   if (ConvertRegReg) {
     // Fixed-point conversion of reg/reg instructions fed by load-immediate
     // into reg/imm instructions. FIXME: This is expensive, control it with
     // an option.
     bool SomethingChanged = false;
     do {
       NumFixedPointIterations++;
       SomethingChanged = false;
       for (MachineBasicBlock &MBB : *MF) {
         for (MachineInstr &MI : MBB) {
           if (MI.isDebugInstr())
             continue;
 
           if (TII->convertToImmediateForm(MI)) {
             // We don't erase anything in case the def has other uses. Let DCE
             // remove it if it can be removed.
             LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
             LLVM_DEBUG(MI.dump());
             NumConvertedToImmediateForm++;
for (MachineInstr &MI : MBB) {
             removeFRSPIfPossible(P1);
             removeFRSPIfPossible(P2);
             break;
           }
           removeFRSPIfPossible(P1);
         }
         break;
       }
+      case PPC::VMRGLB:
+      case PPC::VMRGHB:
+      case PPC::VMRGLH:
+      case PPC::VMRGHH:
+      case PPC::VMRGLW:
+      case PPC::VMRGHW:
+      case PPC::XXMRGLW:
+      case PPC::XXMRGHW: {
+        // (mrgl (swap %a), %b)        --> (mrgh %a, %b) if %b is symmetrical
+        // (mrgl (swap %a), (swap %b)) --> (mrgh %a, %b)
+        bool Swapped = false;
+        Register Reg1 = TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
+        Register Reg2 = TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
+        if (!Register::isVirtualRegister(Reg1) ||
+            !Register::isVirtualRegister(Reg2))
+          break;
+        MachineInstr *SrcMI1 = MRI->getVRegDef(Reg1);
+        MachineInstr *SrcMI2 = MRI->getVRegDef(Reg2);
+
+        // Canonicalize to the swap being in SrcMI1.
+        if (!isSwap(SrcMI1)) {
+          std::swap(SrcMI1, SrcMI2);
+          Swapped = true;
+        }
+        bool IsLHSSwap = isSwap(SrcMI1);
+        bool IsRHSSwap = isSwap(SrcMI2);
+
+        // We can handle two cases:
+        // 1. Both sides come from a swap.
+        // 2. LHS comes from a swap, RHS is symmetrical.
+        if (!(IsLHSSwap && IsRHSSwap) && !(IsLHSSwap && isSymmetrical(SrcMI2)))
+          break;
+
+        LLVM_DEBUG(
+            dbgs() << "Found a merge fed by swap/swap or swap/symmetrical:\n");
+        LLVM_DEBUG(dbgs() << "Merge: ");
+        LLVM_DEBUG(MI.dump());
+        LLVM_DEBUG(dbgs() << "Source 1: ");
+        LLVM_DEBUG(SrcMI1->dump());
+        LLVM_DEBUG(dbgs() << "Source 2: ");
+        LLVM_DEBUG(SrcMI2->dump());
+
+        unsigned NewOpc;
+        switch (MI.getOpcode()) {
+        case PPC::VMRGLB:
+          NewOpc = PPC::VMRGHB;
+          break;
+        case PPC::VMRGLH:
+          NewOpc = PPC::VMRGHH;
+          break;
+        case PPC::VMRGLW:
+          NewOpc = PPC::VMRGHW;
+          break;
+        case PPC::XXMRGLW:
+          NewOpc = PPC::XXMRGHW;
+          break;
+        case PPC::VMRGHB:
+          NewOpc = PPC::VMRGLB;
+          break;
+        case PPC::VMRGHH:
+          NewOpc = PPC::VMRGLH;
+          break;
+        case PPC::VMRGHW:
+          NewOpc = PPC::VMRGLW;
+          break;
+        case PPC::XXMRGHW:
+          NewOpc = PPC::XXMRGLW;
+          break;
+        }
+
+        const TargetRegisterClass *ToRC =
+            MRI->getRegClass(MI.getOperand(0).getReg());
+        MI.setDesc(TII->get(NewOpc));
+
+        // We need to emit a copy for the LHS in both cases.
+        Register RegToCopy =
+            TRI->lookThruCopyLike(SrcMI1->getOperand(1).getReg(), MRI);
+        Register NewSrcReg = getVecCopyOrSubregToReg(MI, RegToCopy, ToRC);
+
+        // If the RHS is also a swap, get a copy for that as well.
+        if (IsRHSSwap) {
+          Register RHSRegToCopy =
+              TRI->lookThruCopyLike(SrcMI2->getOperand(1).getReg(), MRI);
+          Register RHSNewSrcReg =
+              getVecCopyOrSubregToReg(MI, RHSRegToCopy, ToRC);
+          MI.getOperand(Swapped ? 1 : 2).setReg(RHSNewSrcReg);
+        }
+
+        MI.getOperand(Swapped ? 2 : 1).setReg(NewSrcReg);
+        LLVM_DEBUG(dbgs() << "Converting to: ");
+        LLVM_DEBUG(MI.dump());
+        Simplified = true;
+        break;
+      }
       case PPC::EXTSH:
       case PPC::EXTSH8:
       case PPC::EXTSH8_32_64: {
         if (!EnableSExtElimination) break;
         Register NarrowReg = MI.getOperand(1).getReg();
         if (!Register::isVirtualRegister(NarrowReg))
           break;
 

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

 ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P9
 
 @a = external local_unnamed_addr global <4 x i32>, align 16
 @pb = external local_unnamed_addr global float*, align 8
 
 define void @testExpandPostRAPseudo(i32* nocapture readonly %ptr) {
 ; CHECK-P8-LABEL: testExpandPostRAPseudo:
 ; CHECK-P8:  # %bb.0: # %entry
 ; CHECK-P8:    lfiwzx f0, 0, r3
 ; CHECK-P8:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8:    xxpermdi vs0, f0, f0, 2
+; CHECK-P8:    xxswapd vs0, f0
 ; CHECK-P8:    xxspltw v2, vs0, 3
 ; CHECK-P8:    stvx v2, 0, r4
 ; CHECK-P8:    lis r4, 1024
 ; CHECK-P8:    lfiwax f0, 0, r3
 ; CHECK-P8:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P8:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P8:    xscvsxdsp f0, f0
 ; CHECK-P8:    ld r3, 0(r3)

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE-NEXT:    xxspltw v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemVali:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8LE-NEXT:    xxswapd vs0, f0
 ; P8LE-NEXT:    xxspltw v2, vs0, 3
 ; P8LE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr, align 4
   %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
 }

 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE-NEXT:    xxspltw v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8LE-NEXT:    xxswapd vs0, f0
 ; P8LE-NEXT:    xxspltw v2, vs0, 3
 ; P8LE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr, align 4
   %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
 }

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglb3:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI12_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-P9-NEXT:    xxswapd v2, f0
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P9-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = load <8 x i8>, <8 x i8>* %a, align 8
   %1 = zext <8 x i8> %0 to <8 x i16>
   ret <8 x i16> %1
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ; P9-NEXT:    lxvwsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test2:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    stvx v2, 0, r3
 ; P8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %a, i64 3
   %0 = load float, float* %arrayidx, align 4
   %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
   %splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
   store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
   ret void
 }
 
 define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
 ; P9-LABEL: test3:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r4, r4, 12
 ; P9-NEXT:    lxvwsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test3:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    stvx v2, 0, r3
 ; P8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %a, i64 3
   %0 = load i32, i32* %arrayidx, align 4
   %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
   %splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer

 ; P9-LABEL: unadjusted_lxvwsx:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: unadjusted_lxvwsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r3
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    blr
   entry:
     %0 = bitcast i32* %s to <4 x i8>*
     %1 = load <4 x i8>, <4 x i8>* %0, align 4
     %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
     ret <16 x i8> %2
 }

llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
 ; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
 ; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s
 
 define <16 x i8> @test(i32* %s, i32* %t) {
 ; CHECK-LE-LABEL: test:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    lfiwzx f0, 0, r3
-; CHECK-LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-LE-NEXT:    xxswapd vs0, f0
 ; CHECK-LE-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-LE-NEXT:    blr
 
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xxsldwi vs0, f0, f0, 1
 ; CHECK-NEXT:    xxspltw v2, vs0, 0
 ; CHECK-NEXT:    blr
 entry:
   %0 = bitcast i32* %s to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 4
   %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   ret <16 x i8> %2
 }

llvm/test/CodeGen/PowerPC/merge_of_swap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-P9
+define dso_local <4 x i32> @mrglb_self(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglb_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghb v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglb_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghb v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglb_sym(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglb_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    xxlxor v2, v2, v2
+; CHECK-P8-NEXT:    mtvsrd v3, r3
+; CHECK-P8-NEXT:    vmrghb v2, v2, v3
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglb_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglb_swap(<8 x i8>* nocapture readonly %c, <8 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglb_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    ld r4, 0(r4)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghb v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglb_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %1 = load <8 x i8>, <8 x i8>* %d, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define dso_local <4 x i32> @mrghb_self(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghb_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    vmrglb v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghb_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghb v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghb_sym(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghb_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    xxlxor v3, v3, v3
+; CHECK-P8-NEXT:    vmrglb v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghb_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghb_swap(<16 x i8>* nocapture readonly %c, <16 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghb_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r4
+; CHECK-P8-NEXT:    vmrglb v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghb_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    lxv v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %1 = load <16 x i8>, <16 x i8>* %d, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define dso_local <4 x i32> @mrglh_self(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglh_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghh v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglh_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghh v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglh_sym(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglh_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    xxlxor v2, v2, v2
+; CHECK-P8-NEXT:    mtvsrd v3, r3
+; CHECK-P8-NEXT:    vmrghh v2, v2, v3
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglh_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 8, i32 9, i32 2, i32 3, i32 10, i32 11, i32 4, i32 5, i32 12, i32 13, i32 6, i32 7, i32 14, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglh_swap(<8 x i8>* nocapture readonly %c, <8 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglh_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    ld r4, 0(r4)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghh v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglh_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %1 = load <8 x i8>, <8 x i8>* %d, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 1, i32 8, i32 9, i32 2, i32 3, i32 10, i32 11, i32 4, i32 5, i32 12, i32 13, i32 6, i32 7, i32 14, i32 15>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define dso_local <4 x i32> @mrghh_self(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghh_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    vmrglh v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghh_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghh v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghh_sym(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghh_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    xxlxor v3, v3, v3
+; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghh_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghh_swap(<16 x i8>* nocapture readonly %c, <16 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghh_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r4
+; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghh_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    lxv v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %1 = load <16 x i8>, <16 x i8>* %d, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define dso_local <4 x i32> @mrglw_self(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglw_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghw v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglw_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghw v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglw_sym(<8 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglw_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    xxlxor v2, v2, v2
+; CHECK-P8-NEXT:    mtvsrd v3, r3
+; CHECK-P8-NEXT:    vmrghw v2, v2, v3
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglw_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghw v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrglw_swap(<8 x i8>* nocapture readonly %c, <8 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglw_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    ld r4, 0(r4)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghw v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglw_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    lxsd v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghw v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <8 x i8>, <8 x i8>* %c, align 8
+  %1 = load <8 x i8>, <8 x i8>* %d, align 8
+  %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define dso_local <4 x i32> @mrghw_self(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghw_self:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    vmrglw v2, v2, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghw_self:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    vmrghw v2, v2, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghw_sym(<16 x i8>* nocapture readonly %c) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghw_sym:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    xxlxor v3, v3, v3
+; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghw_sym:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    vmrghw v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
+  %1 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %1
+}
+
+define dso_local <4 x i32> @mrghw_swap(<16 x i8>* nocapture readonly %c, <16 x i8>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrghw_swap:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r4
+; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrghw_swap:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxv v2, 0(r3)
+; CHECK-P9-NEXT:    lxv v3, 0(r4)
+; CHECK-P9-NEXT:    vmrghw v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %c, align 8
+  %1 = load <16 x i8>, <16 x i8>* %d, align 8
+  %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
+  %2 = bitcast <16 x i8> %vecinit30 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+; FIXME: This function is semantically equivalent to @mrglw_swap but we get
+;        terrible codegen for it due to how we handle BUILD_VECTOR/shuffle.
+define dso_local <4 x i32> @mrglw_bad(<2 x i32>* nocapture readonly %c, <2 x i32>* nocapture readonly %d) local_unnamed_addr #0 {
+; CHECK-P8-LABEL: mrglw_bad:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    ld r3, 0(r3)
+; CHECK-P8-NEXT:    ld r4, 0(r4)
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    xxswapd v4, v2
+; CHECK-P8-NEXT:    xxswapd v5, v3
+; CHECK-P8-NEXT:    vmrghw v2, v3, v2
+; CHECK-P8-NEXT:    vmrgew v3, v5, v4
+; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-LABEL: mrglw_bad:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxsd v2, 0(r3)
+; CHECK-P9-NEXT:    lxsd v4, 0(r4)
+; CHECK-P9-NEXT:    xxswapd v3, v2
+; CHECK-P9-NEXT:    xxswapd v5, v4
+; CHECK-P9-NEXT:    vmrghw v2, v4, v2
+; CHECK-P9-NEXT:    vmrgew v3, v5, v3
+; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
+; CHECK-P9-NEXT:    blr
+entry:
+  %0 = load <2 x i32>, <2 x i32>* %c, align 8
+  %1 = load <2 x i32>, <2 x i32>* %d, align 8
+  %vecinit30 = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+  ret <4 x i32> %vecinit30
+}
+
+attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/pr25080.ll

 ; LE-NEXT:    xxland 34, 34, 36
 ; LE-NEXT:    xxland 35, 35, 36
 ; LE-NEXT:    vcmpequw 2, 2, 5
 ; LE-NEXT:    vcmpequw 3, 3, 5
 ; LE-NEXT:    xxswapd 0, 34
 ; LE-NEXT:    mfvsrwz 3, 34
 ; LE-NEXT:    xxsldwi 1, 34, 34, 1
 ; LE-NEXT:    mfvsrwz 4, 35
-; LE-NEXT:    xxsldwi 4, 34, 34, 3
-; LE-NEXT:    mtvsrd 2, 3
+; LE-NEXT:    xxsldwi 2, 34, 34, 3
+; LE-NEXT:    mtvsrd 36, 3
 ; LE-NEXT:    mfvsrwz 3, 0
 ; LE-NEXT:    xxswapd 0, 35
-; LE-NEXT:    mtvsrd 3, 4
-; LE-NEXT:    xxsldwi 5, 35, 35, 1
+; LE-NEXT:    mtvsrd 37, 4
 ; LE-NEXT:    mfvsrwz 4, 1
-; LE-NEXT:    xxsldwi 7, 35, 35, 3
-; LE-NEXT:    mtvsrd 1, 3
-; LE-NEXT:    xxswapd 33, 3
-; LE-NEXT:    mfvsrwz 3, 4
-; LE-NEXT:    mtvsrd 4, 4
-; LE-NEXT:    xxswapd 34, 1
+; LE-NEXT:    xxsldwi 1, 35, 35, 1
+; LE-NEXT:    mtvsrd 34, 3
+; LE-NEXT:    mfvsrwz 3, 2
+; LE-NEXT:    mtvsrd 32, 4
 ; LE-NEXT:    mfvsrwz 4, 0
-; LE-NEXT:    mtvsrd 0, 3
-; LE-NEXT:    xxswapd 35, 4
-; LE-NEXT:    mfvsrwz 3, 5
-; LE-NEXT:    mtvsrd 6, 4
-; LE-NEXT:    xxswapd 36, 0
-; LE-NEXT:    mtvsrd 1, 3
-; LE-NEXT:    mfvsrwz 3, 7
-; LE-NEXT:    xxswapd 37, 6
-; LE-NEXT:    vmrglh 2, 3, 2
-; LE-NEXT:    xxswapd 35, 2
-; LE-NEXT:    mtvsrd 2, 3
-; LE-NEXT:    xxswapd 32, 1
+; LE-NEXT:    xxsldwi 0, 35, 35, 3
+; LE-NEXT:    mtvsrd 33, 3
+; LE-NEXT:    mfvsrwz 3, 1
+; LE-NEXT:    mtvsrd 38, 4
+; LE-NEXT:    mtvsrd 35, 3
+; LE-NEXT:    mfvsrwz 3, 0
+; LE-NEXT:    vmrghh 2, 0, 2
+; LE-NEXT:    mtvsrd 32, 3
 ; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; LE-NEXT:    vmrghh 4, 1, 4
 ; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; LE-NEXT:    xxswapd 38, 2
-; LE-NEXT:    vmrglh 3, 4, 3
-; LE-NEXT:    vmrglh 4, 0, 5
-; LE-NEXT:    vmrglh 5, 6, 1
-; LE-NEXT:    vmrglw 2, 3, 2
-; LE-NEXT:    vmrglw 3, 5, 4
+; LE-NEXT:    vmrghh 3, 3, 6
+; LE-NEXT:    vmrghh 5, 0, 5
+; LE-NEXT:    vmrglw 2, 4, 2
 ; LE-NEXT:    vspltish 4, 15
+; LE-NEXT:    vmrglw 3, 5, 3
 ; LE-NEXT:    xxmrgld 34, 35, 34
 ; LE-NEXT:    lvx 3, 0, 3
 ; LE-NEXT:    xxlor 34, 34, 35
 ; LE-NEXT:    vslh 2, 2, 4
 ; LE-NEXT:    vsrah 2, 2, 4
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: pr25080:

llvm/test/CodeGen/PowerPC/pr38087.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \
 ; RUN:   FileCheck %s
 ; Function Attrs: nounwind readnone speculatable
 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
 
 ; Function Attrs: nounwind readnone speculatable
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0
 
 define void @draw_llvm_vs_variant0(<4 x float> %x) {
 ; CHECK-LABEL: draw_llvm_vs_variant0:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v3, f0, f0, 2
-; CHECK-NEXT:    vmrglh v3, v3, v3
+; CHECK-NEXT:    lxsd v3, 0(r3)
+; CHECK-NEXT:    vmrghh v3, v3, v3
 ; CHECK-NEXT:    vextsh2w v3, v3
 ; CHECK-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-NEXT:    xxspltw vs0, vs0, 2
 ; CHECK-NEXT:    xvmaddasp vs0, v2, v2
 ; CHECK-NEXT:    stxvx vs0, 0, r3
 ; CHECK-NEXT:    blr
 entry:
   %.size = load i32, i32* undef

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r5)
 ; CHECK-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi r5, r5, .LCPI0_0@toc@l
 ; CHECK-NEXT:    lxvx v2, 0, r5
 ; CHECK-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
 ; CHECK-NEXT:    addi r5, r5, .LCPI0_1@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r5
-; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
+; CHECK-NEXT:    xxswapd v5, f0
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    li r5, 4
 ; CHECK-NEXT:    vperm v0, v3, v5, v2
 ; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    li r5, 0
 ; CHECK-NEXT:    vperm v1, v5, v3, v4
 ; CHECK-NEXT:    li r6, 0
 ; CHECK-NEXT:    xvnegsp v5, v0
 ; CHECK-NEXT:    xvnegsp v0, v1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    xxswapd v1, f0
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    vperm v6, v1, v3, v4
 ; CHECK-NEXT:    vperm v1, v3, v1, v2
 ; CHECK-NEXT:    xvnegsp v1, v1
 ; CHECK-NEXT:    add r7, r3, r4
 ; CHECK-NEXT:    xvnegsp v6, v6
 ; CHECK-NEXT:    vabsduw v1, v1, v5
 ; CHECK-NEXT:    vabsduw v6, v6, v0
 ; CHECK-NEXT:    vadduwm v1, v6, v1
 ; CHECK-NEXT:    xxswapd v6, v1
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    xxspltw v6, v1, 2
 ; CHECK-NEXT:    vadduwm v1, v1, v6
-; CHECK-NEXT:    xxpermdi v6, f0, f0, 2
+; CHECK-NEXT:    xxswapd v6, f0
 ; CHECK-NEXT:    vextuwrx r3, r5, v1
 ; CHECK-NEXT:    vperm v7, v6, v3, v4
 ; CHECK-NEXT:    vperm v6, v3, v6, v2
 ; CHECK-NEXT:    add r6, r3, r6
 ; CHECK-NEXT:    add r3, r7, r4
 ; CHECK-NEXT:    xvnegsp v6, v6
 ; CHECK-NEXT:    xvnegsp v1, v7
 ; CHECK-NEXT:    vabsduw v6, v6, v5

 define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
 ; CHECK-LABEL: test_pre_inc_disable_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-NEXT:    xxswapd v2, f0
 ; CHECK-NEXT:    lfd f0, 0(r4)
 ; CHECK-NEXT:    addi r3, r3, .LCPI1_1@toc@l
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    lxvx v0, 0, r3
-; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    xxswapd v1, f0
 ; CHECK-NEXT:    vperm v5, v2, v3, v4
 ; CHECK-NEXT:    vperm v2, v3, v2, v0
 ; CHECK-NEXT:    vperm v0, v3, v1, v0
 ; CHECK-NEXT:    vperm v3, v1, v3, v4
 ; CHECK-NEXT:    vabsduw v2, v2, v0
 ; CHECK-NEXT:    vabsduw v3, v5, v3
 ; CHECK-NEXT:    vadduwm v2, v3, v2
 ; CHECK-NEXT:    xxswapd v3, v2

 ; CHECK-LABEL: test32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r5, r3, r4
 ; CHECK-NEXT:    lfiwzx f0, r3, r4
 ; CHECK-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 4
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-NEXT:    xxswapd v2, f0
 ; CHECK-NEXT:    lfiwzx f0, r5, r3
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
-; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
+; CHECK-NEXT:    xxswapd v5, f0
 ; CHECK-NEXT:    vperm v3, v5, v3, v4
 ; CHECK-NEXT:    vspltisw v4, 8
 ; CHECK-NEXT:    vnegw v3, v3
 ; CHECK-NEXT:    vadduwm v4, v4, v4
 ; CHECK-NEXT:    vslw v3, v3, v4
 ; CHECK-NEXT:    vsubuwm v2, v3, v2
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    stxvx vs0, 0, r3

 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sldi r4, r4, 1
 ; CHECK-NEXT:    add r6, r3, r4
 ; CHECK-NEXT:    li r7, 16
 ; CHECK-NEXT:    lxsihzx v2, r6, r7
 ; CHECK-NEXT:    lxsihzx v4, r3, r4
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    mtvsrd f0, r6
+; CHECK-NEXT:    mtvsrd v3, r6
 ; CHECK-NEXT:    vsplth v4, v4, 3
-; CHECK-NEXT:    xxswapd v3, vs0
 ; CHECK-NEXT:    vsplth v2, v2, 3
 ; CHECK-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-NEXT:    vmrglh v2, v3, v2
-; CHECK-NEXT:    vmrglh v3, v3, v4
+; CHECK-NEXT:    vmrghh v2, v3, v2
+; CHECK-NEXT:    vmrghh v3, v3, v4
 ; CHECK-NEXT:    xxlxor v4, v4, v4
 ; CHECK-NEXT:    vmrglw v3, v3, v4
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2

 }
 
 define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r6, r3, r4
 ; CHECK-NEXT:    lxsibzx v2, r3, r4
 ; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtvsrd v3, r3
 ; CHECK-NEXT:    li r3, 8
 ; CHECK-NEXT:    lxsibzx v5, r6, r3
-; CHECK-NEXT:    xxswapd v3, vs0
-; CHECK-NEXT:    vspltb v4, v3, 15
+; CHECK-NEXT:    xxswapd v4, v3
+; CHECK-NEXT:    vspltb v4, v4, 15
 ; CHECK-NEXT:    vspltb v2, v2, 7
-; CHECK-NEXT:    vmrglb v2, v3, v2
+; CHECK-NEXT:    vmrghb v2, v3, v2
 ; CHECK-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI4_0@toc@l
 ; CHECK-NEXT:    vspltb v5, v5, 7
 ; CHECK-NEXT:    vmrglh v2, v2, v4
-; CHECK-NEXT:    vmrglb v3, v3, v5
+; CHECK-NEXT:    vmrghb v3, v3, v5
 ; CHECK-NEXT:    vmrglw v2, v2, v4
 ; CHECK-NEXT:    vmrglh v3, v3, v4
 ; CHECK-NEXT:    vmrglw v3, v4, v3
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3

llvm/test/CodeGen/PowerPC/qpx-load-splat.ll

entry:
   store double* %p, double** %pptr, align 8
   ret <4 x double> %shuffle.i
 }
 
 define <4 x float> @foof(float* nocapture readonly %a) #0 {
 ; CHECK-LABEL: foof:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfiwzx f0, 0, r3
-; CHECK-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-NEXT:    xxswapd vs0, f0
 ; CHECK-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* %a, align 4
   %vecinit.i = insertelement <4 x float> undef, float %0, i32 0
   %shuffle.i = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %shuffle.i
 }
 
 define <4 x float> @foofx(float* nocapture readonly %a, i64 %idx) #0 {
 ; CHECK-LABEL: foofx:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sldi r4, r4, 2
 ; CHECK-NEXT:    lfiwzx f0, r3, r4
-; CHECK-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-NEXT:    xxswapd vs0, f0
 ; CHECK-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-NEXT:    blr
 entry:
   %p = getelementptr float, float* %a, i64 %idx
   %0 = load float, float* %p, align 4
   %vecinit.i = insertelement <4 x float> undef, float %0, i32 0
   %shuffle.i = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %shuffle.i
 }
 
 

llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll

 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
 
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test1(i64* nocapture readonly %int64, <2 x i64> %vec) {
 ; P9LE-LABEL: s2v_test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 entry:
   %0 = load i64, i64* %int64, align 8
   %vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test2(i64* nocapture readonly %int64, <2 x i64> %vec)  {
 ; P9LE-LABEL: s2v_test2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 8(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %int64, i64 1
   %0 = load i64, i64* %arrayidx, align 8
   %vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test3(i64* nocapture readonly %int64, <2 x i64> %vec, i32 signext %Idx)  {
 ; P9LE-LABEL: s2v_test3:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 3
 ; P9LE-NEXT:    lfdx f0, r3, r4
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test3
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r7, 3
 ; P9BE-NEXT:    lfdx f0, r3, r4
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds i64, i64* %int64, i64 %idxprom
   %0 = load i64, i64* %arrayidx, align 8
   %vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test4(i64* nocapture readonly %int64, <2 x i64> %vec)  {
 ; P9LE-LABEL: s2v_test4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test4:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 8(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %int64, i64 1
   %0 = load i64, i64* %arrayidx, align 8
   %vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test5(<2 x i64> %vec, i64* nocapture readonly %ptr1)  {
 ; P9LE-LABEL: s2v_test5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r5)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test5:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r5)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 entry:
   %0 = load i64, i64* %ptr1, align 8
   %vecins = insertelement <2 x i64> %vec, i64 %0, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @s2v_test_f1(double* nocapture readonly %f64, <2 x double> %vec)  {
 ; P9LE-LABEL: s2v_test_f1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
entry:
   ret <2 x double> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @s2v_test_f2(double* nocapture readonly %f64, <2 x double> %vec)  {
 ; P9LE-LABEL: s2v_test_f2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 8(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr

 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @s2v_test_f3(double* nocapture readonly %f64, <2 x double> %vec, i32 signext %Idx)  {
 ; P9LE-LABEL: s2v_test_f3:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 3
 ; P9LE-NEXT:    lfdx f0, r3, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f3:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r7, 3
 ; P9BE-NEXT:    lfdx f0, r3, r4
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
entry:
   ret <2 x double> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @s2v_test_f4(double* nocapture readonly %f64, <2 x double> %vec)  {
 ; P9LE-LABEL: s2v_test_f4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f4:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 8(r3)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
entry:
   ret <2 x double> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @s2v_test_f5(<2 x double> %vec, double* nocapture readonly %ptr1)  {
 ; P9LE-LABEL: s2v_test_f5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r5)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f5:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r5)
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr

llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
 
 define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
 ; P9LE-LABEL: test_liwzx1:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    lfiwzx f0, 0, r3
 ; P9LE-NEXT:    lfiwzx f1, 0, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P9LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P9LE-NEXT:    xxswapd vs0, f0
+; P9LE-NEXT:    xxswapd vs1, f1
 ; P9LE-NEXT:    xvaddsp vs0, vs0, vs1
 ; P9LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P9LE-NEXT:    stfiwx f0, 0, r5
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: test_liwzx1:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    lfiwzx f0, 0, r3
 ; P9BE-NEXT:    lfiwzx f1, 0, r4
 ; P9BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P9BE-NEXT:    xxsldwi vs1, f1, f1, 1
 ; P9BE-NEXT:    xvaddsp vs0, vs0, vs1
 ; P9BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; P9BE-NEXT:    stfiwx f0, 0, r5
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: test_liwzx1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    lfiwzx f1, 0, r4
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P8LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P8LE-NEXT:    xxswapd vs0, f0
+; P8LE-NEXT:    xxswapd vs1, f1
 ; P8LE-NEXT:    xvaddsp vs0, vs0, vs1
 ; P8LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P8LE-NEXT:    stfiwx f0, 0, r5
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: test_liwzx1:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
; P8BE-NEXT:    blr
   ret void
 }
 
 define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
 ; P9LE-LABEL: test_liwzx2:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    lfiwzx f0, 0, r3
 ; P9LE-NEXT:    lfiwzx f1, 0, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P9LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P9LE-NEXT:    xxswapd vs0, f0
+; P9LE-NEXT:    xxswapd vs1, f1
 ; P9LE-NEXT:    xvsubsp vs0, vs0, vs1
 ; P9LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P9LE-NEXT:    mr r3, r5
 ; P9LE-NEXT:    stfiwx f0, 0, r5
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: test_liwzx2:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    lfiwzx f0, 0, r3
 ; P9BE-NEXT:    lfiwzx f1, 0, r4
 ; P9BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P9BE-NEXT:    xxsldwi vs1, f1, f1, 1
 ; P9BE-NEXT:    xvsubsp vs0, vs0, vs1
 ; P9BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; P9BE-NEXT:    mr r3, r5
 ; P9BE-NEXT:    stfiwx f0, 0, r5
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: test_liwzx2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    lfiwzx f1, 0, r4
 ; P8LE-NEXT:    mr r3, r5
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P8LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P8LE-NEXT:    xxswapd vs0, f0
+; P8LE-NEXT:    xxswapd vs1, f1
 ; P8LE-NEXT:    xvsubsp vs0, vs0, vs1
 ; P8LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P8LE-NEXT:    stfiwx f0, 0, r5
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: test_liwzx2:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    lfiwzx f0, 0, r3

llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll

 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test1(i32* nocapture readonly %int32, <2 x i64> %vec)  {
 ; P9LE-LABEL: s2v_test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
 ; P8BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %int32, align 4
   %conv = sext i32 %0 to i64
   %vecins = insertelement <2 x i64> %vec, i64 %conv, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test2(i32* nocapture readonly %int32, <2 x i64> %vec)  {
 ; P9LE-LABEL: s2v_test2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    addi r3, r3, 4
 ; P9BE-NEXT:    lfiwax f0, 0, r3
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test2:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    lfiwax f0, 0, r3
 ; P8BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
   %0 = load i32, i32* %arrayidx, align 4
   %conv = sext i32 %0 to i64
   %vecins = insertelement <2 x i64> %vec, i64 %conv, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test3(i32* nocapture readonly %int32, <2 x i64> %vec, i32 signext %Idx)  {
 ; P9LE-LABEL: s2v_test3:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 2
 ; P9LE-NEXT:    lfiwax f0, r3, r4
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test3:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r7, 2
 ; P9BE-NEXT:    lfiwax f0, r3, r4
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test3:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r7, 2
 ; P8LE-NEXT:    lfiwax f0, r3, r4
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r7, 2
 ; P8BE-NEXT:    lfiwax f0, r3, r4
 ; P8BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P8BE-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %conv = sext i32 %0 to i64
   %vecins = insertelement <2 x i64> %vec, i64 %conv, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test4(i32* nocapture readonly %int32, <2 x i64> %vec)  {
 ; P9LE-LABEL: s2v_test4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test4:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    addi r3, r3, 4
 ; P9BE-NEXT:    lfiwax f0, 0, r3
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test4:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    lfiwax f0, 0, r3
 ; P8BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
   %0 = load i32, i32* %arrayidx, align 4
   %conv = sext i32 %0 to i64
   %vecins = insertelement <2 x i64> %vec, i64 %conv, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test5(<2 x i64> %vec, i32* nocapture readonly %ptr1)  {
 ; P9LE-LABEL: s2v_test5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r5
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test5:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r5
 ; P9BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test5:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r5
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test5:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r5
 ; P8BE-NEXT:    xxpermdi v2, vs0, v2, 1
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr1, align 4
   %conv = sext i32 %0 to i64
   %vecins = insertelement <2 x i64> %vec, i64 %conv, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test6(i32* nocapture readonly %ptr)  {
 ; P9LE-LABEL: s2v_test6:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P9LE-NEXT:    xxswapd v2, f0
 ; P9LE-NEXT:    xxspltd v2, v2, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test6:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
 ; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test6:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P8LE-NEXT:    xxswapd v2, f0
 ; P8LE-NEXT:    xxspltd v2, v2, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test6:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
 ; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test7(i32* nocapture readonly %ptr)  {
 ; P9LE-LABEL: s2v_test7:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P9LE-NEXT:    xxswapd v2, f0
 ; P9LE-NEXT:    xxspltd v2, v2, 1
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test7:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
 ; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test7:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P8LE-NEXT:    xxswapd v2, f0
 ; P8LE-NEXT:    xxspltd v2, v2, 1
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test7:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
 ; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:    -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec)  {
 ; P8LE-LABEL: s2v_test1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; P8LE-NEXT:    addi r3, r4, .LCPI0_0@toc@l
-; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vperm v2, v3, v2, v4
+; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    xxswapd v4, f0
+; P8LE-NEXT:    vperm v2, v4, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE:         xxsldwi vs0, v2, vs0, 1
 ; P8BE:         xxsldwi v2, vs0, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %int32, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x i32> @s2v_test2(i32* nocapture readonly %int32, <4 x i32> %vec)  {
 ; P8LE-LABEL: s2v_test2:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addi r3, r4, .LCPI1_0@toc@l
-; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vperm v2, v3, v2, v4
+; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    xxswapd v4, f0
+; P8LE-NEXT:    vperm v2, v4, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         addi r3, r3, 4
 ; P8BE:         lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE:         xxsldwi vs0, v2, vs0, 1

 define <4 x i32> @s2v_test3(i32* nocapture readonly %int32, <4 x i32> %vec, i32 signext %Idx)  {
 ; P8LE-LABEL: s2v_test3:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r5, r7, 2
 ; P8LE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; P8LE-NEXT:    lfiwzx f0, r3, r5
 ; P8LE-NEXT:    addi r3, r4, .LCPI2_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         sldi r4, r7, 2
 ; P8BE:         lfiwzx f0, r3, r4
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1

 ; Function Attrs: norecurse nounwind readonly
 define <4 x i32> @s2v_test4(i32* nocapture readonly %int32, <4 x i32> %vec)  {
 ; P8LE-LABEL: s2v_test4:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addi r3, r4, .LCPI3_0@toc@l
-; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vperm v2, v3, v2, v4
+; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    xxswapd v4, f0
+; P8LE-NEXT:    vperm v2, v4, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         addi r3, r3, 4
 ; P8BE:         lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE:         xxsldwi vs0, v2, vs0, 1
 ; P8BE:         xxsldwi v2, vs0, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
   %0 = load i32, i32* %arrayidx, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x i32> @s2v_test5(<4 x i32> %vec, i32* nocapture readonly %ptr1)  {
 ; P8LE-LABEL: s2v_test5:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r5
 ; P8LE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vperm v2, v3, v2, v4
+; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    xxswapd v4, f0
+; P8LE-NEXT:    vperm v2, v4, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test5:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         lfiwzx f0, 0, r5
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE:         xxsldwi vs0, v2, vs0, 1
 ; P8BE:         xxsldwi v2, vs0, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr1, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec)  {
 ; P8LE-LABEL: s2v_test_f1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; P8LE-NEXT:    addi r3, r4, .LCPI5_0@toc@l
-; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vperm v2, v3, v2, v4
+; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    xxswapd v4, f0
+; P8LE-NEXT:    vperm v2, v4, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test_f1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE:         lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
 ; P8BE:         xxsldwi vs0, v2, vs0, 1
 ; P8BE:         xxsldwi v2, vs0, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load float, float* %f64, align 4
   %vecins = insertelement <4 x float> %vec, float %0, i32 0
   ret <4 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-DAG:     xxspltw v2, v2, 2
-; P9LE-DAG:     lfiwzx f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P9LE-NEXT:    vmrglw v2, v2, v3
+; P9LE-DAG:     lxsiwzx v3, 0, r3
+; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE:       addi r3, r3, 4
 ; P9BE-DAG:   xxspltw v2, v2, 1
 ; P9BE-DAG:   lfiwzx f0, 0, r3
 ; P9BE-NEXT:  xxsldwi v3, f0, f0, 1
 ; P9BE:       vmrghw v2, v3, v2
 ; P9BE-NEXT:  blr
 
 ; P8LE-LABEL: s2v_test_f2:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    xxspltw v2, v2, 2
-; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    lxsiwzx v3, 0, r3
+; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test_f2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    xxspltw v2, v2, 1
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx)  {
 ; P9LE-LABEL: s2v_test_f3:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 2
-; P9LE-NEXT:    lfiwzx f0, r3, r4
+; P9LE-NEXT:    lxsiwzx v3, r3, r4
 ; P9LE-DAG:     xxspltw v2, v2, 2
-; P9LE-DAG:     xxpermdi v3, f0, f0, 2
-; P9LE-NEXT:    vmrglw v2, v2, v3
+; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f3:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE:         sldi r4, r7, 2
 ; P9BE:         lfiwzx f0, r3, r4
 ; P9BE-DAG:     xxspltw v2, v2, 1
 ; P9BE-DAG:     xxsldwi v3, f0, f0, 1
 ; P9BE:         vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test_f3:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r7, 2
 ; P8LE-NEXT:    xxspltw v2, v2, 2
-; P8LE-NEXT:    lfiwzx f0, r3, r4
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    lxsiwzx v3, r3, r4
+; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test_f3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r7, 2
 ; P8BE-NEXT:    xxspltw v2, v2, 1
 ; P8BE-NEXT:    lfiwzx f0, r3, r4
 ; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds float, float* %f64, i64 %idxprom
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
-; P9LE-NEXT:    lfiwzx f0, 0, r3
+; P9LE-NEXT:    lxsiwzx v3, 0, r3
 ; P9LE-DAG:    xxspltw v2, v2, 2
-; P9LE-DAG:    xxpermdi v3, f0, f0, 2
-; P9LE-NEXT:    vmrglw v2, v2, v3
+; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f4:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE:         addi r3, r3, 4
 ; P9BE:         lfiwzx f0, 0, r3
 ; P9BE-DAG:     xxspltw v2, v2, 1
 ; P9BE-DAG:     xxsldwi v3, f0, f0, 1
 ; P9BE:         vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test_f4:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    xxspltw v2, v2, 2
-; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    lxsiwzx v3, 0, r3
+; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test_f4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
 ; P8BE-NEXT:    xxspltw v2, v2, 1
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f5(<2 x float> %vec, float* nocapture readonly %ptr1)  {
 ; P9LE-LABEL: s2v_test_f5:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lfiwzx f0, 0, r5
+; P9LE-NEXT:    lxsiwzx v3, 0, r5
 ; P9LE-NEXT:    xxspltw v2, v2, 2
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P9LE-NEXT:    vmrglw v2, v2, v3
+; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 
 ; P9BE-LABEL: s2v_test_f5:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE:         lfiwzx f0, 0, r5
 ; P9BE:         xxspltw v2, v2, 1
 ; P9BE-NEXT:    xxsldwi v3, f0, f0, 1
 ; P9BE:         vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 
 ; P8LE-LABEL: s2v_test_f5:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    lfiwzx f0, 0, r5
-; P8LE-NEXT:    xxspltw v2, v2, 2
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-DAG:     lxsiwzx v3, 0, r5
+; P8LE-DAG:     xxspltw v2, v2, 2
+; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 
 ; P8BE-LABEL: s2v_test_f5:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r5
 ; P8BE-NEXT:    xxspltw v2, v2, 1
 ; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %0 = load float, float* %ptr1, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 31710
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 63421
 ; P9LE-NEXT:    mulld r5, r4, r5
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r4, r5
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    mulli r4, r4, -124
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 33437
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r5, r4, 1, 63
 ; P9LE-NEXT:    rldicl r4, r4, 32, 32
 ; P9LE-NEXT:    srawi r4, r4, 5
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -16728
 ; P9LE-NEXT:    mulli r4, r4, 98
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 63249
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r5, r4, 1, 63
 ; P9LE-NEXT:    rldicl r4, r4, 32, 32
 ; P9LE-NEXT:    srawi r4, r4, 8
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, -1003
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_srem_vec_1:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3

 ; P8LE-NEXT:    srawi r8, r8, 6
 ; P8LE-NEXT:    mulli r4, r4, 98
 ; P8LE-NEXT:    mulli r9, r9, -1003
 ; P8LE-NEXT:    add r8, r8, r11
 ; P8LE-NEXT:    mulli r10, r10, 95
 ; P8LE-NEXT:    mulli r8, r8, -124
 ; P8LE-NEXT:    subf r3, r4, r3
 ; P8LE-NEXT:    subf r4, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtvsrd v2, r3
 ; P8LE-NEXT:    subf r3, r10, r7
-; P8LE-NEXT:    mtvsrd f1, r4
+; P8LE-NEXT:    mtvsrd v3, r4
 ; P8LE-NEXT:    subf r4, r8, r5
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    xxswapd v5, vs3
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    vmrglh v3, v5, v4
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v2, v3, v2
+; P8LE-NEXT:    vmrghh v3, v5, v4
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fold_srem_vec_1:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, -16728
 ; P8BE-NEXT:    lis r9, 31710

 ; P9LE-NEXT:    mulld r6, r4, r5
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    mulld r6, r4, r5
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    mulld r6, r4, r5
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    mulld r5, r4, r5
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_srem_vec_2:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3

 ; P8LE-NEXT:    add r9, r9, r12
 ; P8LE-NEXT:    mulli r8, r8, 95
 ; P8LE-NEXT:    add r4, r4, r11
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, 95
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    subf r3, r8, r3
 ; P8LE-NEXT:    subf r6, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtvsrd v2, r3
 ; P8LE-NEXT:    subf r3, r10, r7
 ; P8LE-NEXT:    subf r4, r4, r5
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    xxswapd v5, vs3
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    vmrglh v3, v5, v4
+; P8LE-NEXT:    mtvsrd v3, r6
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v2, v3, v2
+; P8LE-NEXT:    vmrghh v3, v5, v4
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fold_srem_vec_2:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, -21386
 ; P8BE-NEXT:    ori r3, r3, 37253

 ; P9LE-NEXT:    mulld r6, r4, r5
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r6, r4, 95
 ; P9LE-NEXT:    subf r3, r6, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r6, r3
 ; P9LE-NEXT:    extsw r6, r6
 ; P9LE-NEXT:    mulld r7, r6, r5
 ; P9LE-NEXT:    rldicl r7, r7, 32, 32
 ; P9LE-NEXT:    add r6, r7, r6
 ; P9LE-NEXT:    srwi r7, r6, 31
 ; P9LE-NEXT:    srawi r6, r6, 6
 ; P9LE-NEXT:    add r6, r6, r7
 ; P9LE-NEXT:    mulli r7, r6, 95
 ; P9LE-NEXT:    subf r3, r7, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r7, r3
 ; P9LE-NEXT:    extsw r7, r7
 ; P9LE-NEXT:    mulld r8, r7, r5
 ; P9LE-NEXT:    rldicl r8, r8, 32, 32
 ; P9LE-NEXT:    add r7, r8, r7
 ; P9LE-NEXT:    srwi r8, r7, 31
 ; P9LE-NEXT:    srawi r7, r7, 6
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    mulli r8, r7, 95
 ; P9LE-NEXT:    subf r3, r8, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r8, r3
 ; P9LE-NEXT:    extsw r8, r8
 ; P9LE-NEXT:    mulld r5, r8, r5
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r5, r5, r8
 ; P9LE-NEXT:    srwi r8, r5, 31
 ; P9LE-NEXT:    srawi r5, r5, 6
 ; P9LE-NEXT:    add r5, r5, r8
 ; P9LE-NEXT:    mulli r8, r5, 95
 ; P9LE-NEXT:    subf r3, r8, r3
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    mtvsrd f0, r4
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v4, r6
 ; P9LE-NEXT:    vmrglw v2, v2, v3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r6
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r7
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r5
-; P9LE-NEXT:    xxswapd v5, vs0
-; P9LE-NEXT:    vmrglh v4, v5, v4
+; P9LE-NEXT:    mtvsrd v3, r4
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r7
+; P9LE-NEXT:    mtvsrd v5, r5
+; P9LE-NEXT:    vmrghh v4, v5, v4
 ; P9LE-NEXT:    vmrglw v3, v4, v3
 ; P9LE-NEXT:    vadduhm v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: combine_srem_sdiv:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2

 ; P8LE-NEXT:    extsh r9, r4
 ; P8LE-NEXT:    rldicl r6, r6, 16, 48
 ; P8LE-NEXT:    extsh r10, r7
 ; P8LE-NEXT:    extsw r8, r8
 ; P8LE-NEXT:    extsw r9, r9
 ; P8LE-NEXT:    extsh r11, r6
 ; P8LE-NEXT:    extsw r10, r10
 ; P8LE-NEXT:    mulld r12, r8, r5
-; P8LE-NEXT:    extsw r11, r11
 ; P8LE-NEXT:    mulld r0, r9, r5
+; P8LE-NEXT:    extsw r11, r11
 ; P8LE-NEXT:    mulld r30, r10, r5
 ; P8LE-NEXT:    mulld r5, r11, r5
 ; P8LE-NEXT:    rldicl r12, r12, 32, 32
 ; P8LE-NEXT:    rldicl r0, r0, 32, 32
 ; P8LE-NEXT:    rldicl r30, r30, 32, 32
 ; P8LE-NEXT:    add r8, r12, r8
-; P8LE-NEXT:    rldicl r5, r5, 32, 32
 ; P8LE-NEXT:    add r9, r0, r9
+; P8LE-NEXT:    rldicl r5, r5, 32, 32
 ; P8LE-NEXT:    add r10, r30, r10
 ; P8LE-NEXT:    srwi r12, r8, 31
 ; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    srawi r8, r8, 6
 ; P8LE-NEXT:    srawi r0, r9, 6
 ; P8LE-NEXT:    srwi r9, r9, 31
 ; P8LE-NEXT:    add r5, r5, r11
 ; P8LE-NEXT:    add r8, r8, r12
 ; P8LE-NEXT:    srawi r12, r10, 6
 ; P8LE-NEXT:    srwi r10, r10, 31
 ; P8LE-NEXT:    add r9, r0, r9
-; P8LE-NEXT:    mulli r0, r8, 95
+; P8LE-NEXT:    mulli r11, r8, 95
 ; P8LE-NEXT:    add r10, r12, r10
-; P8LE-NEXT:    mtvsrd f0, r8
-; P8LE-NEXT:    srwi r8, r5, 31
+; P8LE-NEXT:    srwi r12, r5, 31
+; P8LE-NEXT:    mtvsrd v2, r8
 ; P8LE-NEXT:    srawi r5, r5, 6
-; P8LE-NEXT:    mulli r11, r9, 95
-; P8LE-NEXT:    mtvsrd f1, r9
+; P8LE-NEXT:    mulli r8, r9, 95
+; P8LE-NEXT:    mtvsrd v3, r9
+; P8LE-NEXT:    add r5, r5, r12
 ; P8LE-NEXT:    mulli r9, r10, 95
-; P8LE-NEXT:    add r5, r5, r8
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f2, r10
-; P8LE-NEXT:    mtvsrd f3, r5
-; P8LE-NEXT:    mulli r5, r5, 95
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r0, r3
-; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    subf r4, r11, r4
-; P8LE-NEXT:    xxswapd v6, vs3
+; P8LE-NEXT:    mtvsrd v4, r10
+; P8LE-NEXT:    mulli r10, r5, 95
+; P8LE-NEXT:    vmrghh v2, v3, v2
+; P8LE-NEXT:    subf r3, r11, r3
+; P8LE-NEXT:    subf r4, r8, r4
+; P8LE-NEXT:    mtvsrd v3, r3
+; P8LE-NEXT:    mtvsrd v5, r4
 ; P8LE-NEXT:    subf r3, r9, r7
-; P8LE-NEXT:    mtvsrd f1, r4
-; P8LE-NEXT:    mtvsrd f4, r3
-; P8LE-NEXT:    subf r3, r5, r6
-; P8LE-NEXT:    mtvsrd f5, r3
-; P8LE-NEXT:    xxswapd v4, vs1
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    xxswapd v3, vs0
-; P8LE-NEXT:    xxswapd v5, vs4
-; P8LE-NEXT:    xxswapd v0, vs5
-; P8LE-NEXT:    vmrglh v3, v4, v3
-; P8LE-NEXT:    vmrglh v4, v0, v5
-; P8LE-NEXT:    vmrglh v5, v6, v1
-; P8LE-NEXT:    vmrglw v3, v4, v3
-; P8LE-NEXT:    vmrglw v2, v5, v2
+; P8LE-NEXT:    subf r4, r10, r6
+; P8LE-NEXT:    mtvsrd v0, r3
+; P8LE-NEXT:    mtvsrd v1, r4
+; P8LE-NEXT:    vmrghh v3, v5, v3
+; P8LE-NEXT:    mtvsrd v5, r5
+; P8LE-NEXT:    vmrghh v0, v1, v0
+; P8LE-NEXT:    vmrghh v4, v5, v4
+; P8LE-NEXT:    vmrglw v3, v0, v3
+; P8LE-NEXT:    vmrglw v2, v4, v2
 ; P8LE-NEXT:    vadduhm v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: combine_srem_sdiv:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r6, v2
 ; P8BE-NEXT:    lis r5, -21386
 ; P8BE-NEXT:    ori r5, r5, 37253

 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 6
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 5
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 5
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    lis r5, -21386
 ; P9LE-NEXT:    ori r5, r5, 37253
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    vmrglh v3, v4, v3
+; P9LE-NEXT:    vmrghh v3, v4, v3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    mulld r5, r4, r5
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 3
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 3
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v4, v2
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_srem_power_of_two:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3

 ; P8LE-NEXT:    srawi r8, r8, 6
 ; P8LE-NEXT:    extsh r10, r9
 ; P8LE-NEXT:    addze r8, r8
 ; P8LE-NEXT:    rldicl r4, r4, 32, 48
 ; P8LE-NEXT:    srawi r10, r10, 5
 ; P8LE-NEXT:    slwi r8, r8, 6
 ; P8LE-NEXT:    subf r7, r8, r7
 ; P8LE-NEXT:    rldicl r3, r3, 32, 32
-; P8LE-NEXT:    mtvsrd f0, r7
+; P8LE-NEXT:    mtvsrd v2, r7
 ; P8LE-NEXT:    add r3, r3, r6
 ; P8LE-NEXT:    addze r6, r10
 ; P8LE-NEXT:    srwi r10, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 6
 ; P8LE-NEXT:    slwi r6, r6, 5
-; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    add r3, r3, r10
 ; P8LE-NEXT:    extsh r10, r4
 ; P8LE-NEXT:    subf r6, r6, r9
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    srawi r8, r10, 3
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtvsrd v3, r6
 ; P8LE-NEXT:    addze r7, r8
-; P8LE-NEXT:    xxswapd v3, vs1
+; P8LE-NEXT:    vmrghh v2, v3, v2
 ; P8LE-NEXT:    subf r3, r3, r5
 ; P8LE-NEXT:    slwi r5, r7, 3
 ; P8LE-NEXT:    subf r4, r5, r4
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    xxswapd v5, vs3
-; P8LE-NEXT:    vmrglh v3, v4, v5
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_srem_power_of_two:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, -21386
 ; P8BE-NEXT:    ori r3, r3, 37253

 ; P9LE-NEXT:    xxlxor v4, v4, v4
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 9
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -19946
 ; P9LE-NEXT:    mulli r4, r4, 654
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 17097
 ; P9LE-NEXT:    mulld r5, r4, r5
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 4
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v3, v4
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r5, r4, 1, 63
 ; P9LE-NEXT:    rldicl r4, r4, 32, 32
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    vmrglh v3, v3, v4
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_srem_one:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3

 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 24749
 ; P8LE-NEXT:    lis r8, -19946
 ; P8LE-NEXT:    lis r10, -14230
-; P8LE-NEXT:    xxlxor v5, v5, v5
+; P8LE-NEXT:    xxlxor v2, v2, v2
 ; P8LE-NEXT:    ori r3, r3, 47143
 ; P8LE-NEXT:    ori r8, r8, 17097
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    extsh r7, r5
 ; P8LE-NEXT:    extsh r9, r6

 ; P8LE-NEXT:    add r8, r8, r9
 ; P8LE-NEXT:    srwi r9, r7, 31
 ; P8LE-NEXT:    srawi r7, r7, 9
 ; P8LE-NEXT:    mulli r3, r3, 5423
 ; P8LE-NEXT:    add r7, r7, r9
 ; P8LE-NEXT:    mulli r8, r8, 23
 ; P8LE-NEXT:    mulli r7, r7, 654
 ; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    subf r3, r8, r6
-; P8LE-NEXT:    subf r4, r7, r4
-; P8LE-NEXT:    mtvsrd f1, r3
-; P8LE-NEXT:    mtvsrd f2, r4
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    vmrglh v2, v2, v3
-; P8LE-NEXT:    vmrglh v3, v4, v5
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    subf r5, r8, r6
+; P8LE-NEXT:    mtvsrd v3, r3
+; P8LE-NEXT:    subf r3, r7, r4
+; P8LE-NEXT:    mtvsrd v4, r5
+; P8LE-NEXT:    mtvsrd v5, r3
+; P8LE-NEXT:    vmrghh v3, v3, v4
+; P8LE-NEXT:    vmrghh v2, v5, v2
+; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_srem_one:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 24749
 ; P8BE-NEXT:    lis r7, -19946
 ; P8BE-NEXT:    lis r8, -14230

 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 4
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    extsw r4, r4
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r5, r4, 1, 63
 ; P9LE-NEXT:    rldicl r4, r4, 32, 32
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 15
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 15
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v3, v4, v3
+; P9LE-NEXT:    vmrghh v3, v4, v3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_urem_i16_smax:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3

 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_i16_smax:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r6, 24749
 ; P8LE-NEXT:    lis r7, -19946
-; P8LE-NEXT:    xxlxor v5, v5, v5
+; P8LE-NEXT:    xxlxor v2, v2, v2
 ; P8LE-NEXT:    ori r6, r6, 47143
 ; P8LE-NEXT:    ori r7, r7, 17097
 ; P8LE-NEXT:    mfvsrd r3, f0
 ; P8LE-NEXT:    rldicl r4, r3, 16, 48
 ; P8LE-NEXT:    rldicl r5, r3, 32, 48
 ; P8LE-NEXT:    extsh r8, r4
 ; P8LE-NEXT:    extsh r9, r5
 ; P8LE-NEXT:    extsw r8, r8

 ; P8LE-NEXT:    srawi r7, r7, 4
 ; P8LE-NEXT:    mulli r6, r6, 5423
 ; P8LE-NEXT:    add r7, r7, r8
 ; P8LE-NEXT:    extsh r8, r3
 ; P8LE-NEXT:    mulli r7, r7, 23
 ; P8LE-NEXT:    srawi r8, r8, 15
 ; P8LE-NEXT:    subf r4, r6, r4
 ; P8LE-NEXT:    addze r6, r8
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    slwi r4, r6, 15
+; P8LE-NEXT:    slwi r6, r6, 15
+; P8LE-NEXT:    mtvsrd v3, r4
 ; P8LE-NEXT:    subf r5, r7, r5
-; P8LE-NEXT:    subf r3, r4, r3
-; P8LE-NEXT:    mtvsrd f1, r5
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    vmrglh v2, v2, v3
-; P8LE-NEXT:    vmrglh v3, v4, v5
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    subf r3, r6, r3
+; P8LE-NEXT:    mtvsrd v4, r5
+; P8LE-NEXT:    mtvsrd v5, r3
+; P8LE-NEXT:    vmrghh v3, v3, v4
+; P8LE-NEXT:    vmrghh v2, v5, v2
+; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_i16_smax:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 24749
 ; P8BE-NEXT:    lis r7, -19946
 ; P8BE-NEXT:    ori r3, r3, 47143

llvm/test/CodeGen/PowerPC/swaps-le-6.ll

 ; CHECK-P9:     addis r3, r2, .LC0@toc@ha
 ; CHECK-P9:     ld r3, .LC0@toc@l(r3)
 ; CHECK-P9:     lxvx vs0, 0, r3
 ; CHECK-P9:     addis r3, r2, .LC1@toc@ha
 ; CHECK-P9:     ld r3, .LC1@toc@l(r3)
 ; CHECK-P9:     lfd f1, 0(r3)
 ; CHECK-P9:     addis r3, r2, .LC2@toc@ha
 ; CHECK-P9:     ld r3, .LC2@toc@l(r3)
-; CHECK-P9:     xxpermdi vs1, f1, f1, 2
+; CHECK-P9:     xxswapd vs1, f1
 ; CHECK-P9:     xxpermdi vs0, vs0, vs1, 1
 ; CHECK-P9:     stxvx vs0, 0, r3
 ; CHECK-P9:     blr
 entry:
   %0 = load <2 x double>, <2 x double>* @x, align 16
   %1 = load double, double* @y, align 8
   %vecins = insertelement <2 x double> %0, double %1, i32 0
   store <2 x double> %vecins, <2 x double>* @z, align 16

 ; CHECK-P9:     addis r3, r2, .LC0@toc@ha
 ; CHECK-P9:     ld r3, .LC0@toc@l(r3)
 ; CHECK-P9:     lxvx vs0, 0, r3
 ; CHECK-P9:     addis r3, r2, .LC1@toc@ha
 ; CHECK-P9:     ld r3, .LC1@toc@l(r3)
 ; CHECK-P9:     lfd f1, 0(r3)
 ; CHECK-P9:     addis r3, r2, .LC2@toc@ha
 ; CHECK-P9:     ld r3, .LC2@toc@l(r3)
-; CHECK-P9:     xxpermdi vs1, f1, f1, 2
+; CHECK-P9:     xxswapd vs1, f1
 ; CHECK-P9:     xxmrgld vs0, vs1, vs0
 ; CHECK-P9:     stxvx vs0, 0, r3
 ; CHECK-P9:     blr
 entry:
   %0 = load <2 x double>, <2 x double>* @x, align 16
   %1 = load double, double* @y, align 8
   %vecins = insertelement <2 x double> %0, double %1, i32 1
   store <2 x double> %vecins, <2 x double>* @z, align 16
   ret void
 }
 

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 ; P9LE-NEXT:    ori r5, r5, 33437
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 16727
 ; P9LE-NEXT:    ori r5, r5, 2287
 ; P9LE-NEXT:    rldicl r4, r4, 27, 37
 ; P9LE-NEXT:    mulli r4, r4, 98
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 8456
 ; P9LE-NEXT:    ori r5, r5, 16913
 ; P9LE-NEXT:    rldicl r4, r4, 24, 40
 ; P9LE-NEXT:    mulli r4, r4, 1003
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 30, 18, 31
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r4, r4, 30, 34
 ; P9LE-NEXT:    mulli r4, r4, 124
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v4, v2
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_urem_vec_1:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31

 ; P8LE-NEXT:    mulli r7, r8, 98
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    rldicl r8, r11, 30, 34
 ; P8LE-NEXT:    mulli r6, r6, 1003
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    mulli r8, r8, 124
 ; P8LE-NEXT:    subf r7, r7, r9
 ; P8LE-NEXT:    subf r6, r6, r10
-; P8LE-NEXT:    mtvsrd f0, r7
+; P8LE-NEXT:    mtvsrd v2, r7
 ; P8LE-NEXT:    subf r3, r3, r5
 ; P8LE-NEXT:    subf r4, r8, r4
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    xxswapd v5, vs3
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    vmrglh v3, v5, v4
+; P8LE-NEXT:    mtvsrd v3, r6
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v2, v3, v2
+; P8LE-NEXT:    vmrghh v3, v5, v4
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fold_urem_vec_1:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    lis r9, 16727

 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_urem_vec_2:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31

 ; P8LE-NEXT:    mulli r8, r8, 95
 ; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    srwi r4, r4, 6
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, 95
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    subf r3, r8, r3
 ; P8LE-NEXT:    subf r6, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtvsrd v2, r3
 ; P8LE-NEXT:    subf r3, r10, r7
 ; P8LE-NEXT:    subf r4, r4, r5
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    xxswapd v5, vs3
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    vmrglh v3, v5, v4
+; P8LE-NEXT:    mtvsrd v3, r6
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v2, v3, v2
+; P8LE-NEXT:    vmrghh v3, v5, v4
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fold_urem_vec_2:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    ori r3, r3, 8969

 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r5, r4, 95
 ; P9LE-NEXT:    subf r3, r5, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r5, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r7, r5, 32
 ; P9LE-NEXT:    mulld r7, r7, r6
 ; P9LE-NEXT:    rldicl r7, r7, 32, 32
 ; P9LE-NEXT:    subf r5, r7, r5
 ; P9LE-NEXT:    srwi r5, r5, 1
 ; P9LE-NEXT:    add r5, r5, r7
 ; P9LE-NEXT:    srwi r5, r5, 6
 ; P9LE-NEXT:    mulli r7, r5, 95
 ; P9LE-NEXT:    subf r3, r7, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r7, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r8, r7, 32
 ; P9LE-NEXT:    mulld r8, r8, r6
 ; P9LE-NEXT:    rldicl r8, r8, 32, 32
 ; P9LE-NEXT:    subf r7, r8, r7
 ; P9LE-NEXT:    srwi r7, r7, 1
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    srwi r7, r7, 6
 ; P9LE-NEXT:    mulli r8, r7, 95
 ; P9LE-NEXT:    subf r3, r8, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r8, r3, 0, 16, 31
 ; P9LE-NEXT:    clrldi r9, r8, 32
 ; P9LE-NEXT:    mulld r6, r9, r6
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
 ; P9LE-NEXT:    subf r8, r6, r8
 ; P9LE-NEXT:    srwi r8, r8, 1
 ; P9LE-NEXT:    add r6, r8, r6
 ; P9LE-NEXT:    srwi r6, r6, 6
 ; P9LE-NEXT:    mulli r8, r6, 95
 ; P9LE-NEXT:    subf r3, r8, r3
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    mtvsrd f0, r4
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v2, v4
+; P9LE-NEXT:    mtvsrd v4, r5
 ; P9LE-NEXT:    vmrglw v2, v2, v3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r5
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r7
-; P9LE-NEXT:    vmrglh v3, v4, v3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r6
-; P9LE-NEXT:    xxswapd v5, vs0
-; P9LE-NEXT:    vmrglh v4, v5, v4
+; P9LE-NEXT:    mtvsrd v3, r4
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v4, r7
+; P9LE-NEXT:    mtvsrd v5, r6
+; P9LE-NEXT:    vmrghh v4, v5, v4
 ; P9LE-NEXT:    vmrglw v3, v4, v3
 ; P9LE-NEXT:    vadduhm v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: combine_urem_udiv:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2

 ; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_urem_udiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r5, 22765
-; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    ori r5, r5, 8969
 ; P8LE-NEXT:    mfvsrd r6, f0
 ; P8LE-NEXT:    clrldi r3, r6, 48
 ; P8LE-NEXT:    rldicl r4, r6, 48, 48
-; P8LE-NEXT:    rldicl r7, r6, 32, 48
 ; P8LE-NEXT:    rlwinm r8, r3, 0, 16, 31
 ; P8LE-NEXT:    rlwinm r9, r4, 0, 16, 31
+; P8LE-NEXT:    rldicl r7, r6, 32, 48
 ; P8LE-NEXT:    rldicl r6, r6, 16, 48
-; P8LE-NEXT:    rlwinm r10, r7, 0, 16, 31
 ; P8LE-NEXT:    clrldi r11, r8, 32
-; P8LE-NEXT:    rlwinm r12, r6, 0, 16, 31
 ; P8LE-NEXT:    clrldi r0, r9, 32
-; P8LE-NEXT:    clrldi r30, r10, 32
+; P8LE-NEXT:    rlwinm r10, r7, 0, 16, 31
+; P8LE-NEXT:    rlwinm r12, r6, 0, 16, 31
 ; P8LE-NEXT:    mulld r11, r11, r5
-; P8LE-NEXT:    clrldi r29, r12, 32
 ; P8LE-NEXT:    mulld r0, r0, r5
+; P8LE-NEXT:    clrldi r30, r10, 32
+; P8LE-NEXT:    clrldi r29, r12, 32
 ; P8LE-NEXT:    mulld r30, r30, r5
 ; P8LE-NEXT:    mulld r5, r29, r5
 ; P8LE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    rldicl r11, r11, 32, 32
 ; P8LE-NEXT:    rldicl r0, r0, 32, 32
-; P8LE-NEXT:    rldicl r30, r30, 32, 32
 ; P8LE-NEXT:    subf r8, r11, r8
-; P8LE-NEXT:    rldicl r5, r5, 32, 32
 ; P8LE-NEXT:    subf r9, r0, r9
+; P8LE-NEXT:    rldicl r30, r30, 32, 32
+; P8LE-NEXT:    rldicl r5, r5, 32, 32
 ; P8LE-NEXT:    srwi r8, r8, 1
-; P8LE-NEXT:    subf r10, r30, r10
-; P8LE-NEXT:    add r8, r8, r11
 ; P8LE-NEXT:    srwi r9, r9, 1
-; P8LE-NEXT:    srwi r10, r10, 1
-; P8LE-NEXT:    subf r11, r5, r12
+; P8LE-NEXT:    add r8, r8, r11
+; P8LE-NEXT:    subf r10, r30, r10
 ; P8LE-NEXT:    add r9, r9, r0
+; P8LE-NEXT:    subf r11, r5, r12
+; P8LE-NEXT:    srwi r10, r10, 1
 ; P8LE-NEXT:    srwi r8, r8, 6
-; P8LE-NEXT:    add r10, r10, r30
 ; P8LE-NEXT:    srwi r11, r11, 1
-; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    srwi r9, r9, 6
+; P8LE-NEXT:    add r10, r10, r30
 ; P8LE-NEXT:    mulli r12, r8, 95
-; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    add r5, r11, r5
-; P8LE-NEXT:    mtvsrd f0, r8
+; P8LE-NEXT:    mtvsrd v2, r8
+; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    mulli r8, r9, 95
-; P8LE-NEXT:    mtvsrd f1, r9
-; P8LE-NEXT:    mulli r9, r10, 95
+; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    srwi r5, r5, 6
-; P8LE-NEXT:    mtvsrd f3, r5
-; P8LE-NEXT:    mulli r5, r5, 95
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    mtvsrd f2, r10
+; P8LE-NEXT:    mtvsrd v3, r9
+; P8LE-NEXT:    mulli r9, r10, 95
+; P8LE-NEXT:    mtvsrd v4, r10
+; P8LE-NEXT:    mulli r10, r5, 95
+; P8LE-NEXT:    vmrghh v2, v3, v2
 ; P8LE-NEXT:    subf r3, r12, r3
-; P8LE-NEXT:    xxswapd v6, vs3
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    subf r3, r9, r7
 ; P8LE-NEXT:    subf r4, r8, r4
-; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    mtvsrd f4, r3
-; P8LE-NEXT:    subf r3, r5, r6
-; P8LE-NEXT:    mtvsrd f1, r4
-; P8LE-NEXT:    mtvsrd f5, r3
-; P8LE-NEXT:    xxswapd v5, vs4
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    xxswapd v3, vs0
-; P8LE-NEXT:    xxswapd v4, vs1
-; P8LE-NEXT:    xxswapd v0, vs5
-; P8LE-NEXT:    vmrglh v3, v4, v3
-; P8LE-NEXT:    vmrglh v4, v0, v5
-; P8LE-NEXT:    vmrglh v5, v6, v1
-; P8LE-NEXT:    vmrglw v3, v4, v3
-; P8LE-NEXT:    vmrglw v2, v5, v2
+; P8LE-NEXT:    mtvsrd v3, r3
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    subf r3, r9, r7
+; P8LE-NEXT:    subf r4, r10, r6
+; P8LE-NEXT:    mtvsrd v0, r3
+; P8LE-NEXT:    mtvsrd v1, r4
+; P8LE-NEXT:    vmrghh v3, v5, v3
+; P8LE-NEXT:    mtvsrd v5, r5
+; P8LE-NEXT:    vmrghh v0, v1, v0
+; P8LE-NEXT:    vmrghh v4, v5, v4
+; P8LE-NEXT:    vmrglw v3, v0, v3
+; P8LE-NEXT:    vmrglw v2, v4, v2
 ; P8LE-NEXT:    vadduhm v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: combine_urem_udiv:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r6, v2
 ; P8BE-NEXT:    lis r5, 22765
 ; P8BE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill

 
 ; Don't fold for divisors that are a power of two.
 define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P9LE-LABEL: dont_fold_urem_power_of_two:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 26, 31
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 27, 31
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    vmrglh v3, v4, v3
+; P9LE-NEXT:    vmrghh v3, v4, v3
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
 ; P9LE-NEXT:    subf r4, r5, r4
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 29, 31
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v2, v4, v2
+; P9LE-NEXT:    mtvsrd v2, r3
+; P9LE-NEXT:    vmrghh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_urem_power_of_two:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 27, 31

 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
 ; P8LE-NEXT:    rlwinm r6, r5, 0, 16, 31
 ; P8LE-NEXT:    clrldi r7, r6, 32
 ; P8LE-NEXT:    mulld r3, r7, r3
 ; P8LE-NEXT:    rldicl r7, r4, 48, 48
 ; P8LE-NEXT:    rlwinm r7, r7, 0, 27, 31
-; P8LE-NEXT:    mtvsrd f1, r7
+; P8LE-NEXT:    mtvsrd v3, r7
 ; P8LE-NEXT:    rldicl r3, r3, 32, 32
-; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    subf r6, r3, r6
 ; P8LE-NEXT:    srwi r6, r6, 1
 ; P8LE-NEXT:    add r3, r6, r3
 ; P8LE-NEXT:    clrldi r6, r4, 48
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    rldicl r4, r4, 32, 48
 ; P8LE-NEXT:    rlwinm r6, r6, 0, 26, 31
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    rlwinm r4, r4, 0, 29, 31
-; P8LE-NEXT:    mtvsrd f0, r6
-; P8LE-NEXT:    mtvsrd f3, r4
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v5, vs3
+; P8LE-NEXT:    mtvsrd v2, r6
+; P8LE-NEXT:    mtvsrd v5, r4
+; P8LE-NEXT:    vmrghh v2, v3, v2
 ; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    vmrglh v3, v4, v5
+; P8LE-NEXT:    mtvsrd v4, r3
+; P8LE-NEXT:    vmrghh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_power_of_two:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    ori r3, r3, 8969

 ; P9LE-NEXT:    ori r5, r5, 30865
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    lis r6, 24749
 ; P9LE-NEXT:    ori r6, r6, 47143
 ; P9LE-NEXT:    rldicl r4, r4, 28, 36
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v3, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    rldicl r4, r4, 21, 43
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtvsrd v4, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 31, 17, 31
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    rldicl r4, r4, 24, 40
 ; P9LE-NEXT:    mulli r4, r4, 654
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
-; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    vmrglh v3, v4, v3
+; P9LE-NEXT:    vmrghh v3, v4, v3
+; P9LE-NEXT:    mtvsrd v2, r3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
-; P9LE-NEXT:    vmrglh v2, v2, v4
+; P9LE-NEXT:    vmrghh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_urem_one:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31

 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    li r3, 0
 ; P8LE-NEXT:    lis r8, 24749
-; P8LE-NEXT:    xxlxor v5, v5, v5
+; P8LE-NEXT:    xxlxor v2, v2, v2
 ; P8LE-NEXT:    oris r5, r3, 45590
 ; P8LE-NEXT:    ori r8, r8, 47143
 ; P8LE-NEXT:    oris r3, r3, 51306
 ; P8LE-NEXT:    ori r5, r5, 17097
 ; P8LE-NEXT:    ori r3, r3, 30865
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r7, r4, 16, 48
 ; P8LE-NEXT:    rlwinm r9, r6, 0, 16, 31
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    mulld r5, r9, r5
 ; P8LE-NEXT:    rlwinm r9, r7, 0, 16, 31
 ; P8LE-NEXT:    mulld r8, r9, r8
 ; P8LE-NEXT:    rlwinm r9, r4, 31, 17, 31
 ; P8LE-NEXT:    mulld r3, r9, r3
 ; P8LE-NEXT:    rldicl r5, r5, 28, 36
 ; P8LE-NEXT:    rldicl r8, r8, 21, 43
 ; P8LE-NEXT:    mulli r5, r5, 23
 ; P8LE-NEXT:    rldicl r3, r3, 24, 40
 ; P8LE-NEXT:    mulli r8, r8, 5423
 ; P8LE-NEXT:    mulli r3, r3, 654
 ; P8LE-NEXT:    subf r5, r5, r6
 ; P8LE-NEXT:    subf r6, r8, r7
-; P8LE-NEXT:    mtvsrd f0, r5
+; P8LE-NEXT:    mtvsrd v3, r5
 ; P8LE-NEXT:    subf r3, r3, r4
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    xxswapd v4, vs2
-; P8LE-NEXT:    vmrglh v2, v3, v2
-; P8LE-NEXT:    vmrglh v3, v4, v5
-; P8LE-NEXT:    vmrglw v2, v2, v3
+; P8LE-NEXT:    mtvsrd v4, r6
+; P8LE-NEXT:    mtvsrd v5, r3
+; P8LE-NEXT:    vmrghh v3, v4, v3
+; P8LE-NEXT:    vmrghh v2, v5, v2
+; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_one:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    li r3, 0
 ; P8BE-NEXT:    lis r8, 24749
 ; P8BE-NEXT:    oris r6, r3, 51306

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs1
-; CHECK-P9-NEXT:    xxswapd v3, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1

 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs2
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v4, v5
-; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    vmrghh v3, v4, v3
+; CHECK-P8-NEXT:    vmrghh v2, v2, v5
+; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v4, v2
+; CHECK-P9-NEXT:    mtvsrd v2, r3
+; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
entry:
   ret i64 %1
 }
 
 define <8 x i16> @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v5, r3, r4
-; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    lvx v3, r3, r4
 ; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xxsldwi vs2, v5, v5, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v5
-; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    xscvspdpn f2, v2
+; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
+; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglh v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    xxswapd vs0, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    mfvsrwz r3, f2
+; CHECK-P8-NEXT:    xscvdpsxws f2, f4
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghh v2, v4, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v6, vs3
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    vmrglh v3, v3, v4
-; CHECK-P8-NEXT:    vmrglh v4, v0, v5
-; CHECK-P8-NEXT:    vmrglh v5, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    vmrghh v3, v3, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghh v5, v0, v5
+; CHECK-P8-NEXT:    mtvsrd v1, r3
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
+; CHECK-P8-NEXT:    vmrghh v4, v4, v1
+; CHECK-P8-NEXT:    vmrglw v3, v4, v5
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
entry:
   %1 = fptoui <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    li r6, 32
 ; CHECK-P8-NEXT:    li r5, 16
-; CHECK-P8-NEXT:    lvx v2, r4, r6
+; CHECK-P8-NEXT:    li r6, 32
 ; CHECK-P8-NEXT:    lvx v3, r4, r5
+; CHECK-P8-NEXT:    lvx v2, r4, r6
 ; CHECK-P8-NEXT:    li r6, 48
-; CHECK-P8-NEXT:    xscvspdpn f0, v5
-; CHECK-P8-NEXT:    xxsldwi vs1, v5, v5, 3
+; CHECK-P8-NEXT:    xxsldwi vs0, v5, v5, 3
+; CHECK-P8-NEXT:    xscvspdpn f1, v5
 ; CHECK-P8-NEXT:    lvx v4, r4, r6
-; CHECK-P8-NEXT:    xscvspdpn f4, v2
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f2, v3
 ; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xxswapd vs8, v3
-; CHECK-P8-NEXT:    xscvspdpn f6, v4
+; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
 ; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 3
+; CHECK-P8-NEXT:    xxswapd vs8, v3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xxsldwi vs10, v2, v2, 3
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    xscvspdpn f7, vs7
+; CHECK-P8-NEXT:    xscvspdpn f8, vs8
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    xxsldwi vs9, v3, v3, 1
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    xscvspdpn f2, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f1, f5
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xxsldwi vs0, v3, v3, 1
+; CHECK-P8-NEXT:    xscvspdpn f4, v2
+; CHECK-P8-NEXT:    xscvdpsxws f5, f7
+; CHECK-P8-NEXT:    xxsldwi vs7, v4, v4, 3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 3
+; CHECK-P8-NEXT:    xscvspdpn f6, v4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f1, f8
+; CHECK-P8-NEXT:    xxswapd vs8, v4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    xxswapd vs5, v2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xxsldwi vs12, v2, v2, 1
-; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    xxswapd vs11, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xxswapd v2, v4
+; CHECK-P8-NEXT:    vmrghh v3, v0, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f6, f6
+; CHECK-P8-NEXT:    xscvspdpn f1, vs5
+; CHECK-P8-NEXT:    xxsldwi vs5, v2, v2, 1
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghh v2, v5, v1
+; CHECK-P8-NEXT:    vmrghh v5, v6, v0
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f2, f3
+; CHECK-P8-NEXT:    xscvspdpn f5, vs5
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    xxsldwi vs13, v4, v4, 3
-; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxsldwi v3, v4, v4, 1
-; CHECK-P8-NEXT:    xscvspdpn f10, vs10
+; CHECK-P8-NEXT:    mtvsrd v7, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xxsldwi vs2, v4, v4, 1
+; CHECK-P8-NEXT:    xscvspdpn f8, vs8
+; CHECK-P8-NEXT:    xscvdpsxws f0, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvspdpn f1, vs2
+; CHECK-P8-NEXT:    xscvdpsxws f3, f7
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xscvdpsxws f0, f8
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    xscvdpsxws f6, f6
-; CHECK-P8-NEXT:    xscvspdpn f12, vs12
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    vmrghh v0, v0, v7
+; CHECK-P8-NEXT:    mtvsrd v7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvspdpn f11, vs11
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvspdpn v2, v2
-; CHECK-P8-NEXT:    xscvdpsxws f8, f8
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    mfvsrwz r6, f2
-; CHECK-P8-NEXT:    xscvspdpn f13, vs13
-; CHECK-P8-NEXT:    xscvspdpn v3, v3
-; CHECK-P8-NEXT:    xscvdpsxws f10, f10
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    vmrghh v4, v8, v4
+; CHECK-P8-NEXT:    mtvsrd v8, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f2, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    xscvdpsxws f12, f12
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
-; CHECK-P8-NEXT:    xscvdpsxws v2, v2
-; CHECK-P8-NEXT:    xxswapd v9, vs6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    xxswapd v0, vs5
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    xscvdpsxws f13, f13
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    xscvdpsxws v3, v3
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f9
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
-; CHECK-P8-NEXT:    mtvsrd f9, r6
-; CHECK-P8-NEXT:    xxswapd v6, vs10
-; CHECK-P8-NEXT:    mfvsrwz r6, f11
-; CHECK-P8-NEXT:    mtvsrd f12, r4
-; CHECK-P8-NEXT:    xxswapd v1, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, v2
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f11, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v7, vs11
-; CHECK-P8-NEXT:    mfvsrwz r4, v3
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
-; CHECK-P8-NEXT:    xxswapd v4, vs7
-; CHECK-P8-NEXT:    vmrglh v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v5, vs8
-; CHECK-P8-NEXT:    xxswapd v0, vs2
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    vmrglh v4, v5, v4
-; CHECK-P8-NEXT:    vmrglh v5, v0, v1
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglh v0, v7, v6
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    xxswapd v10, vs1
+; CHECK-P8-NEXT:    vmrghh v1, v1, v9
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghh v7, v8, v7
+; CHECK-P8-NEXT:    vmrghh v6, v6, v9
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
-; CHECK-P8-NEXT:    vmrglh v1, v1, v6
-; CHECK-P8-NEXT:    vmrglh v6, v8, v7
-; CHECK-P8-NEXT:    vmrglh v7, v9, v10
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
-; CHECK-P8-NEXT:    vmrglw v4, v1, v0
-; CHECK-P8-NEXT:    vmrglw v5, v7, v6
+; CHECK-P8-NEXT:    vmrglw v3, v0, v5
+; CHECK-P8-NEXT:    vmrglw v4, v1, v4
+; CHECK-P8-NEXT:    vmrglw v5, v6, v7
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
 ; CHECK-P8-NEXT:    stvx v3, r3, r5
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs1, 0(r4)
-; CHECK-P9-NEXT:    lxv vs3, 16(r4)
-; CHECK-P9-NEXT:    xscvspdpn f5, vs1
-; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-P9-NEXT:    xscvspdpn f8, vs3
-; CHECK-P9-NEXT:    xxswapd vs4, vs1
-; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    lxv vs2, 0(r4)
+; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-P9-NEXT:    xxswapd vs4, vs2
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f4, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f5, f5
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    xscvspdpn f5, vs2
+; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f8, f8
-; CHECK-P9-NEXT:    xxsldwi vs6, vs3, vs3, 3
-; CHECK-P9-NEXT:    xxswapd vs7, vs3
-; CHECK-P9-NEXT:    xscvspdpn f6, vs6
-; CHECK-P9-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-P9-NEXT:    xscvspdpn f7, vs7
-; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    lxv vs1, 16(r4)
+; CHECK-P9-NEXT:    xxsldwi vs6, vs1, vs1, 3
+; CHECK-P9-NEXT:    xxswapd vs3, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f5
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
+; CHECK-P9-NEXT:    xscvspdpn f4, vs6
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    xscvspdpn f2, vs1
+; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
-; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
 ; CHECK-P9-NEXT:    lxv vs0, 32(r4)
-; CHECK-P9-NEXT:    xxsldwi vs9, vs0, vs0, 3
-; CHECK-P9-NEXT:    xxswapd vs10, vs0
-; CHECK-P9-NEXT:    xscvspdpn f9, vs9
-; CHECK-P9-NEXT:    xscvspdpn f10, vs10
-; CHECK-P9-NEXT:    xscvdpsxws f9, f9
-; CHECK-P9-NEXT:    xscvdpsxws f10, f10
-; CHECK-P9-NEXT:    mtvsrd f2, r5
+; CHECK-P9-NEXT:    mtvsrd v4, r5
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
+; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    mtvsrd v4, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    xscvspdpn f2, vs3
+; CHECK-P9-NEXT:    vmrghh v4, v5, v4
+; CHECK-P9-NEXT:    mtvsrd v5, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    xxswapd v3, vs4
+; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    mtvsrd v0, r5
+; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghh v5, v5, v0
+; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrglw v3, v5, v4
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mfvsrwz r5, f1
 ; CHECK-P9-NEXT:    lxv vs1, 48(r4)
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs5
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs6
-; CHECK-P9-NEXT:    xxswapd v5, vs7
-; CHECK-P9-NEXT:    mtvsrd f3, r5
-; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    xxswapd v0, vs3
-; CHECK-P9-NEXT:    vmrglh v4, v5, v4
-; CHECK-P9-NEXT:    xxswapd v5, vs8
-; CHECK-P9-NEXT:    vmrglh v5, v5, v0
+; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    mtvsrd v1, r5
+; CHECK-P9-NEXT:    vmrghh v0, v1, v0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglw v3, v5, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v2, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r4
+; CHECK-P9-NEXT:    mfvsrwz r4, f0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
+; CHECK-P9-NEXT:    mtvsrd v2, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
+; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrglw v2, v2, v0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglh v2, v4, v2
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f10
-; CHECK-P9-NEXT:    mtvsrd f10, r5
-; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    xxswapd v1, vs10
-; CHECK-P9-NEXT:    vmrglh v0, v1, v0
-; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    stxv vs2, 0(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r4
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
+; CHECK-P9-NEXT:    stxv vs2, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xxswapd vs3, vs1

 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs1
-; CHECK-P9-NEXT:    xxswapd v3, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1

 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs2
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v4, v5
-; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    vmrghh v3, v4, v3
+; CHECK-P8-NEXT:    vmrghh v2, v2, v5
+; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v4, v2
+; CHECK-P9-NEXT:    mtvsrd v2, r3
+; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
entry:
   ret i64 %1
 }
 
 define <8 x i16> @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v5, r3, r4
-; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    lvx v3, r3, r4
 ; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xxsldwi vs2, v5, v5, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v5
-; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    xscvspdpn f2, v2
+; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
+; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglh v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    xxswapd vs0, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    mfvsrwz r3, f2
+; CHECK-P8-NEXT:    xscvdpsxws f2, f4
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghh v2, v4, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v6, vs3
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    vmrglh v3, v3, v4
-; CHECK-P8-NEXT:    vmrglh v4, v0, v5
-; CHECK-P8-NEXT:    vmrglh v5, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    vmrghh v3, v3, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghh v5, v0, v5
+; CHECK-P8-NEXT:    mtvsrd v1, r3
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
+; CHECK-P8-NEXT:    vmrghh v4, v4, v1
+; CHECK-P8-NEXT:    vmrglw v3, v4, v5
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
entry:
   %1 = fptosi <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    li r6, 32
 ; CHECK-P8-NEXT:    li r5, 16
-; CHECK-P8-NEXT:    lvx v2, r4, r6
+; CHECK-P8-NEXT:    li r6, 32
 ; CHECK-P8-NEXT:    lvx v3, r4, r5
+; CHECK-P8-NEXT:    lvx v2, r4, r6
 ; CHECK-P8-NEXT:    li r6, 48
-; CHECK-P8-NEXT:    xscvspdpn f0, v5
-; CHECK-P8-NEXT:    xxsldwi vs1, v5, v5, 3
+; CHECK-P8-NEXT:    xxsldwi vs0, v5, v5, 3
+; CHECK-P8-NEXT:    xscvspdpn f1, v5
 ; CHECK-P8-NEXT:    lvx v4, r4, r6
-; CHECK-P8-NEXT:    xscvspdpn f4, v2
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f2, v3
 ; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xxswapd vs8, v3
-; CHECK-P8-NEXT:    xscvspdpn f6, v4
+; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
 ; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 3
+; CHECK-P8-NEXT:    xxswapd vs8, v3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xxsldwi vs10, v2, v2, 3
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    xscvspdpn f7, vs7
+; CHECK-P8-NEXT:    xscvspdpn f8, vs8
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    xxsldwi vs9, v3, v3, 1
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    xscvspdpn f2, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f1, f5
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xxsldwi vs0, v3, v3, 1
+; CHECK-P8-NEXT:    xscvspdpn f4, v2
+; CHECK-P8-NEXT:    xscvdpsxws f5, f7
+; CHECK-P8-NEXT:    xxsldwi vs7, v4, v4, 3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 3
+; CHECK-P8-NEXT:    xscvspdpn f6, v4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f1, f8
+; CHECK-P8-NEXT:    xxswapd vs8, v4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    xxswapd vs5, v2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xxsldwi vs12, v2, v2, 1
-; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    xxswapd vs11, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xxswapd v2, v4
+; CHECK-P8-NEXT:    vmrghh v3, v0, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f6, f6
+; CHECK-P8-NEXT:    xscvspdpn f1, vs5
+; CHECK-P8-NEXT:    xxsldwi vs5, v2, v2, 1
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghh v2, v5, v1
+; CHECK-P8-NEXT:    vmrghh v5, v6, v0
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f2, f3
+; CHECK-P8-NEXT:    xscvspdpn f5, vs5
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    xxsldwi vs13, v4, v4, 3
-; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxsldwi v3, v4, v4, 1
-; CHECK-P8-NEXT:    xscvspdpn f10, vs10
+; CHECK-P8-NEXT:    mtvsrd v7, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xxsldwi vs2, v4, v4, 1
+; CHECK-P8-NEXT:    xscvspdpn f8, vs8
+; CHECK-P8-NEXT:    xscvdpsxws f0, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvspdpn f1, vs2
+; CHECK-P8-NEXT:    xscvdpsxws f3, f7
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xscvdpsxws f0, f8
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    xscvdpsxws f6, f6
-; CHECK-P8-NEXT:    xscvspdpn f12, vs12
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    vmrghh v0, v0, v7
+; CHECK-P8-NEXT:    mtvsrd v7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvspdpn f11, vs11
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvspdpn v2, v2
-; CHECK-P8-NEXT:    xscvdpsxws f8, f8
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    mfvsrwz r6, f2
-; CHECK-P8-NEXT:    xscvspdpn f13, vs13
-; CHECK-P8-NEXT:    xscvspdpn v3, v3
-; CHECK-P8-NEXT:    xscvdpsxws f10, f10
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    vmrghh v4, v8, v4
+; CHECK-P8-NEXT:    mtvsrd v8, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f2, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    xscvdpsxws f12, f12
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
-; CHECK-P8-NEXT:    xscvdpsxws v2, v2
-; CHECK-P8-NEXT:    xxswapd v9, vs6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    xxswapd v0, vs5
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    xscvdpsxws f13, f13
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    xscvdpsxws v3, v3
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f9
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
-; CHECK-P8-NEXT:    mtvsrd f9, r6
-; CHECK-P8-NEXT:    xxswapd v6, vs10
-; CHECK-P8-NEXT:    mfvsrwz r6, f11
-; CHECK-P8-NEXT:    mtvsrd f12, r4
-; CHECK-P8-NEXT:    xxswapd v1, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, v2
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f11, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v7, vs11
-; CHECK-P8-NEXT:    mfvsrwz r4, v3
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
-; CHECK-P8-NEXT:    xxswapd v4, vs7
-; CHECK-P8-NEXT:    vmrglh v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v5, vs8
-; CHECK-P8-NEXT:    xxswapd v0, vs2
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    vmrglh v4, v5, v4
-; CHECK-P8-NEXT:    vmrglh v5, v0, v1
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglh v0, v7, v6
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    xxswapd v10, vs1
+; CHECK-P8-NEXT:    vmrghh v1, v1, v9
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghh v7, v8, v7
+; CHECK-P8-NEXT:    vmrghh v6, v6, v9
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
-; CHECK-P8-NEXT:    vmrglh v1, v1, v6
-; CHECK-P8-NEXT:    vmrglh v6, v8, v7
-; CHECK-P8-NEXT:    vmrglh v7, v9, v10
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
-; CHECK-P8-NEXT:    vmrglw v4, v1, v0
-; CHECK-P8-NEXT:    vmrglw v5, v7, v6
+; CHECK-P8-NEXT:    vmrglw v3, v0, v5
+; CHECK-P8-NEXT:    vmrglw v4, v1, v4
+; CHECK-P8-NEXT:    vmrglw v5, v6, v7
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
 ; CHECK-P8-NEXT:    stvx v3, r3, r5
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs1, 0(r4)
-; CHECK-P9-NEXT:    lxv vs3, 16(r4)
-; CHECK-P9-NEXT:    xscvspdpn f5, vs1
-; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-P9-NEXT:    xscvspdpn f8, vs3
-; CHECK-P9-NEXT:    xxswapd vs4, vs1
-; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    lxv vs2, 0(r4)
+; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-P9-NEXT:    xxswapd vs4, vs2
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f4, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f5, f5
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    xscvspdpn f5, vs2
+; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f8, f8
-; CHECK-P9-NEXT:    xxsldwi vs6, vs3, vs3, 3
-; CHECK-P9-NEXT:    xxswapd vs7, vs3
-; CHECK-P9-NEXT:    xscvspdpn f6, vs6
-; CHECK-P9-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-P9-NEXT:    xscvspdpn f7, vs7
-; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    lxv vs1, 16(r4)
+; CHECK-P9-NEXT:    xxsldwi vs6, vs1, vs1, 3
+; CHECK-P9-NEXT:    xxswapd vs3, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f5
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
+; CHECK-P9-NEXT:    xscvspdpn f4, vs6
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    xscvspdpn f2, vs1
+; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
-; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
 ; CHECK-P9-NEXT:    lxv vs0, 32(r4)
-; CHECK-P9-NEXT:    xxsldwi vs9, vs0, vs0, 3
-; CHECK-P9-NEXT:    xxswapd vs10, vs0
-; CHECK-P9-NEXT:    xscvspdpn f9, vs9
-; CHECK-P9-NEXT:    xscvspdpn f10, vs10
-; CHECK-P9-NEXT:    xscvdpsxws f9, f9
-; CHECK-P9-NEXT:    xscvdpsxws f10, f10
-; CHECK-P9-NEXT:    mtvsrd f2, r5
+; CHECK-P9-NEXT:    mtvsrd v4, r5
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
+; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    mtvsrd v4, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    xscvspdpn f2, vs3
+; CHECK-P9-NEXT:    vmrghh v4, v5, v4
+; CHECK-P9-NEXT:    mtvsrd v5, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    xxswapd v3, vs4
+; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    mtvsrd v0, r5
+; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghh v5, v5, v0
+; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrglw v3, v5, v4
+; CHECK-P9-NEXT:    mfvsrwz r5, f2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mfvsrwz r5, f1
 ; CHECK-P9-NEXT:    lxv vs1, 48(r4)
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs5
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs6
-; CHECK-P9-NEXT:    xxswapd v5, vs7
-; CHECK-P9-NEXT:    mtvsrd f3, r5
-; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    xxswapd v0, vs3
-; CHECK-P9-NEXT:    vmrglh v4, v5, v4
-; CHECK-P9-NEXT:    xxswapd v5, vs8
-; CHECK-P9-NEXT:    vmrglh v5, v5, v0
+; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    mtvsrd v1, r5
+; CHECK-P9-NEXT:    vmrghh v0, v1, v0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglw v3, v5, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v2, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r4
+; CHECK-P9-NEXT:    mfvsrwz r4, f0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
+; CHECK-P9-NEXT:    mtvsrd v2, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
+; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrglw v2, v2, v0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglh v2, v4, v2
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f10
-; CHECK-P9-NEXT:    mtvsrd f10, r5
-; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    xxswapd v1, vs10
-; CHECK-P9-NEXT:    vmrglh v0, v1, v0
-; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    stxv vs2, 0(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r4
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
+; CHECK-P9-NEXT:    stxv vs2, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xxswapd vs3, vs1

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxmrglw vs0, v2, v2
+; CHECK-P8-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-P8-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-P8-NEXT:    xvcvdpuxds v2, vs0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    xxmrglw vs0, v2, v2
+; CHECK-P9-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-P9-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-P9-NEXT:    xvcvdpuxds v2, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs0
entry:
   store <16 x i64> %1, <16 x i64>* %agg.result, align 128
   ret void
 }
 
 define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxmrglw vs0, v2, v2
+; CHECK-P8-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-P8-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-P8-NEXT:    xvcvdpuxds v2, vs0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    xxmrglw vs0, v2, v2
+; CHECK-P9-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-P9-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-P9-NEXT:    xvcvdpuxds v2, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs0

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs1
-; CHECK-P9-NEXT:    xxswapd v3, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0

 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs2
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
-; CHECK-P8-NEXT:    vmrglb v3, v4, v5
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    vmrghb v3, v4, v3
+; CHECK-P8-NEXT:    vmrghb v2, v2, v5
+; CHECK-P8-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v4, v2
+; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
entry:
   ret i32 %1
 }
 
 define i64 @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v5, r3, r4
-; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    lvx v3, r3, r4
 ; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xxsldwi vs2, v5, v5, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v5
-; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    xscvspdpn f2, v2
+; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
+; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglb v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    xxswapd vs0, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    mfvsrwz r3, f2
+; CHECK-P8-NEXT:    xscvdpsxws f2, f4
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghb v2, v4, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v6, vs3
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    vmrglb v3, v3, v4
-; CHECK-P8-NEXT:    vmrglb v4, v0, v5
-; CHECK-P8-NEXT:    vmrglb v5, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    vmrghb v3, v3, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghb v5, v0, v5
+; CHECK-P8-NEXT:    mtvsrd v1, r3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
+; CHECK-P8-NEXT:    vmrghb v4, v4, v1
+; CHECK-P8-NEXT:    vmrglh v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
entry:
   %1 = fptoui <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }
 
 define <16 x i8> @test16elt(<16 x float>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v4, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    lvx v3, r3, r4
-; CHECK-P8-NEXT:    li r4, 32
-; CHECK-P8-NEXT:    xscvspdpn f2, v2
-; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v3
-; CHECK-P8-NEXT:    xxswapd vs1, v2
-; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 1
-; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
-; CHECK-P8-NEXT:    lvx v2, r3, r4
+; CHECK-P8-NEXT:    lvx v2, r3, r5
+; CHECK-P8-NEXT:    xxsldwi vs0, v4, v4, 3
+; CHECK-P8-NEXT:    xxswapd vs2, v4
+; CHECK-P8-NEXT:    xxsldwi vs4, v4, v4, 1
+; CHECK-P8-NEXT:    xscvspdpn f1, v4
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
+; CHECK-P8-NEXT:    xxsldwi vs6, v3, v3, 3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xxswapd vs6, v3
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 1
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xxsldwi vs8, v2, v2, 3
-; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxswapd vs9, v2
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    xxswapd vs7, v3
+; CHECK-P8-NEXT:    xscvspdpn f2, vs2
+; CHECK-P8-NEXT:    xxsldwi vs8, v3, v3, 1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
+; CHECK-P8-NEXT:    xxsldwi vs9, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f6, vs6
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    xscvdpsxws f4, f4
 ; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f0, f5
-; CHECK-P8-NEXT:    xxswapd v0, vs4
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xxswapd vs0, v2
+; CHECK-P8-NEXT:    mfvsrwz r5, f2
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtvsrd v4, r5
+; CHECK-P8-NEXT:    mfvsrwz r5, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f6
-; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    vmrghb v3, v4, v3
+; CHECK-P8-NEXT:    mtvsrd v4, r5
+; CHECK-P8-NEXT:    mfvsrwz r5, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f7
-; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f0, f8
-; CHECK-P8-NEXT:    xxswapd v5, vs7
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xscvdpsxws f1, f9
-; CHECK-P8-NEXT:    xxswapd v1, vs8
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    vmrglb v3, v4, v3
-; CHECK-P8-NEXT:    xxswapd v4, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    xxswapd v7, vs3
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    vmrglb v4, v4, v5
-; CHECK-P8-NEXT:    xxswapd v5, vs5
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    xscvdpsxws f4, f8
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    lvx v9, r3, r4
-; CHECK-P8-NEXT:    vmrglb v1, v6, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs1
+; CHECK-P8-NEXT:    lvx v0, r3, r4
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxsldwi vs2, v9, v9, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v9
-; CHECK-P8-NEXT:    xxswapd vs3, v9
-; CHECK-P8-NEXT:    xxsldwi vs5, v9, v9, 1
+; CHECK-P8-NEXT:    xscvspdpn f5, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xxsldwi vs3, v0, v0, 3
+; CHECK-P8-NEXT:    mtvsrd v1, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    xxswapd vs4, v0
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
+; CHECK-P8-NEXT:    mtvsrd v7, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    xxsldwi vs0, v0, v0, 1
+; CHECK-P8-NEXT:    xscvspdpn f2, v0
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f6, f9
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghb v2, v6, v1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtvsrd v6, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghb v4, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v5, r5
+; CHECK-P8-NEXT:    vmrghb v0, v6, v1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v9, vs4
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v6, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    vmrglb v2, v0, v7
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v7, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    vmrglb v5, v8, v5
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    xxswapd v10, vs3
-; CHECK-P8-NEXT:    vmrglb v0, v0, v6
+; CHECK-P8-NEXT:    vmrghb v5, v5, v7
+; CHECK-P8-NEXT:    vmrghb v1, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtvsrd v7, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mtvsrd v9, r3
+; CHECK-P8-NEXT:    vmrghb v7, v8, v7
+; CHECK-P8-NEXT:    vmrghb v6, v6, v9
 ; CHECK-P8-NEXT:    vmrglh v3, v4, v3
-; CHECK-P8-NEXT:    vmrglb v6, v8, v7
-; CHECK-P8-NEXT:    vmrglb v7, v9, v10
-; CHECK-P8-NEXT:    vmrglh v2, v2, v1
-; CHECK-P8-NEXT:    vmrglh v4, v0, v5
-; CHECK-P8-NEXT:    vmrglh v5, v7, v6
+; CHECK-P8-NEXT:    vmrglh v2, v5, v2
+; CHECK-P8-NEXT:    vmrglh v4, v1, v0
+; CHECK-P8-NEXT:    vmrglh v5, v6, v7
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    lxv vs3, 0(r3)
+; CHECK-P9-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-P9-NEXT:    xscvspdpn f4, vs4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    lxv vs0, 48(r3)
+; CHECK-P9-NEXT:    lxv vs1, 32(r3)
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    xxswapd vs4, vs3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
+; CHECK-P9-NEXT:    xscvspdpn f4, vs4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    xscvspdpn f4, vs3
+; CHECK-P9-NEXT:    xxsldwi vs3, vs3, vs3, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f3
 ; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    lxv vs0, 48(r3)
-; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs4, 16(r3)
+; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 3
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    xxswapd vs2, vs4
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xscvspdpn f2, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 1
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v4, v5, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v4, v5, v4
-; CHECK-P9-NEXT:    xxswapd v5, vs1
-; CHECK-P9-NEXT:    xxswapd v0, vs0
-; CHECK-P9-NEXT:    vmrglb v5, v5, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r3
+; CHECK-P9-NEXT:    vmrghb v5, v5, v0
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)

 ; CHECK-P8-NEXT:    mtvsrd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs1
-; CHECK-P9-NEXT:    xxswapd v3, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0

 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs2
-; CHECK-P8-NEXT:    xxswapd v5, vs3
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
-; CHECK-P8-NEXT:    vmrglb v3, v4, v5
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    vmrghb v3, v4, v3
+; CHECK-P8-NEXT:    vmrghb v2, v2, v5
+; CHECK-P8-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v4, v2
+; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
entry:
   ret i32 %1
 }
 
 define i64 @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v5, r3, r4
-; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    lvx v3, r3, r4
 ; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xxsldwi vs2, v5, v5, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v5
-; CHECK-P8-NEXT:    xxswapd vs3, v5
-; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xxswapd vs1, v2
+; CHECK-P8-NEXT:    xscvspdpn f2, v2
+; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
+; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v1, vs4
-; CHECK-P8-NEXT:    vmrglb v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    xxswapd vs0, v3
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    mfvsrwz r3, f2
+; CHECK-P8-NEXT:    xscvdpsxws f2, f4
+; CHECK-P8-NEXT:    xscvspdpn f1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f5
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghb v2, v4, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v6, vs3
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    vmrglb v3, v3, v4
-; CHECK-P8-NEXT:    vmrglb v4, v0, v5
-; CHECK-P8-NEXT:    vmrglb v5, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    vmrghb v3, v3, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mtvsrd v0, r4
+; CHECK-P8-NEXT:    mtvsrd v5, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghb v5, v0, v5
+; CHECK-P8-NEXT:    mtvsrd v1, r3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
+; CHECK-P8-NEXT:    vmrghb v4, v4, v1
+; CHECK-P8-NEXT:    vmrglh v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
entry:
   %1 = fptosi <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }
 
 define <16 x i8> @test16elt_signed(<16 x float>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    lvx v2, 0, r3
+; CHECK-P8-NEXT:    lvx v4, 0, r3
 ; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    lvx v3, r3, r4
-; CHECK-P8-NEXT:    li r4, 32
-; CHECK-P8-NEXT:    xscvspdpn f2, v2
-; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v3
-; CHECK-P8-NEXT:    xxswapd vs1, v2
-; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 1
-; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
-; CHECK-P8-NEXT:    lvx v2, r3, r4
+; CHECK-P8-NEXT:    lvx v2, r3, r5
+; CHECK-P8-NEXT:    xxsldwi vs0, v4, v4, 3
+; CHECK-P8-NEXT:    xxswapd vs2, v4
+; CHECK-P8-NEXT:    xxsldwi vs4, v4, v4, 1
+; CHECK-P8-NEXT:    xscvspdpn f1, v4
+; CHECK-P8-NEXT:    xscvspdpn f3, v3
+; CHECK-P8-NEXT:    xxsldwi vs6, v3, v3, 3
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
-; CHECK-P8-NEXT:    xxswapd vs6, v3
-; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 1
-; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xxsldwi vs8, v2, v2, 3
-; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxswapd vs9, v2
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
-; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    xxswapd vs7, v3
+; CHECK-P8-NEXT:    xscvspdpn f2, vs2
+; CHECK-P8-NEXT:    xxsldwi vs8, v3, v3, 1
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
+; CHECK-P8-NEXT:    xxsldwi vs9, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f6, vs6
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    xscvdpsxws f4, f4
 ; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f0, f5
-; CHECK-P8-NEXT:    xxswapd v0, vs4
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xxswapd vs0, v2
+; CHECK-P8-NEXT:    mfvsrwz r5, f2
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtvsrd v4, r5
+; CHECK-P8-NEXT:    mfvsrwz r5, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f6
-; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    vmrghb v3, v4, v3
+; CHECK-P8-NEXT:    mtvsrd v4, r5
+; CHECK-P8-NEXT:    mfvsrwz r5, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f7
-; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f0, f8
-; CHECK-P8-NEXT:    xxswapd v5, vs7
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xscvdpsxws f1, f9
-; CHECK-P8-NEXT:    xxswapd v1, vs8
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    vmrglb v3, v4, v3
-; CHECK-P8-NEXT:    xxswapd v4, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    xxswapd v7, vs3
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    vmrglb v4, v4, v5
-; CHECK-P8-NEXT:    xxswapd v5, vs5
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    xscvdpsxws f4, f8
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    lvx v9, r3, r4
-; CHECK-P8-NEXT:    vmrglb v1, v6, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs1
+; CHECK-P8-NEXT:    lvx v0, r3, r4
+; CHECK-P8-NEXT:    mfvsrwz r3, f1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
-; CHECK-P8-NEXT:    xxsldwi vs2, v9, v9, 3
-; CHECK-P8-NEXT:    xscvspdpn f4, v9
-; CHECK-P8-NEXT:    xxswapd vs3, v9
-; CHECK-P8-NEXT:    xxsldwi vs5, v9, v9, 1
+; CHECK-P8-NEXT:    xscvspdpn f5, v2
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xxsldwi vs3, v0, v0, 3
+; CHECK-P8-NEXT:    mtvsrd v1, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    xxswapd vs4, v0
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    xscvspdpn f2, vs2
+; CHECK-P8-NEXT:    mtvsrd v7, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    xxsldwi vs0, v0, v0, 1
+; CHECK-P8-NEXT:    xscvspdpn f2, v0
 ; CHECK-P8-NEXT:    xscvspdpn f3, vs3
-; CHECK-P8-NEXT:    xscvspdpn f5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    xscvdpsxws f4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f6, f9
+; CHECK-P8-NEXT:    xscvspdpn f4, vs4
+; CHECK-P8-NEXT:    xscvspdpn f0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f4, f4
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    vmrghb v2, v6, v1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtvsrd v6, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    vmrghb v4, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v5, r5
+; CHECK-P8-NEXT:    vmrghb v0, v6, v1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    xxswapd v9, vs4
-; CHECK-P8-NEXT:    mtvsrd f1, r3
+; CHECK-P8-NEXT:    mtvsrd v6, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    vmrglb v2, v0, v7
-; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v7, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    vmrglb v5, v8, v5
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    xxswapd v10, vs3
-; CHECK-P8-NEXT:    vmrglb v0, v0, v6
+; CHECK-P8-NEXT:    vmrghb v5, v5, v7
+; CHECK-P8-NEXT:    vmrghb v1, v1, v6
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtvsrd v7, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mtvsrd v9, r3
+; CHECK-P8-NEXT:    vmrghb v7, v8, v7
+; CHECK-P8-NEXT:    vmrghb v6, v6, v9
 ; CHECK-P8-NEXT:    vmrglh v3, v4, v3
-; CHECK-P8-NEXT:    vmrglb v6, v8, v7
-; CHECK-P8-NEXT:    vmrglb v7, v9, v10
-; CHECK-P8-NEXT:    vmrglh v2, v2, v1
-; CHECK-P8-NEXT:    vmrglh v4, v0, v5
-; CHECK-P8-NEXT:    vmrglh v5, v7, v6
+; CHECK-P8-NEXT:    vmrglh v2, v5, v2
+; CHECK-P8-NEXT:    vmrglh v4, v1, v0
+; CHECK-P8-NEXT:    vmrglh v5, v6, v7
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    lxv vs3, 0(r3)
+; CHECK-P9-NEXT:    xxsldwi vs4, vs3, vs3, 3
+; CHECK-P9-NEXT:    xscvspdpn f4, vs4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    lxv vs0, 48(r3)
+; CHECK-P9-NEXT:    lxv vs1, 32(r3)
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    xxswapd vs4, vs3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
+; CHECK-P9-NEXT:    xscvspdpn f4, vs4
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    xscvspdpn f4, vs3
+; CHECK-P9-NEXT:    xxsldwi vs3, vs3, vs3, 1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    mfvsrwz r3, f4
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f3
 ; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    lxv vs0, 48(r3)
-; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs4, 16(r3)
+; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 3
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    xxswapd vs2, vs4
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xscvspdpn f2, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 1
-; CHECK-P9-NEXT:    xscvspdpn f2, vs2
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v3, v4, v3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglb v3, v4, v3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v4, v5, v4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v4, v5, v4
-; CHECK-P9-NEXT:    xxswapd v5, vs1
-; CHECK-P9-NEXT:    xxswapd v0, vs0
-; CHECK-P9-NEXT:    vmrglb v5, v5, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r3
+; CHECK-P9-NEXT:    vmrghb v5, v5, v0
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

 
 define i32 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglh v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
 ; CHECK-BE-NEXT:    mfvsrwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2

 ; CHECK-P8-NEXT:    xscvdpsxws f2, f0
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    xxswapd v2, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xxswapd v5, vs1
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    vmrghh v2, v4, v2
+; CHECK-P8-NEXT:    vmrghh v3, v5, v3
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
-; CHECK-P9-NEXT:    xxswapd v4, vs0
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
+; CHECK-P9-NEXT:    mtvsrd v4, r3
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1

 ; CHECK-P8-NEXT:    xscvdpsxws f5, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f2
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs4
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs5
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs6
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v1, vs7
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs2
-; CHECK-P8-NEXT:    vmrglh v2, v5, v2
-; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    vmrglh v3, v0, v3
-; CHECK-P8-NEXT:    vmrglh v4, v6, v4
-; CHECK-P8-NEXT:    vmrglh v5, v5, v1
+; CHECK-P8-NEXT:    vmrghh v2, v0, v2
+; CHECK-P8-NEXT:    vmrghh v3, v1, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    vmrghh v4, v0, v4
+; CHECK-P8-NEXT:    vmrghh v5, v1, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs3, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    li r5, 16
+; CHECK-P8-NEXT:    lxvd2x vs2, 0, r4
 ; CHECK-P8-NEXT:    li r6, 32
-; CHECK-P8-NEXT:    lxvd2x vs1, r4, r5
-; CHECK-P8-NEXT:    lxvd2x vs2, r4, r6
-; CHECK-P8-NEXT:    li r6, 48
-; CHECK-P8-NEXT:    lxvd2x vs3, r4, r6
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lxvd2x vs3, r4, r5
+; CHECK-P8-NEXT:    lxvd2x vs1, r4, r6
 ; CHECK-P8-NEXT:    li r6, 64
-; CHECK-P8-NEXT:    xscvdpsxws f4, f0
+; CHECK-P8-NEXT:    lxvd2x vs0, r4, r7
 ; CHECK-P8-NEXT:    lxvd2x vs5, r4, r6
-; CHECK-P8-NEXT:    li r6, 80
-; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    xscvdpsxws f6, f1
-; CHECK-P8-NEXT:    lxvd2x vs7, r4, r6
+; CHECK-P8-NEXT:    li r7, 80
 ; CHECK-P8-NEXT:    li r6, 96
-; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    xscvdpsxws f8, f2
-; CHECK-P8-NEXT:    lxvd2x vs9, r4, r6
+; CHECK-P8-NEXT:    xscvdpsxws f4, f2
+; CHECK-P8-NEXT:    lxvd2x vs7, r4, r7
+; CHECK-P8-NEXT:    lxvd2x vs10, r4, r6
 ; CHECK-P8-NEXT:    li r6, 112
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
-; CHECK-P8-NEXT:    xscvdpsxws f10, f3
-; CHECK-P8-NEXT:    lxvd2x vs11, r4, r6
+; CHECK-P8-NEXT:    xscvdpsxws f6, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    xscvdpsxws f12, f5
+; CHECK-P8-NEXT:    xscvdpsxws f8, f1
+; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f9, f0
+; CHECK-P8-NEXT:    xxswapd vs0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f11, f5
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f13, f7
+; CHECK-P8-NEXT:    xscvdpsxws f12, f7
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
-; CHECK-P8-NEXT:    xscvdpsxws v2, f9
-; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws v3, f11
-; CHECK-P8-NEXT:    xxswapd vs11, vs11
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mfvsrwz r7, f4
+; CHECK-P8-NEXT:    lxvd2x vs4, r4, r6
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f13, f10
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs4
+; CHECK-P8-NEXT:    xscvdpsxws f6, f4
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f9
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f10
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs6
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mtvsrd v0, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f12
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f13
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xxswapd vs6, vs10
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f12, r4
-; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mfvsrwz r4, v2
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, v3
-; CHECK-P8-NEXT:    mtvsrd v2, r4
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    xxswapd v2, v2
-; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    mtvsrd v3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v3, v3
+; CHECK-P8-NEXT:    mtvsrd v7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    xxswapd vs2, vs4
+; CHECK-P8-NEXT:    mtvsrd v2, r7
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xscvdpsxws f7, f7
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f6
+; CHECK-P8-NEXT:    vmrghh v2, v8, v2
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    vmrghh v3, v9, v3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
-; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f9
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
-; CHECK-P8-NEXT:    vmrglh v4, v8, v4
-; CHECK-P8-NEXT:    xxswapd v8, vs3
-; CHECK-P8-NEXT:    vmrglh v5, v9, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    vmrglh v0, v10, v0
-; CHECK-P8-NEXT:    xxswapd v10, vs7
-; CHECK-P8-NEXT:    vmrglh v1, v8, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs9
-; CHECK-P8-NEXT:    vmrglh v6, v9, v6
-; CHECK-P8-NEXT:    xxswapd v9, vs0
-; CHECK-P8-NEXT:    vmrglh v7, v10, v7
-; CHECK-P8-NEXT:    vmrglh v2, v8, v2
-; CHECK-P8-NEXT:    vmrglh v3, v9, v3
-; CHECK-P8-NEXT:    vmrglw v4, v5, v4
-; CHECK-P8-NEXT:    vmrglw v5, v1, v0
-; CHECK-P8-NEXT:    vmrglw v0, v7, v6
+; CHECK-P8-NEXT:    vmrghh v4, v8, v4
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f7
+; CHECK-P8-NEXT:    vmrghh v5, v9, v5
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    vmrghh v0, v8, v0
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    vmrghh v1, v9, v1
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghh v6, v8, v6
+; CHECK-P8-NEXT:    vmrghh v7, v9, v7
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    vmrglw v3, v5, v4
+; CHECK-P8-NEXT:    vmrglw v4, v1, v0
+; CHECK-P8-NEXT:    vmrglw v5, v7, v6
+; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
+; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
-; CHECK-P8-NEXT:    stvx v3, 0, r3
-; CHECK-P8-NEXT:    xxmrgld v2, v2, v0
-; CHECK-P8-NEXT:    stvx v2, r3, r5
+; CHECK-P8-NEXT:    stvx v3, r3, r5
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs4, 0(r4)
-; CHECK-P9-NEXT:    lxv vs3, 16(r4)
-; CHECK-P9-NEXT:    lxv vs2, 32(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f5, f4
-; CHECK-P9-NEXT:    lxv vs1, 48(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f6, f3
-; CHECK-P9-NEXT:    lxv vs0, 64(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f7, f2
-; CHECK-P9-NEXT:    xscvdpsxws f8, f1
-; CHECK-P9-NEXT:    xxswapd vs4, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
-; CHECK-P9-NEXT:    xscvdpsxws f9, f0
+; CHECK-P9-NEXT:    lxv vs3, 0(r4)
+; CHECK-P9-NEXT:    lxv vs2, 16(r4)
+; CHECK-P9-NEXT:    lxv vs1, 32(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f4, f3
+; CHECK-P9-NEXT:    lxv vs0, 48(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f5, f2
+; CHECK-P9-NEXT:    xscvdpsxws f6, f1
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    xscvdpsxws f7, f0
+; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
+; CHECK-P9-NEXT:    mtvsrd v2, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtvsrd v4, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
+; CHECK-P9-NEXT:    mtvsrd v5, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    lxv vs3, 64(r4)
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs5
-; CHECK-P9-NEXT:    xxswapd v5, vs8
-; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    mtvsrd f3, r5
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r5
-; CHECK-P9-NEXT:    xxswapd vs0, vs0
-; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    xxswapd v1, vs2
 ; CHECK-P9-NEXT:    lxv vs2, 80(r4)
-; CHECK-P9-NEXT:    xxswapd v3, vs4
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    xxswapd v4, vs3
-; CHECK-P9-NEXT:    xscvdpsxws f3, f2
-; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    vmrghh v2, v2, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs7
-; CHECK-P9-NEXT:    mtvsrd f1, r5
+; CHECK-P9-NEXT:    lxv vs1, 96(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f4, f3
+; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    vmrghh v3, v3, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v1
-; CHECK-P9-NEXT:    xxswapd v1, vs1
-; CHECK-P9-NEXT:    mtvsrd f0, r5
-; CHECK-P9-NEXT:    vmrglh v5, v5, v1
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    xxswapd v1, vs0
 ; CHECK-P9-NEXT:    lxv vs0, 112(r4)
-; CHECK-P9-NEXT:    lxv vs1, 96(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    vmrghh v5, v5, v0
+; CHECK-P9-NEXT:    mfvsrwz r4, f4
+; CHECK-P9-NEXT:    vmrglw v4, v5, v4
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r4
+; CHECK-P9-NEXT:    xscvdpsxws f3, f2
+; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    xxmrgld vs4, v4, v2
+; CHECK-P9-NEXT:    mtvsrd v2, r4
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    stxv vs4, 0(r3)
+; CHECK-P9-NEXT:    mfvsrwz r4, f3
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    vmrglw v3, v5, v4
-; CHECK-P9-NEXT:    xxmrgld vs4, v3, v2
-; CHECK-P9-NEXT:    xxswapd v2, vs3
-; CHECK-P9-NEXT:    vmrglh v0, v0, v1
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r4
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
-; CHECK-P9-NEXT:    stxv vs4, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs4, 48(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
 ; CHECK-BE-NEXT:    lxv vs3, 32(r4)

 
 define i32 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglh v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
 ; CHECK-BE-NEXT:    mfvsrwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2

 ; CHECK-P8-NEXT:    xscvdpsxws f2, f0
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    xxswapd v2, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xxswapd v5, vs1
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglh v3, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    vmrghh v2, v4, v2
+; CHECK-P8-NEXT:    vmrghh v3, v5, v3
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
-; CHECK-P9-NEXT:    xxswapd v4, vs0
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
+; CHECK-P9-NEXT:    mtvsrd v4, r3
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1

 ; CHECK-P8-NEXT:    xscvdpsxws f5, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f2
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs4
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs5
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs6
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v1, vs7
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs2
-; CHECK-P8-NEXT:    vmrglh v2, v5, v2
-; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    vmrglh v3, v0, v3
-; CHECK-P8-NEXT:    vmrglh v4, v6, v4
-; CHECK-P8-NEXT:    vmrglh v5, v5, v1
+; CHECK-P8-NEXT:    vmrghh v2, v0, v2
+; CHECK-P8-NEXT:    vmrghh v3, v1, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    vmrghh v4, v0, v4
+; CHECK-P8-NEXT:    vmrghh v5, v1, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs3, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    li r5, 16
+; CHECK-P8-NEXT:    lxvd2x vs2, 0, r4
 ; CHECK-P8-NEXT:    li r6, 32
-; CHECK-P8-NEXT:    lxvd2x vs1, r4, r5
-; CHECK-P8-NEXT:    lxvd2x vs2, r4, r6
-; CHECK-P8-NEXT:    li r6, 48
-; CHECK-P8-NEXT:    lxvd2x vs3, r4, r6
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lxvd2x vs3, r4, r5
+; CHECK-P8-NEXT:    lxvd2x vs1, r4, r6
 ; CHECK-P8-NEXT:    li r6, 64
-; CHECK-P8-NEXT:    xscvdpsxws f4, f0
+; CHECK-P8-NEXT:    lxvd2x vs0, r4, r7
 ; CHECK-P8-NEXT:    lxvd2x vs5, r4, r6
-; CHECK-P8-NEXT:    li r6, 80
-; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    xscvdpsxws f6, f1
-; CHECK-P8-NEXT:    lxvd2x vs7, r4, r6
+; CHECK-P8-NEXT:    li r7, 80
 ; CHECK-P8-NEXT:    li r6, 96
-; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    xscvdpsxws f8, f2
-; CHECK-P8-NEXT:    lxvd2x vs9, r4, r6
+; CHECK-P8-NEXT:    xscvdpsxws f4, f2
+; CHECK-P8-NEXT:    lxvd2x vs7, r4, r7
+; CHECK-P8-NEXT:    lxvd2x vs10, r4, r6
 ; CHECK-P8-NEXT:    li r6, 112
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
-; CHECK-P8-NEXT:    xscvdpsxws f10, f3
-; CHECK-P8-NEXT:    lxvd2x vs11, r4, r6
+; CHECK-P8-NEXT:    xscvdpsxws f6, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    xscvdpsxws f12, f5
+; CHECK-P8-NEXT:    xscvdpsxws f8, f1
+; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xscvdpsxws f9, f0
+; CHECK-P8-NEXT:    xxswapd vs0, vs0
+; CHECK-P8-NEXT:    xscvdpsxws f11, f5
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    xscvdpsxws f13, f7
+; CHECK-P8-NEXT:    xscvdpsxws f12, f7
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
-; CHECK-P8-NEXT:    xscvdpsxws v2, f9
-; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    xscvdpsxws v3, f11
-; CHECK-P8-NEXT:    xxswapd vs11, vs11
-; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mfvsrwz r7, f4
+; CHECK-P8-NEXT:    lxvd2x vs4, r4, r6
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xscvdpsxws f13, f10
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs4
+; CHECK-P8-NEXT:    xscvdpsxws f6, f4
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f9
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f10
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs6
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mtvsrd v0, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f12
+; CHECK-P8-NEXT:    xscvdpsxws f1, f1
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f13
+; CHECK-P8-NEXT:    xscvdpsxws f0, f0
+; CHECK-P8-NEXT:    mtvsrd v6, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    xxswapd vs6, vs10
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f12, r4
-; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mfvsrwz r4, v2
-; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, v3
-; CHECK-P8-NEXT:    mtvsrd v2, r4
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    xxswapd v2, v2
-; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    mtvsrd v3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v3, v3
+; CHECK-P8-NEXT:    mtvsrd v7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    xxswapd vs2, vs4
+; CHECK-P8-NEXT:    mtvsrd v2, r7
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    xscvdpsxws f7, f7
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    xscvdpsxws f4, f6
+; CHECK-P8-NEXT:    vmrghh v2, v8, v2
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    xscvdpsxws f2, f2
+; CHECK-P8-NEXT:    vmrghh v3, v9, v3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
-; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f9
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
-; CHECK-P8-NEXT:    vmrglh v4, v8, v4
-; CHECK-P8-NEXT:    xxswapd v8, vs3
-; CHECK-P8-NEXT:    vmrglh v5, v9, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    vmrglh v0, v10, v0
-; CHECK-P8-NEXT:    xxswapd v10, vs7
-; CHECK-P8-NEXT:    vmrglh v1, v8, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs9
-; CHECK-P8-NEXT:    vmrglh v6, v9, v6
-; CHECK-P8-NEXT:    xxswapd v9, vs0
-; CHECK-P8-NEXT:    vmrglh v7, v10, v7
-; CHECK-P8-NEXT:    vmrglh v2, v8, v2
-; CHECK-P8-NEXT:    vmrglh v3, v9, v3
-; CHECK-P8-NEXT:    vmrglw v4, v5, v4
-; CHECK-P8-NEXT:    vmrglw v5, v1, v0
-; CHECK-P8-NEXT:    vmrglw v0, v7, v6
+; CHECK-P8-NEXT:    vmrghh v4, v8, v4
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f7
+; CHECK-P8-NEXT:    vmrghh v5, v9, v5
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    vmrghh v0, v8, v0
+; CHECK-P8-NEXT:    mtvsrd v8, r4
+; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    vmrghh v1, v9, v1
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghh v6, v8, v6
+; CHECK-P8-NEXT:    vmrghh v7, v9, v7
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    vmrglw v3, v5, v4
+; CHECK-P8-NEXT:    vmrglw v4, v1, v0
+; CHECK-P8-NEXT:    vmrglw v5, v7, v6
+; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
+; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
-; CHECK-P8-NEXT:    stvx v3, 0, r3
-; CHECK-P8-NEXT:    xxmrgld v2, v2, v0
-; CHECK-P8-NEXT:    stvx v2, r3, r5
+; CHECK-P8-NEXT:    stvx v3, r3, r5
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs4, 0(r4)
-; CHECK-P9-NEXT:    lxv vs3, 16(r4)
-; CHECK-P9-NEXT:    lxv vs2, 32(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f5, f4
-; CHECK-P9-NEXT:    lxv vs1, 48(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f6, f3
-; CHECK-P9-NEXT:    lxv vs0, 64(r4)
-; CHECK-P9-NEXT:    xscvdpsxws f7, f2
-; CHECK-P9-NEXT:    xscvdpsxws f8, f1
-; CHECK-P9-NEXT:    xxswapd vs4, vs4
-; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
-; CHECK-P9-NEXT:    xscvdpsxws f9, f0
+; CHECK-P9-NEXT:    lxv vs3, 0(r4)
+; CHECK-P9-NEXT:    lxv vs2, 16(r4)
+; CHECK-P9-NEXT:    lxv vs1, 32(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f4, f3
+; CHECK-P9-NEXT:    lxv vs0, 48(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f5, f2
+; CHECK-P9-NEXT:    xscvdpsxws f6, f1
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    xscvdpsxws f7, f0
+; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    mfvsrwz r5, f4
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
+; CHECK-P9-NEXT:    mtvsrd v2, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mtvsrd v3, r5
+; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtvsrd v4, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
+; CHECK-P9-NEXT:    mtvsrd v5, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    lxv vs3, 64(r4)
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs5
-; CHECK-P9-NEXT:    xxswapd v5, vs8
-; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    mtvsrd f3, r5
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r5
-; CHECK-P9-NEXT:    xxswapd vs0, vs0
-; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    xxswapd v1, vs2
 ; CHECK-P9-NEXT:    lxv vs2, 80(r4)
-; CHECK-P9-NEXT:    xxswapd v3, vs4
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    xxswapd v4, vs3
-; CHECK-P9-NEXT:    xscvdpsxws f3, f2
-; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    vmrghh v2, v2, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs7
-; CHECK-P9-NEXT:    mtvsrd f1, r5
+; CHECK-P9-NEXT:    lxv vs1, 96(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f4, f3
+; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    vmrghh v3, v3, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
 ; CHECK-P9-NEXT:    mfvsrwz r5, f0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v1
-; CHECK-P9-NEXT:    xxswapd v1, vs1
-; CHECK-P9-NEXT:    mtvsrd f0, r5
-; CHECK-P9-NEXT:    vmrglh v5, v5, v1
-; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    xxswapd v1, vs0
 ; CHECK-P9-NEXT:    lxv vs0, 112(r4)
-; CHECK-P9-NEXT:    lxv vs1, 96(r4)
+; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    vmrghh v4, v4, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r5
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    vmrghh v5, v5, v0
+; CHECK-P9-NEXT:    mfvsrwz r4, f4
+; CHECK-P9-NEXT:    vmrglw v4, v5, v4
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r4
+; CHECK-P9-NEXT:    xscvdpsxws f3, f2
+; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    xxmrgld vs4, v4, v2
+; CHECK-P9-NEXT:    mtvsrd v2, r4
+; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghh v2, v3, v2
+; CHECK-P9-NEXT:    stxv vs4, 0(r3)
+; CHECK-P9-NEXT:    mfvsrwz r4, f3
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    vmrglw v3, v5, v4
-; CHECK-P9-NEXT:    xxmrgld vs4, v3, v2
-; CHECK-P9-NEXT:    xxswapd v2, vs3
-; CHECK-P9-NEXT:    vmrglh v0, v0, v1
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghh v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
+; CHECK-P9-NEXT:    mtvsrd v4, r4
 ; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    vmrglh v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    vmrglh v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglh v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r4
+; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
-; CHECK-P9-NEXT:    stxv vs4, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs4, 48(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
 ; CHECK-BE-NEXT:    lxv vs3, 32(r4)

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

 
 define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpuxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglw v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpuxws f0, v2
 ; CHECK-P9-NEXT:    mffprwz r3, f0

 
 define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglw v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
 ; CHECK-P9-NEXT:    mffprwz r3, f0

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

 
 define i16 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglb v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2

 ; CHECK-P8-NEXT:    xscvdpsxws f2, f0
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    xxswapd v2, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xxswapd v5, vs1
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
-; CHECK-P8-NEXT:    vmrglb v3, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    vmrghb v2, v4, v2
+; CHECK-P8-NEXT:    vmrghb v3, v5, v3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
-; CHECK-P9-NEXT:    xxswapd v4, vs0
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
+; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1

 ; CHECK-P8-NEXT:    xscvdpsxws f5, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f2
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs4
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs5
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs6
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v1, vs7
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs2
-; CHECK-P8-NEXT:    vmrglb v2, v5, v2
-; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    vmrglb v3, v0, v3
-; CHECK-P8-NEXT:    vmrglb v4, v6, v4
-; CHECK-P8-NEXT:    vmrglb v5, v5, v1
+; CHECK-P8-NEXT:    vmrghb v2, v0, v2
+; CHECK-P8-NEXT:    vmrghb v3, v1, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    vmrghb v4, v0, v4
+; CHECK-P8-NEXT:    vmrghb v5, v1, v5
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs3, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)

 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    lxvd2x vs11, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f12, f5
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
 ; CHECK-P8-NEXT:    xscvdpsxws f13, f7
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs4
-; CHECK-P8-NEXT:    mtvsrd f6, r4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f8
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f10
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mtvsrd f8, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r4
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f12
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f13
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mtvsrd f12, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    mtvsrd f13, r4
+; CHECK-P8-NEXT:    mtvsrd v6, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
-; CHECK-P8-NEXT:    mtvsrd v2, r3
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    mtvsrd v3, r3
+; CHECK-P8-NEXT:    mtvsrd v7, r4
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, v3
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v9, vs1
+; CHECK-P8-NEXT:    vmrghb v4, v8, v4
+; CHECK-P8-NEXT:    vmrghb v5, v9, v5
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f5
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v10, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f5, r3
+; CHECK-P8-NEXT:    vmrghb v0, v8, v0
+; CHECK-P8-NEXT:    vmrghb v1, v9, v1
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f9
-; CHECK-P8-NEXT:    mtvsrd f7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f11
-; CHECK-P8-NEXT:    vmrglb v4, v8, v4
-; CHECK-P8-NEXT:    xxswapd v8, vs3
-; CHECK-P8-NEXT:    vmrglb v5, v9, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    vmrglb v0, v10, v0
-; CHECK-P8-NEXT:    xxswapd v10, vs7
-; CHECK-P8-NEXT:    vmrglb v1, v8, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    vmrglb v6, v9, v6
-; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    vmrglb v7, v10, v7
-; CHECK-P8-NEXT:    vmrglb v2, v8, v2
-; CHECK-P8-NEXT:    vmrglb v3, v9, v3
+; CHECK-P8-NEXT:    vmrghb v6, v8, v6
+; CHECK-P8-NEXT:    vmrghb v2, v9, v2
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghb v3, v8, v3
+; CHECK-P8-NEXT:    vmrghb v7, v9, v7
 ; CHECK-P8-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v5, v1, v0
-; CHECK-P8-NEXT:    vmrglh v0, v7, v6
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
-; CHECK-P8-NEXT:    vmrglw v2, v2, v0
-; CHECK-P8-NEXT:    xxmrgld v2, v2, v3
+; CHECK-P8-NEXT:    vmrglh v2, v2, v6
+; CHECK-P8-NEXT:    vmrglh v3, v7, v3
+; CHECK-P8-NEXT:    vmrglw v4, v5, v4
+; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    xxmrgld v2, v2, v4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs7, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f8, f7
 ; CHECK-P9-NEXT:    xxswapd vs7, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f7
+; CHECK-P9-NEXT:    lxv vs6, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 112(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 96(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 80(r3)
 ; CHECK-P9-NEXT:    lxv vs3, 64(r3)
 ; CHECK-P9-NEXT:    lxv vs4, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs5, 32(r3)
-; CHECK-P9-NEXT:    lxv vs6, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    xxswapd v2, vs8
-; CHECK-P9-NEXT:    mtvsrd f7, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f6
 ; CHECK-P9-NEXT:    xxswapd vs6, vs6
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f5
 ; CHECK-P9-NEXT:    xxswapd vs5, vs5
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f5
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs7
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    mtvsrd f5, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs5
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f4
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    mtvsrd f5, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs5
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs4
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs3
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    vmrglh v3, v4, v3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
-; CHECK-P9-NEXT:    xxswapd v5, vs1
-; CHECK-P9-NEXT:    xxswapd v0, vs0
-; CHECK-P9-NEXT:    vmrglb v5, v5, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r3
+; CHECK-P9-NEXT:    vmrghb v5, v5, v0
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)

 
 define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
-; CHECK-P8-NEXT:    vmrglb v2, v2, v3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglb v2, v3, v2
+; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2

 ; CHECK-P8-NEXT:    xscvdpsxws f2, f0
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtvsrd v2, r3
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    xxswapd v2, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    xxswapd v5, vs1
-; CHECK-P8-NEXT:    vmrglb v2, v3, v2
-; CHECK-P8-NEXT:    vmrglb v3, v5, v4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
+; CHECK-P8-NEXT:    vmrghb v2, v4, v2
+; CHECK-P8-NEXT:    vmrghb v3, v5, v3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs1
-; CHECK-P9-NEXT:    xxswapd v4, vs0
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    vmrglh v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
+; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1

 ; CHECK-P8-NEXT:    xscvdpsxws f5, f1
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f2
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f3
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    xxswapd v2, vs4
+; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs5
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    xxswapd v4, vs6
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v1, vs7
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v5, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    xxswapd v6, vs2
-; CHECK-P8-NEXT:    vmrglb v2, v5, v2
-; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    vmrglb v3, v0, v3
-; CHECK-P8-NEXT:    vmrglb v4, v6, v4
-; CHECK-P8-NEXT:    vmrglb v5, v5, v1
+; CHECK-P8-NEXT:    vmrghb v2, v0, v2
+; CHECK-P8-NEXT:    vmrghb v3, v1, v3
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mtvsrd v1, r4
+; CHECK-P8-NEXT:    vmrghb v4, v0, v4
+; CHECK-P8-NEXT:    vmrghb v5, v1, v5
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mfvsrd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs3, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
+; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
-; CHECK-P9-NEXT:    lxv vs2, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs1
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs1
-; CHECK-P9-NEXT:    xxswapd v5, vs0
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    mtvsrd v5, r3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)

 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    lxvd2x vs11, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f12, f5
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
 ; CHECK-P8-NEXT:    xscvdpsxws f13, f7
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
+; CHECK-P8-NEXT:    mfvsrwz r3, f4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    xxswapd v4, vs4
-; CHECK-P8-NEXT:    mtvsrd f6, r4
+; CHECK-P8-NEXT:    mtvsrd v4, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f8
+; CHECK-P8-NEXT:    mtvsrd v5, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f10
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mtvsrd f8, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r4
+; CHECK-P8-NEXT:    mtvsrd v0, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, f12
+; CHECK-P8-NEXT:    mtvsrd v1, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f13
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mtvsrd f12, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    mtvsrd f13, r4
+; CHECK-P8-NEXT:    mtvsrd v6, r3
+; CHECK-P8-NEXT:    mfvsrwz r3, v2
+; CHECK-P8-NEXT:    mtvsrd v2, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
-; CHECK-P8-NEXT:    mtvsrd v2, r3
-; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
-; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    mtvsrd v3, r3
+; CHECK-P8-NEXT:    mtvsrd v7, r4
+; CHECK-P8-NEXT:    mfvsrwz r3, f0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v3, v3
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    xxswapd v9, vs1
+; CHECK-P8-NEXT:    vmrghb v4, v8, v4
+; CHECK-P8-NEXT:    vmrghb v5, v9, v5
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f5
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    xxswapd v10, vs2
 ; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f5, r3
+; CHECK-P8-NEXT:    vmrghb v0, v8, v0
+; CHECK-P8-NEXT:    vmrghb v1, v9, v1
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
 ; CHECK-P8-NEXT:    mfvsrwz r3, f9
-; CHECK-P8-NEXT:    mtvsrd f7, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, f11
-; CHECK-P8-NEXT:    vmrglb v4, v8, v4
-; CHECK-P8-NEXT:    xxswapd v8, vs3
-; CHECK-P8-NEXT:    vmrglb v5, v9, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    vmrglb v0, v10, v0
-; CHECK-P8-NEXT:    xxswapd v10, vs7
-; CHECK-P8-NEXT:    vmrglb v1, v8, v1
-; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    vmrglb v6, v9, v6
-; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    vmrglb v7, v10, v7
-; CHECK-P8-NEXT:    vmrglb v2, v8, v2
-; CHECK-P8-NEXT:    vmrglb v3, v9, v3
+; CHECK-P8-NEXT:    vmrghb v6, v8, v6
+; CHECK-P8-NEXT:    vmrghb v2, v9, v2
+; CHECK-P8-NEXT:    mtvsrd v8, r3
+; CHECK-P8-NEXT:    mtvsrd v9, r4
+; CHECK-P8-NEXT:    vmrghb v3, v8, v3
+; CHECK-P8-NEXT:    vmrghb v7, v9, v7
 ; CHECK-P8-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v5, v1, v0
-; CHECK-P8-NEXT:    vmrglh v0, v7, v6
-; CHECK-P8-NEXT:    vmrglh v2, v3, v2
-; CHECK-P8-NEXT:    vmrglw v3, v5, v4
-; CHECK-P8-NEXT:    vmrglw v2, v2, v0
-; CHECK-P8-NEXT:    xxmrgld v2, v2, v3
+; CHECK-P8-NEXT:    vmrglh v2, v2, v6
+; CHECK-P8-NEXT:    vmrglh v3, v7, v3
+; CHECK-P8-NEXT:    vmrglw v4, v5, v4
+; CHECK-P8-NEXT:    vmrglw v2, v3, v2
+; CHECK-P8-NEXT:    xxmrgld v2, v2, v4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv vs7, 0(r3)
 ; CHECK-P9-NEXT:    xscvdpsxws f8, f7
 ; CHECK-P9-NEXT:    xxswapd vs7, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f7
+; CHECK-P9-NEXT:    lxv vs6, 16(r3)
 ; CHECK-P9-NEXT:    lxv vs0, 112(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 96(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 80(r3)
 ; CHECK-P9-NEXT:    lxv vs3, 64(r3)
 ; CHECK-P9-NEXT:    lxv vs4, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs5, 32(r3)
-; CHECK-P9-NEXT:    lxv vs6, 16(r3)
 ; CHECK-P9-NEXT:    mfvsrwz r3, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r3
+; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    xxswapd v2, vs8
-; CHECK-P9-NEXT:    mtvsrd f7, r3
-; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f6
 ; CHECK-P9-NEXT:    xxswapd vs6, vs6
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
+; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r3
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f5
 ; CHECK-P9-NEXT:    xxswapd vs5, vs5
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f5
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    vmrglb v2, v2, v3
-; CHECK-P9-NEXT:    xxswapd v3, vs7
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    mtvsrd f5, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs5
+; CHECK-P9-NEXT:    mtvsrd v3, r3
+; CHECK-P9-NEXT:    mfvsrwz r3, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f4
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    mtvsrd f5, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs5
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    vmrglw v2, v3, v2
+; CHECK-P9-NEXT:    mtvsrd v3, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
+; CHECK-P9-NEXT:    vmrghb v3, v3, v4
 ; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    xxswapd v3, vs4
-; CHECK-P9-NEXT:    vmrglb v3, v3, v4
-; CHECK-P9-NEXT:    xxswapd v4, vs3
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
-; CHECK-P9-NEXT:    vmrglh v3, v4, v3
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    vmrglh v3, v4, v3
+; CHECK-P9-NEXT:    mtvsrd v4, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
+; CHECK-P9-NEXT:    vmrghb v4, v4, v5
 ; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtvsrd v5, r3
 ; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    vmrglb v4, v4, v5
-; CHECK-P9-NEXT:    xxswapd v5, vs1
-; CHECK-P9-NEXT:    xxswapd v0, vs0
-; CHECK-P9-NEXT:    vmrglb v5, v5, v0
+; CHECK-P9-NEXT:    mtvsrd v0, r3
+; CHECK-P9-NEXT:    vmrghb v5, v5, v0
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

entry:
   %1 = sitofp <2 x i16> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }
 
 define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    vspltisw v3, 8
-; CHECK-P8-NEXT:    xxswapd v2, vs0
+; CHECK-P8-NEXT:    vmrghh v2, v2, v2
 ; CHECK-P8-NEXT:    vadduwm v3, v3, v3
-; CHECK-P8-NEXT:    vmrglh v2, v2, v2
 ; CHECK-P8-NEXT:    vslw v2, v2, v3
 ; CHECK-P8-NEXT:    vsraw v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    vmrglh v2, v2, v2
+; CHECK-P9-NEXT:    mtvsrd v2, r3
+; CHECK-P9-NEXT:    vmrghh v2, v2, v2
 ; CHECK-P9-NEXT:    vextsh2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v2

llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxmrglw v2, v2, v2
+; CHECK-P8-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-P8-NEXT:    xvcvuxwdp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    xxmrglw v2, v2, v2
+; CHECK-P9-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-P9-NEXT:    xvcvuxwdp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvuxwdp v2, v2
entry:
   store <16 x double> %1, <16 x double>* %agg.result, align 128
   ret void
 }
 
 define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxmrglw v2, v2, v2
+; CHECK-P8-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-P8-NEXT:    xvcvsxwdp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd f0, r3
-; CHECK-P9-NEXT:    xxswapd v2, vs0
-; CHECK-P9-NEXT:    xxmrglw v2, v2, v2
+; CHECK-P9-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-P9-NEXT:    xvcvsxwdp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvsxwdp v2, v2

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 }
 
 define <1 x float> @constrained_vector_ceil_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI103_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI103_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %ceil
 }
 

 }
 
 define <1 x float> @constrained_vector_floor_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI107_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI107_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %floor
 }
 

 }
 
 define <1 x float> @constrained_vector_round_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_round_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI111_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI111_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %round
 }
 

 }
 
 define <1 x float> @constrained_vector_trunc_v1f32() #0 {
 ; PC64LE-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI115_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI115_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
                                <1 x float> <float 1.5>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %trunc
 }
 

llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

 ; CHECK-P9-VECTOR-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-VECTOR-NEXT:    xxpermdi v2, vs0, vs1, 1
 ; CHECK-P9-VECTOR-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testi0:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lfd f1, 0(r4)
 ; CHECK-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xxpermdi vs1, f1, f1, 2
+; CHECK-P9-NEXT:    xxswapd vs1, f1
 ; CHECK-P9-NEXT:    xxpermdi v2, vs0, vs1, 1
 ; CHECK-P9-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %p1
   %s = load double, double* %p2
   %r = insertelement <2 x double> %v, double %s, i32 0
   ret <2 x double> %r
 
 

 ; CHECK-P9-VECTOR-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-VECTOR-NEXT:    xxmrgld v2, vs1, vs0
 ; CHECK-P9-VECTOR-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testi1:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lfd f1, 0(r4)
 ; CHECK-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xxpermdi vs1, f1, f1, 2
+; CHECK-P9-NEXT:    xxswapd vs1, f1
 ; CHECK-P9-NEXT:    xxmrgld v2, vs1, vs0
 ; CHECK-P9-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %p1
   %s = load double, double* %p2
   %r = insertelement <2 x double> %v, double %s, i32 1
   ret <2 x double> %r