[PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

[nemanjai]

Summary

We currently emit incorrect codegen for this constraint because we set it as a constraint that allows registers. This will cause the value to be copied to the stack and that address to be passed as the address. This is not what we want.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=42762

[amyk]

clang/lib/Basic/Targets/PPC.h

277

Just curious, but does this case still require Info.setAllowsMemory(); as well?

[nemanjai]

clang/lib/Basic/Targets/PPC.h

277

I don't want to change the behaviour of a QPX-specific asm constraint, so I'd rather leave it as-is. Q will set both, Z will only set "memory".

[lei]

LGTM

[amyk]

clang/lib/Basic/Targets/PPC.h

277

I see. Thanks for explaining.

clang/test/CodeGen/ppc64-inline-asm.c

50

Missing a k in CHECK?

[stefanp]

Other than the two missing Ks in the test case as Amy pointed out LGTM.

[nemanjai]

clang/test/CodeGen/ppc64-inline-asm.c

50

Great catch! Thank you.

clang/lib/Basic/Targets/PPC.h

case 'e':
       // es: A "stable" memory operand; that is, one which does not
       // include any automodification of the base register. Unlike
       // `m', this constraint can be used in asm statements that
       // might access the operand several times, or that might not
       // access it at all.
       Info.setAllowsMemory();
       Name++; // Skip over 'e'.
       break;
     case 'Q': // Memory operand that is an offset from a register (it is
               // usually better to use `m' or `es' in asm statements)
+      Info.setAllowsRegister();
+      LLVM_FALLTHROUGH;
     case 'Z': // Memory operand that is an indexed or indirect from a
               // register (it is usually better to use `m' or `es' in
               // asm statements)
       Info.setAllowsMemory();
-      Info.setAllowsRegister();
       break;
     case 'R': // AIX TOC entry
     case 'a': // Address operand that is an indexed or indirect from a
               // register (`p' is preferable for asm statements)
     case 'S': // Constant suitable as a 64-bit mask operand
     case 'T': // Constant suitable as a 32-bit mask operand
     case 'U': // System V Release 4 small data area reference
     case 't': // AND masks that can be performed by two rldic{l, r}

clang/test/CodeGen/ppc64-inline-asm.c

 }
 
 double test_fmax(double x, double y) {
   asm("xsmaxdp %x0, %x1, %x2" : "=ws"(x) : "ws"(x), "ws"(y));
   return x;
 // CHECK-LABEL: double @test_fmax(double %x, double %y)
 // CHECK: call double asm "xsmaxdp ${0:x}, ${1:x}, ${2:x}", "=^ws,^ws,^ws"(double %x, double %y)
 }
+
+void testZ(void *addr) {
+  asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)addr) : "memory");
+// CHECK-LABEL: void @testZ(i8* %addr)
+// CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8* %addr)
+}
+
+void testZwOff(void *addr, long long off) {
+  asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)(addr + off)) : "memory");
+// CHECK-LABEL: void @testZwOff(i8* %addr, i64 %off)
+// CHECK: %[[VAL:[^ ]+]] = getelementptr i8, i8* %addr, i64 %off
+// CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8* %[[VAL]])
+}